CMOS Bulk Input Current Switch Logic Circuit

Hong-Yi Huang, *Chun-Tsai Hung and Sheng-Chia Chiang

hyhuang@mail.ntpu.edu.tw Graduate Institute of Electrical Engineering, National Taipei University, Taiwan

*Department of Electronic Engineering, National ShaLu Industrial Vocational Senior High School, Taiwan.

Abstract—In this work, the CMOS bulk-input current

switch logic (BCSL) circuit is proposed. A negative (positive) boost circuit providing a voltage level for NMOS (PMOS) bulk terminal is also developed to avoid the forward biasing of drain/source-to-bulk junctions. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to low parasitic resistive and capacitive load. The dynamic power is reduced. The BCSL has the potential of low-power and high-speed operation in low-voltage design. It is shown that the BCSL has better speed and power performance compared to the conventional differential logic circuits in simulation results.

I. INTRODUCTION

A MOSFET has four terminals, including source, gate, drain and bulk. A signal transmitted from drain to source can be well controlled by gate signal in the conventional CMOS logic. For traditional design, the bulk terminal is connected to a highest (PMOS) or lowest (NMOS) level of the power supply or the source terminal to avoid the forward biasing of source/drain-to-bulk p/n junction.

The conventional static CMOS logic circuits [1]-[2] are constructed with the same number of NMOS and PMOS transistors in a gate. There is no dc power dissipation. The noise margin is excellent. The pseudo-NMOS logic [3] uses a PMOS load to replace the PMOS logic network of the CMOS logic circuit. The transistor number, the capacitive load and the layout area of the pseudo-NMOS logic can be reduced. The pass transistor logic (PTL) [4] has its control signal and input/output signals connected to gate and source/drain, respectively. The PTL has advantages over the standard CMOS designs in terms of layout density, circuit delay and power consumption. The domino logic [5] is a dynamic circuit in which the precharging and evaluating clock scheme is adopted. The domino logic circuit achieves great chip-area saving by using only one PMOS device in each dynamic gate.

The differential cascode voltage switch (DCVS) logic uses only two cross-coupled PMOS devices as the loads [6]-[7]. The differential inputs are connected to the NMOS differential logic network to generate a pair of complementary outputs. The differential current switch logic (DCSL) [8]-[9] is known to have the advantage of low power consumption by restricting the internal voltage swing of the logic network. The evaluating phase of differential logic circuits is improved using a sense amplifier. However, all of the conventional logic

families require cascaded devices in the logic network [1]-[9]. The precharging phase becomes the bottle neck of the operation when the logic complexity increases.

The current latch sense amplifier [10] is sensitive to the current difference at two-sides of the input devices. It generates a pair of full-voltage output signals without dc power dissipation. Combining the current latch sense amplifier with the threshold logic [11], the differential logic network is designed without cascoding of the input devices. The parallelism of the input devices results in lower resistive path from outputs to GND. Thus the delay can be reduced, as the complexity of the logic increases.

The devices in the differential logic network of the bulk input differential logic (BIDL) [12] are connected in parallel, leading to a low parasitic resistive and capacitive load [13]. The source/drain-to-bulk junction has a possible forward bias problem. An improved boost circuit to avoid the possible forward biasing problem is proposed. A scheme to restrict the voltage swing is also developed to reduce the dynamic power consumption.

II. BULK INPUT CURRENT SWITCH LOGIC

To produce signal swings suitable for NMOS and PMOS bulk terminals without forward biasing of source/drain-to-bulk junctions, the negative and positive boost circuits are proposed as shown in Fig. 1(a) and Fig. 2(a). Fig. 1(b) depicts that Vn is lowered to GND and –VOL. Fig. 2(b) illustrates that Vp is raised to VDD and VOH.

Fig .1. (a) Negative boost circuit (NBC) and (b) waveforms.

The wire-OR and wire-NAND functions can be realized using combination of multiple NBCs shown in Fig. 3. When the input signal are given by A , B andC , the output is A B C+ + . When the input signals are given

by A , B and C , the output is A B C+ + that equals to

A B Ci i . The wire-AND and wire-NOR functions can be implemented using combination of multiple PBCs shown

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in Fig. 4. When the input signal are given by A , B and C , the output is A B Ci i . When the input signals are

given by A , B and C , the output is A B Ci i that equals

to A B C+ + .

Fig. 2. (a) Positive boost circuit (PBC) and (b) waveforms.

Fig. 3.3-input wire-OR and wire-NAND functions of NBC.

Fig. 4. 3-input wire-AND and wire-NOR functions of PBC.

Fig. 5 depicts the proposed bulk-input current switch

logic (BCSL) with NMOS logic differential network. When φ is logical “0”, the outputs Q and Q are precharged to VDD. When φ makes a low-to-high transition, the BCSL turns to the evaluation phase. The discharging paths of Q and Q are turned on. The current IL denotes the summation of the current on the left side of the differential NMOS network while the current IR denotes the current on the right side. The current difference of IL and IR is then amplified by the cross-coupled devices M P1, M P2 and the two NMOS differential network. If IL is exceeds IR, then Q is charging to VDD and Q is discharging to GND. If IL is smaller than IR, then Q is discharging to GND and Q is charging to VDD.

Therefore, the dynamic power consumed by charging and discharging of internal nodes is reduced. A current latch sense amplifier is used to generate a pair of full-swing output signals Q and Q without dc power dissipation. The logic network is designed without cascoding of devices. The resistive path from output to VDD has only one-stacked PMOS devices.

Fig. 6 depicts The BCSL with PMOS differential

network. When φ is logical “1”, the outputs Q and Q are precharged to GND. When φ makes a high-to-low transition, the BCSL turns to the evaluation phase. The PMOS logic network has a similar operation to the NMOS logic network. The resistive path from output to VDD has only two-stacked PMOS devices resulting in an improvement of delay at the evaluation phase.

Fig. 5. BCSL with NMOS logic network.

Fig. 6. BCSL with PMOS logic network.

In Fig. 5, the input signals are connected to the bulk

terminals of the NMOS differential network whose devices are connected in parallel. Each NMOS device in the logic network requires an individual p-well to control its bulk terminal. A p-well or a triple-well CMOS process is necessary for this design. A negative boost circuit shown in Fig. 1(a) transferring the voltage swing is connected to the bulk terminal of the NMOS input device. The substrate bias has two states. In Fig. 6, each PMOS device in the logic network requires an individual n-well to control its bulk terminal. An n-well CMOS process is necessary for this design. A positive boost circuit is connected to the bulk terminal of the PMOS input device shown in Fig. 2(a).

III. DESING EXAMPLES AND COMPARISONS

The procedures to implement a carry out gate by using the BCSL with NMOS logic network are consisted with the following steps: The NMOS logic network can be obtained by inducing the K-map rules from the truth table shown in Table I. The concepts are as following: when there are either two or three 1s in the input signal, the carry out is then shifted forward by 1 bit. In the logic network, the design procedure is different from those from the NAND gate or NOR gate. By the rules, the logic network can be implemented as shown in Fig. 7, in which Vn1, Vn3and Vn5 are the output signals of A , B and C , respectively, after NBC; Vn2, Vn4 and Vn6 are the output

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signals of A , B andC , respectively, after NBC by the same manner.

TABLE I

TRUTH TABLE AND LOGIC TREE REASONING OF CARRY-OUT GATE

Fig. 7. Carry-out gate.

The overall circuit analysis of Fig. 7 is as follows: given

that φ is logical ”0”, the outputs Q and Q are precharged to VDD, and when φ makes a low-to-high transition, the BCSL turns to the evaluation phase. When there are two or more 1s in the input signals, MN1 to MN6 are all turned on. Meanwhile there’s at most one MOSFET with the body effect among MN1, MN3 and MN5; but two or more having the body effect among MN2, MN4 and MN6, so that IL=IDS1+IDS3+IDS5 is greater than IR=IDS2+IDS4+IDS6. After being amplified by the sense amplifier, MN2, MN4 and MN6 turned off gradually, charging the output Q to VDD; MN1, MN3 and MN5 keep turn on persistently, discharging Q to GND.

When there are two or more 0s within the input signals, MN1 to MN6 are all turned on. There are two or more MOSFETs among MN1, MN3 and MN5 with body effects; but at most one among MN2, MN4 and MN6 with the body effect. So that IL=IDS1+IDS3+IDS5 is less than IR =IDS2+IDS4+IDS6. After being amplified by sense amplifier, MN1, MN3 and MN5 turned off gradually, charging the output Q being charged to VDD; Hence MN2, MN4 and MN6 keep turned on persistently, discharging Q to GND. The status of the circuit is listed in Table II.

The procedures for designing schematics of 3-input NAND/AND gate by using BCSL with NMOS logic network (Fig. 8.) are as follows: Using the circling and simplifying methods of K-map from the truth table (Table III) to design an n-type logic network. In K-map, eclipses and rectangles represent the 0-loop and 1-loop,

respectively. 0-loop is when inputting ABC =111, the output Q=0. The logic function on the right side network is noted as A B Ci i , the right logic network can be implemented by using three parallel NMOS; 1-loop, which are represented as rectangles, indicating that the output Q=1 when any of the input ABC equals 0. The 1-loop

can be simplified into 3 elements: A , B and C , respectively.

TABLE II

TRUTH TABLE AND STATE TRANSITIONS OF CARRY-OUT GATE

TABLE III TRUTH TABLE AND LOGIC TREE REASONING OF NAND/AND GATE

Using wire-OR is able to implement the left logic

network. In order to retrieve the correct sampling from both sides of the network, the device widths of the logic network are designed to fit the equation: WMN1=3WMN2=3WMN3=3WMN4, i.e. IDS2=IDS3=IDS4= 1/3IDS1. The analysis of the circuit shown in Fig. 8 is as follows: given that φ=0 and the circuit performs Q=Q=1, and the circuit begins to evaluate when φ turns to 1 from 0: When inputting signal ABC =111, although MN1, MN2, MN3, and MN4 are all on due to Vn1= -VOL, Vn2=Vn3=Vn4=0V; body effect of MN1 exists, thus makes IL=IDS1 to be less than IR =IDS2+IDS3+IDS4. After being amplified and compared by sense amplifier, MN1 turns off gradually, which makes output Q charges to VDD; MN2, MN3, and MN4 keep turn on, which make Q discharge to GND.

When any of the input signals to be 0, there’s at least one of Vn2, Vn3, Vn4 to be -VOL due to Vn1=0V, which means MN1 is on and without body effect, and the same as MN2, MN3,and MN4 but with body effects. Thus makes IL to exceed IR. After being amplified and compared by sense amplifier, MN1 keeps turn on, which makes output Q being

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discharged to GND; MN2, MN3, and MN4 turned off gradually, which make Q being charged to VDD.

Fig. 8. Three input NAND/AND gate.

The BCSL circuit can be applied to a pipelined system

shown in Fig. 9. Both P-section and N-section are controlled by a true-single-phase clock φ. When φ transits from VDD to GND, the sense amplifier of the P-section is enabled. A pair of full-swing signals 1Q and

1Q is transmitted to the NMOS differential logic network of the next N-section. When φ transits from GND to VDD, the sense amplifier of the N-section is enabled. A pair of full-swing signals

2Q and 2Q is transmitted to the PMOS

differential logic network of the next P-section.

Fig. 9. Pipelined structure composed of P-section and N- section

BCSL circuit

The 0.18um single-poly six-metal triple-well CMOS device models are used for SPICE simulation. The operating clock frequency is 1 GHz. The supply voltage is 1.8 V. Table IV compares the power dissipations and the delay time for various differential logic circuits. The BCSL exhibits improved speed, power, and power-delay product.

IV. CONCLUSIONS

In this work, a new CMOS differential logic called bulk input current switch logic is presented and analyzed. New positive and negative boost circuits are proposed to generate the bulk voltage for the input devices without forward biasing of the source/drain-to-bulk junctions. The devices of the logic network are connected in parallel resulting in lower parasitic resistance and capacitance. It is proved that the BCSL has better speed and power performance compared to the other differential logic circuits.

TABLE IV COMPARISONS OF DIFFERENTIAL LOGIC CIRCUITS

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