2007 4th International Conference on Electrical and Electronics Engineering (ICEEE 2007)

IJu J

Model for a CMOS Bit-Level Product Cell

Yesenia E. Gonzalez-Navarro, Felipe Gomez-Castafieda, Jose A. Moreno-Cadenas,Luis M. Flores-Nava, Oliverio Arellano-Cardenas

VLSI Lab., Solid-State Electronics Section, Department of Electrical Engineering, CINVESTAV-IPN, Mexico City,Mexico

Phone: 52 (55) 50613800 ext. 6261 Fax: 52 (55) 50613978 e-mail: ygonzalezgsees.cinvestav.mxAbstract An analysis method for a bit-level product cell

used for vector-matrix multiplications is presented. The cell isa combination of a charge injection binary multiplier and ananalog accumulator. CID/CCD principles help to understandthe cell function and MOS structure equations are used todescribe the cell operations.

Keywords CCD, CID, CMOS, MOS, product cell,vector-matrix multiplication (VMM)

I. INTRODUCTION

Different systems for pattern recognition like NeuralNetworks (NN) or Support Vector Machines (SVM) basetheir function in vector-matrix multiplications (VMM) so,new dedicated parallel VLSI architectures have beendeveloped to speed up VMM computation [1], [2].

The goal is to solve the equation

Ny(in) = >W(m,n)X(n)

n=l(1)

illustrated in Fig. 2; but, actually, the physical structure isconstructed like a CMOS CCD, where there is no anydiffusion between the control or output gates. This workfocuses in the analysis and modeling of the product cellfunction for an n-well CMOS process combining three-terminal MOS structure equations and CCD principles toprovide an analysis model for the structure.

(in) (in) (in)Y1,1 Y1,2 . Yl,

I I

w5rn2)

I Y2,2n)(n) (in)Y2,1l y22 .. *Y2,J

(YIn) (in) (In)yIJ yI,2 ...YIJ

with N-dimensional input vector X(n) , M-dimensionaloutput vector (in) and M XN matrix elements

W(m,n) computing inner-products between the input vectorand the prototype or template vectors in W (rows of W).

Some VMM architectures [3], [4] propose single CMOSbit-level product cells to solve (1), resulting in an efficientway to avoid the problem. In this architecture each elementof the input vector X(n)and W(m,n) is binary encoded.Encoding with I-bits the real value matrix elements andencoding with J-bits the real value input elements, thebinary-binary VMM partial product results

N(m) = E (m,n)X (n)

Y2,j >1 i=l

l X (1)

| (1)1x,

x(2)JI

x(2)1 2(2)lx

(n)

2Ji

I x(n)1 2I x(n

I

Fig. 1. Block diagram of the m-row ofW with I-bits binary encoded

elements Wi) ,a serial input vector X with J-bit encoded

(n) (in)elements X and the corresponding partial product outputs 321,]

W, i

SEr(2)

The partial products obtained of the bit-level productcells in the same row are accumulated in an output line andthese quantized results can be manipulated in the digitaldomain. Fig. 1 depicts one row of a matrix W and an inputvector X with binary encoding elements. The bit resolutionof the matrix elements in W can differ from the bitresolution of the input vector elements in X.

A model is provided in the literature [1] to represent theelectrical operation of the CMOS bit-level product cell. Themodel contains three MOS transistors connected in series,

Xi

T I T

Ml M M3

SET xj

*vout

Vout

Fig. 2. Electrical representation of a binary-binary unit cell (top). Physicalstructure ofthe bit-level product cell (bottom).

1-4244-1166-1/07/$25.00 ©2007 IEEE.385 IEEE Catalog Number: 07EX1762C

ISBN: 1-4244-1166-1Library of Congress: 2007923398

,

-I ))~ I'1

I _

I

w M,I

w M,

A A

W.

. . .

t i

2007 4th International Conference on Electrical and Electronics Engineering (ICEEE 2007)

IJu J

II. BIT-LEVEL PRODUCT CELL

A. General description

The bit-level product cell computes one argument of thesum in (2). The cell stores one bit of the matrix element

w(n,n) and performs a one quadrant binary-binary

multiplication of w(mn) and xi". For an array of

w(m,n) cells with common m and i indexes having their

output nodes connected at the same point and, a vector x(n)with j values presented in sequence over time, the resulting

products y (i) are accumulated in the time at the output

node.

B. Cell operation

When a matrix element value w(nn) is stored, the

voltage applied to the SET gate is held at GND. A VDD

voltage applied to w(m)represents a logic "0" and an

applied voltage level smaller than VDD represents a logic

"1". For x() values, a VDD voltage level applied to this

gate represents a logic "1" and a GND voltage levelrepresents a logic "0".

The cell operation can be analyzed combining ChargeInjection Devices (CID) and Charge Coupled Devices(CCD) principles. That is, there is a charge quantity injectedby the w(nn) electrode and the correct manipulation of the

SET and x(n) control gates allows that this charge be

transferred to the area bellow the VOWt control gate [5]. The

charge quantity in the area under the VOWt gate will induce aproportional voltage level at this gate. The voltage levelobtained at VOWt represents the resultant product operation.

Fig. 3 describes a bit-level product of w(m,n) and x(n,

when a logic "1" is applied to w(n,n) (a level voltage of

VDD /2 is used) and a logic "1" is applied to x("). The

Compute operation starts when a VDD voltage level is held

at the SET control gate. After the SET control gateallows that the charge injected be transferred to the area

under the x(n) gate, the voltage applied to the SET control

gate returns to GND . During the first three clock times, the

VOWt node is held at a VDD / 2 voltage level and in the last

1-4244-1166-1/07/$25.00 ©2007 IEEE.

clock time, the V0u1 gate is floating and its voltage levelonly depends on the charge quantity transferred to the area

under the Vout gate.

W. r) SET x(")ut

/ GND-VDD/2-VDDA GND-VDD/2-VDDA GND-VDD/2-VDD

/ GND-VDD/2-Vnn

386

y -LvUUtime

Fig. 3. Bit-level product cell operation analyzed by charge injection andcharge transfer theories.

C. Analysis ofthe structure

According to Fig. 3, the operation of the bit-levelproduct cell can be modeled like a CID/CCD structure,where the injected charge by the diffusion electrode istransferred to the output electrode (VOu1). To really modelhow much charge quantity is injected and which is thecorresponding V0u1 voltage level, the structure of Fig. 3 willbe divided for analysis in two new structures, see Fig. 4.One is a three-terminal MOS structure that is used to modelthe charge injection phenomenon controlled by the diffusionelectrode and the SET gate electrode (the third terminal isthe substrate). The second structure is a MOS capacitor,used to model the output voltage level according to theinjected charge. The xj gate can be modeled as a single

switch allowing or blocking the transfer of charge. An n-well process is used for the analysis but the resultingequations can be equally valid for a p-well process if bothsignals and technology parameters are considered.

wi SET Xj vout

V- -~11 AI - -= 1-

Three-terminal MOS MOS capacitor structurestructure

Fig. 4. Proposed structures to model the bit-level product cell.

IEEE Catalog Number: 07EX1762CISBN: 1-4244-1166-1Library of Congress: 2007923398

2007 4th International Conference on Electrical and Electronics Engineering (ICEEE 2007)

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D. Charge injection model From (4.1), (4.2) and (4.3) we have:

A two-terminal MOS structure (MOS capacitor)operates in three basic regions: accumulation, depletion andinversion. The operation region depends basically on thegate potential applied to the structure and its effect in thesurface potential, yJ . For a three-terminal MOS structure,the operation region is a function of two control electrodes,one at the n+-diffusion and another at the gate.

To properly operate the structure, a reverse potential(w(mn) value) is applied at the n+-diffusion, causing freecarriers at p-region been attracted to the junction inproportion to the reverse voltage level, so, to form aninversion layer at the p-region, the potential level at the SETgate will be larger than in a MOS capacitor structure [6] andthe surface potential at the onset of strong inversion will begiven by

i, (inv) = V, + 20,, (3)Where V. denotes the reverse voltage applied to the

junction and OFP is the Fermi potential for a p-region.A two-terminal MOS structure operating in inversion

region is characterized by five equations [7]

VGB =wox + Ys + OMS (4.1)QG + QO+ QI + QB =O (4.2)QG COXYOX (4.3)QB = 2qcz:Na Vs (4.4)

QI -2qFs Na( + Vse-(4.5)

Where VGB is the voltage applied to the gate, Vox is the

potential drop across the oxide, OMS is the metal-

semiconductor workfunction difference, QG , QB and QIare charges per unit area on gate, in the semiconductor areaunder the oxide and in the inversion layer, respectively. Q0is the effective interface charge per unit area, COX is the

oxide capacitance per unit area, q is the electron charge, Esis the permittivity of silicon, Na is the acceptor

concentration and /5t is the thermal voltage.The first four equations above are also valid for a three

terminal MOS structure, difference occurs for QI becausenow the charge quantity in the inversion layer is affected bythe Vr voltage:

- VJ)(5)

V =V 1/W _QB (VFs ) + QI (VFs )VGB =VFB +YVs -Q()QI )

oxWhere VFB is the flat-band voltage defined by

VFB =MS -

ox

(6)

(7)

Equation (4.4) can be redefined by

QB Y-rCOX Vs (8)Where 7 is the body effect coefficient or body factordefined by

2q.Fs Nar ~~~~~~~~~~(9)ox

Using (5) and (8) in (6), VGB can be written as

VGB VFB + V's + y[yt, + (2OF,+V)]/,(f0)The equation above is important because it gives a

relation between VGB, V1 and yJV,. Knowing the value of

yJ for a given value of VGB and Vr, we can obtain the

different charge quantities in the structure. So, the value QIcalculated from (5) should be considered as the injectedcharge in the structure, due to the applied voltages on the n+-diffusion and the SET gate.

E. MOS capacitor structure

The product and accumulate operations of the cell(injected charge and transferred or blocked charge) arecompleted by capacitively sensing the amount of chargeunder the VOWt gate (output summing node). The operationis given by

t =Cout

(1 1)

Where Cout is the total capacitance looked at the VOWtelectrode.

III. SIMULATION RESULTS

Equation (10) cannot be explicitly solved for yJ,, thatis why it is numerically solved. MATLAB programminglanguage was used to emulate the bit-level product process.The cell has four control ports: w(m<n), SET, x n andi i~~~~~~

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ISBN: 1-4244-1166-1Library of Congress: 2007923398

-(20,,+V,)] I 0,Q, = 2qv,Na

2007 4th International Conference on Electrical and Electronics Engineering (ICEEE 2007)

IJu J

VOut . Simulations parameters were available from MOSIS,for a 1.2pm, CMOS process.

Table I presents some data values used for simulations,table II shows the transferred charge per unit area and thecorresponding output level voltage when a logic "1" or a

logic "0" is presented at W (m ,n) and Xn For w(m,n), a

logic "1" is represented by VDD /2 and a zero-level I

VDD . For XJ, a logic "1" is represented by VDDand a loE

"0" by GND. A 5V power supply is used.

TABLE IUSED PARAMETERS

V - 1.2085VFB7 0.3341V'/2

¢,~' 0.3266V

Na 4.13282el5cm-3

d 3.17e-6cm

TABLE IIPRODUCT CELL SIMULATION RESULTS

(m n) x(in) Qtransf Vout

O O OC/cm2 OV

0 1 -3.8577e-14C/cm2 3.4806e-7V1 0 OC/cm2 OV

1 1 -2.4803e-7C/cm2 2.2378V

Fig. 5 represents a five-cell array with the outpconnected at the same node. Linearity of the systemobserved according to the number of cells with a logicproduct result.

2.5 -

L2-

- 1-

0 -

Poly Poly2 SiO21- 'I.

SET-by

gic vout

Fig. 6. Bit-level product cell diagram in a standard n-well, double polyCMOS process (top). Layout design (bottom).

IV. CONCLUSIONS

A model for a CMOS bit-level product cell is presented.The analysis is based on CID/CCD theories. Equations fortwo and three terminal MOS structures are used to describethe cell operation. The model allows previous knowledge ofthe injected charge quantity and its proportional voltage atthe output as well, according to the voltage values at thecontrol electrodes. Simulation results fit well with thedescribing cell function, and also, for a group of cells withthe output node connected at the same point, it shows alinear behavior with an increasing/decreasing voltage value,according to their product operations. Results obtained inthe present work are the base for future developments to

put create an electrical macromodel for the bit-level productis cell.

'1"ACKNOWLEDGMENT

This work was partially supported by Consejo Nacionalde Ciencia y Tecnologia (CONACYT), Mexico.

REFERENCES

u W'0 1 2 3

Cells with a logic one product result

4 5

Fig. 5. Linearity test for a bit-level 5-cell array.

Fig. 6 shows the bit-level product cell using a standardn-well, double poly CMOS process (top) and the layoutdesign of the cell using 1.2pm design rules (bottom).

1-4244-1166-1/07/$25.00 ©2007 IEEE.388

[1] R. Genov, G. Cauwenberghs, "Charge-mode parallel architecture forvector-matrix multiplication", IEEE Trans. Circuits Syst. II, vol. 48,no. 10, pp. 930-936, Oct. 2001.

[2] J. Wawrzynek et al., "SPERT-II: A vector microprocessor system",Computer, vol. 29, issue 3, pp.79-86, March 1996.

[3] A. Agranat et al., "The CCD neural processor: a neural networkintegrated circuit with 65536 programmable analog synapses", IEEETrans. Circuits Syst.,, vol. 37, no. 8, pp. 1073-1075, Aug. 1990.

[4] C. Neugebauer, A. Yariv, "A parallel analog CCD/CMOS neuralnetwork IC", Proc. IEEE Int. Joint Conf Neural Networks(IJCNN'9 1), vol. 1, pp. 447-45 1, Seattle, WA, 1991.

[5] M. J. Howes, D. V. Morgan, "Charge-coupled devices and systems",Ed. John Wiley and Sons, 1979.

[6] A. S. Grove, "Physics and technology of semiconductor devices", Ed.John Wiley and Sons, 1967, ch. 9-10, pp. 263-305.

[7] Y. P. Tsividis, "Operation and modeling of the MOS transistor", Ed.Mc Graw Hill, 1988, ch. 3, pp. 75-86.

IEEE Catalog Number: 07EX1762CISBN: 1-4244-1166-1Library of Congress: 2007923398