International Electronic Manufacturing Technology

Die Attach Epoxy Delamination Study on Low RDs(on) Device

Tan Chip KingFairchild Semiconductor (Malaysia) Sdn. Bhd.

Bayan Lepas Free Industrial Zone, 11900 Penang, Malaysiachipking.tanAfairchildsemi.com

Abstract-Delamination or separations betweensurfaces of die attach epoxy and leadframe has become a

barrier for Molded Leadless Package (MLP) to meetMoisture Sensitivity Level (MSL) 1 requirement as per

JEDEC standard. Besides, Mosfet devices that requirelow static Drain-Source On-State resistance RDs(on) andthermal resistance performance are significantly affectedif the delamination is observed between the epoxy anddie attach paddle (DAP). Hence, an evaluation has beencarried out with two set of different materialscombination namely epoxies (Epoxy A & B) anddifferent surface treatment of leadframe (LF X & Y).MLP package with body size of 5x6 mm sq has beenselected as test vehicle because of its low RDs(on) andMSL 1 @260'C requirement. Objective of thisevaluation is to fulfill these two requirements while toensure there is no delam between epoxy and DAP layers.In this evaluation, package is reflowed at 260°C andsubjected to 500 temperature cycles. Scanning AcousticTomography (SAT) and electrical test are used to checkfor package delamination and Rdson value respectively.Results show that only combination of LF Y and EpoxyB shows no package delamination and meeting Rdsonvalues.

1. Introduction

The demanding for Molded Leadless Package (MLP) or

Quad Flat No Lead (QFN) nowadays has rapidlyincreased due to its low cost, low thermal resistancerelative to other non-exposed pad packages andsimplified assembly process. Moreover the short cycletime & quality performance of this package has beenwell recognized by most of the semiconductor OEMparties. In term of reliability achievement, it could notbe denied that this package can meet MoistureSensitivity Level 1 (MSL) with threeRLme's reflow underleadfree temperature profile of 260°C. However, forpackage to achieve MSL 1, it is strongly depends on

overall construction of package which include,combination of materials such as leadframe, die attachepoxy and molding compound. Besides, design of framewith proper geometry and shape should be taken intohigh consideration as well.

Today, manufacturers are keenly searching for productminiaturization and MLP has become the best altemativepackage to replace TSSOP, SOIC & SSOP. This isbecause the size of MLP package can be shrunk about

50% as compared with current leaded package while stillproviding the same functional application. It can besuited unquestionably to products which have space

constrained such as ultra portable products DVD players,cell phones, MP3 and personal digital assistants (PDAs).

Hence, requirement on delamination criteria, RDS(on)performance and electrical drift analysis have beenstrictly regulated. Recently, Fairchild Penang hadevaluated two set of different materials (epoxy &leadframe surface roughness) combination on a lowRDS(on) discrete device which had die size of 148x130mils as the test vehicle for this evaluation. Basically, thispaper is to address the reliability findings of these twoset of materials combination as well as the electricalperformance in term of RDS(on) reading.

2. Test Vehicle Selection

2.1. Die and Device SelectionWith current low RDs(on) mosfet devices available, thelargest die size of discrete device had been selected. Themosfet die with size of 148x130 mils was the only diehad been used through this evaluation. It was

experienced that larger die size had high potential ofseparation rather than smaller die size. This is becausethe larger interface area between die and epoxy, the levelof stress induced is higher when exposed to temperaturechange.

The layout of electrical parameters & test configurationsfor low RDs(on) mosfet die is shown in Figure 1.

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Figure 1. The static Drain-Source On-State resistance electricalparameters & test configurations.

2.2. Epoxies and Leadframes SelectionMeanwhile, it is important to choose the correct dieattach conductive silver paste for this evaluation as it

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will dramatically influence the RDs(on) performances.Thus, behaviors of epoxy properties such as thermalconductivity, tensile modulus and coefficient thermalexpansion (CTE) have to take into considerationcarefully. As of results, Epoxy A with high thermalconductivity of 10W/mK and Epoxy B with low stressmagnitude were chosen. The difference of materialproperties between these two epoxies are consolidated inTable 1.

Table 1. Material properties of Epoxy A & B.

home Uni Epoxv A Epox B Condition0.5 n Pa s 113 EHD type scometer

_______ 5 m 0D 180 3o cone roter SCRIT Nkhip 45 60.8 2x2 chipAg plated Cu anme

D_eShear Stren~h 2 C _ 2 126 IWCMOmin cured in Oven

OlE v~~~IPP 69 93 IMAkbelowiTgCTE a p_ 0 9___ ui2 ppM 148 TMA, above TgTensile modulus Mpa 480 190 Tensile meterThermalcond~ut W/mK 10 4 RI IWC 1h cured

In leadiframe selection, properties that need to be takeninto attention are surface treatment in terms ofchemically & mechanical, surface profile, surfaceroughness and plating thickness. In this case, only oneleadframe design with two different surface treatmentswas evaluated. In the other word, there is no change ofgeometry and dimension of frame. The base element wascopper even though with dissimilar surface roughnessand platting thickness. The size of die attach paddle(DAP) for the leadframe is 174x152 mils. Table 2 showsthe surf"ace roughness images of these frames and otherchemical properties.

Table 2. Material Properties of LF X & LF Y

pPreplatediPd _ Pre-plated NiPdPoloti:pv.Au Yes YesBase niaterial CDA194H C 194H

Surfiace Roughnessunder SEM SOOX

Surface Treatment Micro-etched Up-grade u-PPFAu Flash: 0.12 u' mis Au-Ag alloy: 0.2 u" min

Platinig lIrhickitess Pd: 0.8 u'- 6,v u" Pd 0.1 u' minN _ - 80u Ni 10u n

should be focused on are die attach epoxy and differentsurface treatment of frames. Figure 2 illustirates thecombination of evaluated materials.

Epoxy A

Epoxy BLF

Leg 1 Epoxy A + LF XLeg 2 Epoxy A + LF YLeg 3 Epoxy B + LF X

Leg 4 Epoxy B + LF Y

Figure 2. Combination of epoxies and leadframe in this evaluation.

3. Design of Experiment

Total 4 legs of matrix DOE had been evaluated. Each ofthe DOE was assembled with in house MLP standardprocess flow which the same process of parameters suchas die attach, die attach cure, wire bonding, molding &post mold cure were used. In addition, all legs wereexposed to equal staging time, temperature & clean roomhumidity during all processes. Then, units wereserialized and tested with appropriate test program, onlyelectrically good units were continue subjected todelamination checking by using SAT (ScanningAcoustic Tomography) method. Typically, images of topand through scan were captured and analyzed todetermine the performance of package delamination.Once delamination was observed, subsequenceexperiments would not proceed. Next, units weresubjected through preconditioning as per JEDECstandard which include dry bake, MSL (Moisture Soak)& reflow at leadfree temperature 2600C [1]. Afterreflow, units were again checked for delamincation andclean units were tested accordingly. Every time unitswere sent for testing, the functional data of each, serializeunit was carefully recorded.

Although as mentioned in JEDEC standard [1], certainpercentage of delamination was still acceptable as longas electrically tested well but in this experirment onlyzero delam was allowed while electrically good was amust. These subsequence steps at E-Test & SAT wererepeated until the final stress test completeclL namelytemperature cycling (-65°C to 1650C) 500 cycle (TMCL5OOC). All the electrical and stress tests for this DOE aresimplified in figure 3. Stress test of temperaturie cyclingwas conducted to determine the ability of component towithstand mechanical stresses induced by alternatinghigh & low temperature extremes [2].

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LF YLF X

Basically, all legs were assembled with simplified MLPstandard process flow and bill of materials. Regions that

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International Electronic Manufacturing Technology IEMT 2006, Putrajaya, Malaysia

End of Assembly

E-Test 1cE1> SAT 1

Dry Bake (125°C, 24 hrs)

MSL 1@2600C

SAT 2 C<>E-Test 2

TMCL 100C

SAT 3 E,>E-Test 3

TMCL 500C

SAT 4 <>E-Test 4

Figure 3. Typical Electrical & Reliability Tests flow.

4. Results and Discussions

At the end of the evaluation, combination of leadframe Yand die attach epoxy B was the only leg that survivedthrough the DOE. The rest of the legs did not proceedfurther with next tests after units came out frompreconditioning stress test. This was because ofdelamination between epoxy die attach layer and theDAP thus, failed the evaluation purpose.

However, all units from the four legs were clean and freefrom die top to mold compound and mold compound todie attach paddle separation after verification with SATimages as shown in Figure 4.

4.1. Leg 1, 2 & 3 InvestigationFigure 4 depicts through scan pictures for leg 1, 2 & 3which showed separation at die attach layer. To ensurethere was a discontinuity layer as reflected in throughscan pictures, two units from each failed leg were thencross-sectioned and SEM had been carried out to capturethe tiny separation as shown in figure 5. Based on thecaptured images and investigation done, separation was

likely initiated from comer of the interface between dieattach & leadframe surface and propagating towards

center of die. However it depends on where was thesectioning direction and some units just showed equalgap distance of separation. All 3 legs displayed the samephenomena.

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Figure 4. Top scan & through scan images before and afterpreconditioning with MSLl for Leg 1, 2 & 3.

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Figure 5. Cross section picture under power scope & SEM for Leg 1, 2& 3.

4.2. Correlation with FEA 2D Model SimulationTherefore, a simple symmetry 2D finite element analysis(FEA) was carried out to correlate with actual case as

above. FEA software Ansys is the simulation tool usedfor this correlation. Results showed that interfacebetween leadframe and at the edge of epoxy A & Bexperienced the highest peel stress (Sy) when subiectingto simulation scenario reflow. FEA simulation results are

shown in figure 6. Simulation studies have proven thatcooling down from peak temperature 2600C to 25°Croom temperature after coming out from reflow oven hasinduced the CTE mismatch stress or thermal stress [3].Apparently, this thermal stress is the main contributionof delamination and the highest stress concentrationwould be the initial cracking point. In summary,

separation was initially started from edge of die attachand then spread to center of package for Epoxy A &Epoxy B respectively.

E h Ij11lll l_ l 2D FEA Model withconstrained boundaty

conditions

j

A...

Epoxy A

Epoxy 8

Figure 6. Sy stress (peel stress) reflow simulation for Epoxy A & B.

In the other words, no further electrical test wasperfonned for Leg 1, 2 & 3 after preconditioning. Thetiny separation observed definitely had caused theRDS(on) reading failed or drifted beyond the altowablelimitation. Delamination in the die attach region isknown to increase the electrical resistance where lead topoor RDS(on) reading [4].

4.3 Verification on Survivor Units (Leg 4)Overall, Leg 4 was the only lot that showed cleanresults until the end of all stress tests. With theconvincing component level reliability test data, therobustness of this MLP 5x6 package has been clearlydemonstrated. All SAT images from first to last timepoint reliability tests in this cont^ext have been wellpresented in Figure 7. No sign of delaminalion was

observed from the through scan images and furtherverification namely cross section was done on thescanning survivor units to ensure there was no

separation at die attach layer. Figure 8 confirms; there isno delamination from the diagonal cross-section of a

survivor unit from leg 4. In general, polymericmaterials used for this leg could withstand thehygroscopic & CTE mismatch stress induced bymoisture soaking and reflow process respective!Iy [3].

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International Electronic Manufacturing Technology

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CSAM I CSAM 2 Result

Top Scan Nill

Trough Scan Nill

-ICSAM 3 CSAM 4

Top Scan [_l

Through Scan s111

Figure 7. Sat images for all stress tests of Leg 4.

specifications when it is applied in actual operation suchas machinery, automation, communication andcomputing. Therefore, to prevent device malfunctionwhich might occur during real application especiallywhen it is exposed to sudden temperature change, FSPMhas strictly fixed percentage of functional shift above25% as compared to stress free value is not acceptable.

As a result, Leg 4 units with high thermal conductivityof epoxy B showed less than 15% of RDS(on) drift. Dataof this functional reading at each stress test was analyzedand tabulated into graph as shown in figure 9. It wasfurther justified by the boxplots as presented in figure10. It was suspected that the 15% of drift was primarycaused by the stress induced during destructive stresstest like temperature cycling. This has impacted themicro structure configuration change especially forepoxies or in this case, silver paste. However, testingvariation such as resistance from cable, geometry ofcontact pins, improper setup and socket board design arealso contributing to the drift as well.

Based on the promising data as discussed above,selecting the right combination of epoxy die attach andleadframe can resolve package delamination issue aswell as provide better RDS(on) data. This hasdemolished altemative way by adding more gold wireson source channel which is extremely costly and beingused by most discrete devices manufacturer. Aside fromthat, this package requires no dry pack and consequentlyhas reduced the packing cost.

1 2 3 4 5 6 7 8 S 11

(a)

Figure 8. Diagonal section image of a survivor unit from Leg 4.

Besides of mechanical stress tests verification had beendone, the electrical test data was also validated byfunctional drift analysis. Leg 4 was tested after each timepoint and no failure encountered till the final time pointand RDS(on) data of every single serialized unit was

carefully recorded at each electrical test This enables an

exclusive monitoring on RDS(on) performance.Meanwhile, the purpose of this drift analysis is to ensure

the units are still functional and well within the

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International Electronic Manufacturing Technology

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Figure 9. RSD(on) 1 & 2 drift analysis plot.

Boxpots of Rdson I

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Assessment results have convincingly showed Leg 4with combination of Epoxy B and Leadframe Y are thesolution for die attach separation and providle goodRDS(on) reading while is able to meet MSL 1requirements.

Acknowledgments

The author would like to express his sincere gratitude toMr. Gooi Boon Huan and thanks to the project teammembers for their tireless efforts and supportsthroughout thisackage evaluation.

References

1) IPC/JEDEC J-STD-020C. "Moisture/ReflowSensitivity Classification for Nonhermatic SolidStateSurface Mount Devices."

2) JEDEC Standard: JESD22-A104C, "TemLperatureCycling."

3) E.H. Wong, K.C. Chan, R. Rajoo and T.B. Lim."The Mechanics and Impact of HygroscopicSwelling of Polymeric Materials in electronicPackaging", electronic Components andTechnology Conference, IEEE, 2000.

4) Asif Chowdhury, Bruce Guenin, ChanHIee Woo,SeungMo Kim and Seri Lee, "The effect of DieAttach Layer Delamination on the ThermalPerformance of Plastic Packages", ECTCConference, May 25-28, 1998.

Figure 10. Boxplots of RSD(on) I & 2 drift analysis.

4. Conclusions

Selecting the correct combination of die attach epoxyand surface treatment of leadframe can solve theproblems of die attach epoxy delamination which leadto failure of low RDS(on) requirement.

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