Evaluating Fault Coverage of Bulk Built-in Current Sensorfor Soft Errors in Combinational and Sequential Logic

Egas Henes Neto1, Ivandro Ribeiro1, Michele Vieira1, Gilson Wirth1,Fernanda Lima Kastensmidt2

Universidade Estadual do Rio Grande do SulEngenharia em Sistemas Digitais

Estrada Santa Maria 2300Guaiba - RS - Brazil+55 51 491 40 42

<egas-henes, ivandro-ribeiro, michele-vieira, gilson-wirth>@uergs.edu.br

ABSTRACTIn this paper, we propose a new approach for using Built-inCurrent Sensor (BICS) to detect not only transient upsets insequential logic but also in combinational circuits. In thisapproach, the BICS is connected in the design bulk to increase itssensitivity to detect any current discrepancy that may occur duringa charged particle strike. In addition, the proposed BICS caninform if the upset has occurred in the PMOS or NMOStransistors, which can generate a more precise evaluation of thecorrupted region. The proposed approach was validated by Spicesimulation. The BICS and the case-studied circuits were designedin the 100nm CMOS technology. The bulk BIC sensor detectsvarious shapes of current pulses generated due to charged particlestrike. Results show that the proposed bulk BICS presents minorpenalties for the design in terms of area, performance and powerconsumption and it has high detection sensitivity.

Categories and Subject DescriptorsB.8. 1 [Hardware]: Reliability, Testing, and Fault-Tolerance.

General TermsDesign and Reliability.

KeywordsBICS, SET, SEU and soft error detection

1. INTRODUCTIONIntegrated circuits (ICs) operating in space applications aresusceptible to radiation, which effects can be permanent ortransient [1]. The space radiation environment consists of variouscharged particles that may interact with the silicon causingundesirable effects. When a single heavy ion strikes the silicon, it

Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and thatcopies bear this notice and the full citation on the first page. To copyotherwise, or republish, to post on servers or to redistribute to lists,requires prior specific permission and/or a fee.SBCCI'05, September 4-7, 2005, Florian6polis, Brazil.Copyright 2005 ACM 1-59593-174-0/05/0009 ...$5.00.

2Universidade Federal do Rio Grande do SulPPGC - Instituto de Informatica

Caixa Postal: 15064Porto Alegre - RS - Brazil

+55 51 33 16 70 36fglima@inf.ufrgs.br

loses its energy via the production of free electron hole pairsresulting in a dense ionized track in the local region. Protons andneutrons can cause nuclear reaction when passing through thematerial. The recoil also produces ionization. The ionizationgenerates a transient current pulse that can be interpreted as asignal in the circuit causing an upset.

A single particle can hit either the combinational logic or thesequential logic in the silicon. When a charged particle strikes oneof the sensitive nodes of a memory cell, the effect can produce aninversion in the stored value, in other words, a bit flip in thememory cell. This is called Single Event Upset (SEU) [2]. When acharged particle hits the combinational logic block, it alsogenerates a transient current pulse. This phenomenon is calledSingle Transient Effect (SET) [3]. If the induced transient pulse isnot logically or electrically masked by the logic, then the SET willeventually appear at the input of a latch, where it may beinterpreted as a valid signal.

Soft errors (SEU and SET) on devices have become more frequentbecause of smaller transistor features achieved by the continuoustechnology evolution. Detecting soft errors in the combinationaland sequential logic is extremely important to avoid errors in thecircuit application. However, it is a complex task as the intemalsignals are becoming at the same order of magnitude of thetransient currents generated by the charged particle strike.

Built-in Current Sensor (BICS) can be successfully used formonitoring on-chip current variations provoked by permanentfaults, such as stuck at circuits, and SEU, as presented in [4, 5].However, for the best of our knowledge, no work has alreadyproposed a method based on BICS to detect SET, which isbecoming an important issue in the new technologies. In thispaper, we propose a new approach for using BICS to detecttransient upsets in sequential and combinational logic. In thisapproach, the BICS is connected to the design bulk of thetransistors, which increases the BICS sensitivity to detect anydiscrepancy in the circuit internal current that may occur during aparticle strike. In this paper, the proposed BICS is named bulk-BICS.

This new approach has two main positive effects. The first one isthat the BICS is able to differentiate SETs from internal logicsignals and consequently detect them. The second one is that, in

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this case, the BICS has a minor effect in terms ofperformance andpower dissipation compared to the BICS connected to the powerlines.

The proposed approach was validated by Spice simulation. TheBICS and the case-studied circuits were designed in the lOOnmCMOS technology. Results using bulk-BICS present less than0.5% of performance degradation when connected to a memorycell and less than 9.5% when connected to the case studycombinational circuit. Results also show the high detectionsensitivity of the bulk-BICS to SEU and SET.

This paper is organized as follows. The next section discussesrecent related works, which use BICS connected to the powerlines to detect SEU in memory cells. Section 3 presents theproposed bulk-BICS and its results when connected to a memorycell. Section 4 shows the results of the proposed BICS embeddedin combinational circuits. The detection upsets in NMOS andPMOS region is shown in section 5. Conclusions and futureworks are discussed in section 6.

2. RELATED WORKAn efficient method to detect SEU and SET in integrated circuitsis mandatory to evaluate the sensitivity of a circuit and toguarantee its reliability. For sequential logic, Error CorrectingCodes (ECCs) are often used to detect and correct soft errors inmemories. However, ECCs may cause significant area,performance and power dissipation penalties. In addition, ECConly detects and corrects the SEU at the time the faulty word isread, and not when it occurs, which may cause accumulation ofSEUs invalidating ECC based on single error detection andcorrection capabilities. BICS have been successfully used formonitoring on-chip upsets because it presents fewer penaltiescompared to ECCs.

Related works [4, 5] have presented asynchronous BICS able todetect SEUs in memories. In this case, the BICS in placed on thepower lines of a memory. This is an efficient solution forsequential circuits. However, this solution does not work forcombinational logic because BICS connected to the power linecannot efficiently differentiate internal signals propagatingthrough the logic from SET (upsets). Detecting transient upsets inthe combinational logic is much more complex because it isnecessary to evaluate the intensity of the pulse generated by thecharged particle strike. Previous works on SET detection haveproposed logic duplication, time redundancy and extra transistorsfor detection, which are all very costly for the design [6].This work shows that the BICS connected to the bulk can reducethe penalties in terms of area, performance and power dissipation,increasing the efficiency in detecting SEU and detecting SET incombinational logic. The BICS used for comparison to ourapproach was published in [4]. In this case, the BICS is connectedin the power lines of a memory, as represented in figure 1.

In the absence of current in the virtual power-bus (VDD' andGnd'), the voltage level in the gate of transistor T3 is VDD and theone on the gate of T6 is Gnd. When a charged particle strikes thesilicon, two situations can occur, where in both cases the voltagelevel on the BICS output increases, producing a positive output.The first case happens when the upset is due to a particle whichcharges the drain of the PMOS device that is off, thus, the gate ofT6 is charged to a voltage greater than Gnd. The second one

happens when the upset is due to a particle which discharges thedrain of the NMOS device that is off, thus, the gate of T3 isdischarged to a voltage smaller than VDD.

Figure 1. Built-in Current Sensor connected to the power linesof a Memory Cell.

In the next sections, we present our proposed method, the bulk-BICS able to detect SEU and SET with a minor effect in area,performance and power dissipation. In addition, the results showthe efficiency of our method in detecting various shapes ofcharged current pulses that may strike in combinational andsequential logic.

3. A BULK-BIC SENSORS EMBEDDED INMEMORY CELLSWhen a charged particle strikes a sensitive node in a CMOScircuit, it generates a current that flows between the drain of thetransistor and the bulk. The direction of the current depends if theparticle is discharging the logic node, or is charging the logicnode [2]. The current induced by a charged particle strike is moreintense at the bulk than at the connection to the power lines.Consequently, it is more efficient to think about a BICSconnected to the bulk of a circuit, instead of connecting it to thepower lines of a circuit. This new connection scheme is presentedin figure 2.

Figure 2. The Bulk-BICS connected to a Memory cell.

The bulk-BICS works the same as the referenced one, the onlydifference is that now the BICS is analysing the current thatoccurs in the bulk of the transistors. During the normal operation,the current in the bulk is approximately zero. Only the leakagecurrent flows through the biased junction, which is still very lowcompared to the current generated by charged particles. So, when

63

a charged particle generates a current in the bulk, it is very clear tothe bulk-BICS that an upset has happen. The bulk-BICS can becalibrated to detect only transient current pulses that actually cancause an error in the logic.

3.1 Performance Evaluation for Bulk-BICS inMemory CellsThe bulk-BICS and the case-study circuits were designed in the100nm CMOS technology. The Spice model is from theUniversity of Califomia, Berkeley. For this technology, thesupply voltage VDD is 1.2V and WMIN is 1.5 the LMIN [7]. For thememory cell, the two PMOS transistors cell were dimensionedwith L minimum and Wp = 2WMIN, and the four NMOS transistorswere dimensioned with WN- WMIN. The dimensions for thestandard and the bulk-BICS are: transistors TI, T2 and T7 useW=0.15gm and L=lgm (W/L = 0.15/1 = 3/20). Transistors T6and T4 use W=0.6,um and L=0.lgm (W/L = 6/1). Transistor T3uses W==lm and L= 0.1pm (W/L = 10/1). Transistor T5 usesW=0. 15gm and L=0. Igm (W/L = 0.15/0.1 = 3/2).

Table 1 presents the results of the comparison between thestandard BICS [5] and the bulk-BICS in terms of performancedegradation. The propagation time (Tp) in the write and read cyclewere analysed, as well as the rising and falling time during thewrite cycle. The simulation results show that the use of embeddedbulk-BICS provokes very low performance degradation in thememory cells. All the propagation, rising and falling time of thememory without using a BICS and using an embedded bulk-BICSare very similar, the difference is less then 0.5%.

Table 2 shows the results of the comparison between the standardBICS [5] and the proposed one in terms ofpower dissipation. Theresults show that the standard BICS presents a power dissipationtwo order of magnitude higher that the bulk-BICS.

Table 1. BICS Comparison Results in Terms of PerformanceDegradation in the Memory Cell.

tim (ps) Memory cell Embedded Embeddedtime (ps) Memory cell Standard BICS Bulk-BICS

Write tpLH 82.2 85.6 (4.1%) 81.9 (-0.3%)Write tPHL 69.6 63 (-9.5%) 69.6 (0 %)Read tPLH 143 151.1 (5.7%) 143.4 (0.27%)Read tPHL 143 151.1 (5.7%) 143.3(0.27%)

Write TRIsING 44.5 851.6 (1813.7%) 44.3 (-0.44%)Write TFALLING 39.6 32.4 (18.2%) 39.8 (0.5%)

Table 2. BICS Comparison Results in Terms of PowerDissipation in the Memory Cell.

power dissipation Embedded Standard Embedded Bulk-(fW) BICS BICS

Write operation 0.54 0.0046.Read operation 0.73 0.0024

3.2 Sensitivity Evaluation for Bulk-BICS inMemory CellsThe simulations show that the bulk-BICS is efficient to detecttransient faults in memory cells. During the simulations, the timeparameters of the exponential current source that are modelled bydouble exponential current pulse at the particle strike [8] are keptfixed while the parameter current peak (Io) varies. As discussed in[8], the temporal shape of the transient current generated by thecharged particle strike is a decisive factor for SEU occurrence ornot.

Table 3 presents the minimum current peak (IOMN) to provoke abit-flip, for the same time parameters. Note that the presence of aembedded BICS, either connected to the power lines or connectedto the bulk has a minor effect in the sensitivity of the memory cell.Actually, one can say that the embedded bulk-BICS tums thecircuit a little less sensitive to SEU because the minimum currentpeak able to provoke a bit-flip in the memory cell increases withthe presence of the embedded bulk-BICS.Table 4 shows the IOMIN able to provoke a positive transition inbulk-BICS output, in other words, the minimum current peak thatthe BICS can detect. In this paper a transition is defined as asignal that reaches VDD/2. Please note that the minimum currentdetected by the BICS are around 20% smaller than the actuallyminimum current that is able to provoke a SEU. This means thatthe BICS work in a considerable safe margin of detection. Resultsshow that the embedded bulk-BICS has higher detectionsensitivity than the standard BICS connected to the power lines.

Table 3. The Minimum Current Peak (IOMIN) to Provoke a Bit-Flip in the Memory Cell (values in gA).

Memory cell Embedded EmbeddedStandard BICS Bulk-BICS

Upset from 335 319 345'1 5to '0' 35 1

Upset from 361 347 365'0' to '1

3

Table 4. The Minimum Current Peak (IOMIN) to Provoke aPositive Transition in the Bulk-BICS Output (values in pA).

Embedded EmbeddedStandard BICS Bulk-BICS

Upset fom 252 (-21%) 257 (-25%)

.Upset rmm 278 (-20%) 217 (-40%)

64

Vdd

Vdd/2

a3)

0)n4-

VA.J el --v UU

Vdd/2

fitU0 0.25 0.5 0.75 1

Time (ns)Figure 3. A positive transition in the Bulk-BICS output.

Figure 3 shows a simulation where a current pulse generated by a

charged particle strike provokes a positive transition in the Bulk-BICS output. In this case Io = OMmIN and as the upset is from '1' to'0', the Io = IOMmN = 257gA.

simulation time, under the waveform of an ideal square pulse,maintaining fixed the inputs B and C, in such a way that the pathA is not logically masked. The results of this first simulations arethe propagation delay, of low to high (tpLH) and of high to low(tpHL), and the rising and falling delay, that are shown in table 5and the power dissipation, in table 6.

Table 5. The Bulk-BICS Embedded in Combinational circuit(performance degradation- values in ps)

Comb. Embedded Embeddedcircuit Standard BICS Bulk-BICS

tPLH 80.6 126.3 (56.7%) 88.1 (9.3%)

tPHL 106.4 183.4 (72.4%) 105.1 (-1.2%)TRISING 20 1263.4 (6217%) 18.6 (-7%)

TFALLING 18.3 190.1 (938.8%) 18.4 (0.5%)

Results show that the embedded bulk-BICS present less than9.5% in performance degradation, while the embedded standardBICS can present up to 938.8% in performance degradation,which is unacceptable. Results also show that the bulk-BICSpresents less power dissipation overhead compared to the standardone.

Table 6. The Bulk-BICS Embedded in Combinational circuit(Power Dissipation by BICS - values in fW)

4. BULK-BIC SENSORS EMBEDDED INCOMBINATIONAL CELLSA transient pulse in a combinational circuit, produced by a

particle strikes, may be captured by a memory cell, producing a

soft-error [3]. Therefore, the detection of transient faults incombinational circuits is very important in recent technologies.Figure 4 shows the case study combinational circuit used in thesimulations. All the PMOS transistors have the same values forthe parameter W, Wp = 2WMIN. The same happens for NMOSdevices, where the parameter W is WN = WMIN for all thetransistors. Different shapes of current pulses were also injected inthe sensitive nodes of this combinational circuit in order toevaluate the detection of the BICS.

Figure 4. Combinational circuit used in simulations.

4.1 Performance Evaluation for Bulk-BICS inCombinational Logic CellsThe combinational circuit was simulated with no-embeddedBICS, with embedded standard BICS and with embedded bulk-BICS. The simulation consists in changing the input A during the

4.2 Sensitivity Evaluation for Bulk-BICS inCombinational Logic CellsSimilar to the experiments presented in section 3, duringsimulation, the time parameters of the injected current pulse are

kept fixes while Io varies. In simulation, a current pulse is insertedin logic node XOR1 (see figure 4), that is at logic level '1'. Whenthis happens, the input A is high and the inputs B and C are low.The parameter Io is IOMIN = 297gA, where IOMIN is the minimumcurrent peak for to provoke a transition in the positive Bulk-BICSoutput pulse. Figure 5 shows this behaviour.

In this simulation, the transient current is detected by the bulk-BICS. The transient pulse in XOR1 is small and its propagationfor the stages XOR2 and out is electrically masked, however, theSET was detected by Bulk-BICS. The standard BICS could notdetect any SET because it could not differentiate the SET from theinternal signals. The continuation of this work is concern to builda correlation between the SET detection by the embedded bulk-BICS and the probability of the SET being captured by a memorycell provoking a soft error.

65

SRAM cell node wherethe particle hit occurs

u

BICS Outputlis

Vdd/2

c

I

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Vdd/2

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5. DETEC1AND PMOSIn this section, Nperformed in theidentification ofproposed BICSmodified BICS istransistor T4 islarge area becausiis normally highpossibility of distthe ones in the Nfaulty region in tI

In the absence (Gnd'), the voltagare, respectively,BICS is similar tT6 by MN2 and I

The same modifiBICS, when a

situations: if the i

of the PMOS c

discharged to a v

a particle which (

off, then, the galGnd;

Ul -

I

Figure 6. The modified BICS.

In first case, the voltage level on the BICS P-output is increased,producing a positive pulse. In second case, the voltage level on

the BICS N-output is decreased, producing a negative pulse. Thepositive output or negative output makes possible to differentiatethe upsets in the PMOS transistors to the upsets in the NMOStransistors.

lcs Outpu6. CONCLUSIONS AND FUTURE WORK

0 0.2 0.55 75 1 The authors have proposed the use of BICS connected to the bulkof the transistors instead of connecting it to the power lines. This

Titme (ns) increases the sensitivity of the BICS to detect transient current

in the positive Bulk-BICS output.pulses generated by charged particle strikes and enables the BICSto detect SET. The proposed bulk-BICS was first evaluated in

[ING UPSETS IN THE NMOS memory cells to detect SEU. The simulation results showed that

the use of embedded bulk-BICS provokes virtually noREGION performance degradation in the memory cells, performance

we discuss about the modifications that can be degradation is less then 0.5%. Results also showed that the bulk-standard BICS design in order to allowing the BICS presents less power dissipation overhead compared to theupsets in the NMOS and PMOS region. The standard one and the embedded bulk-BICS has higher detection

is presented in figure 6. One advantage of the sensitivity than the standard BICS connected to the power lines.s the reduction of the number of transistors. The This means that a smaller number of bulk-BICS may be used to

iow removed. This transistor usually occupies a detect SEUs in a memory cell array, which reduces the area

e the relation between W and L for this transistor overhead used for embedded BICS. Usually, there are more than

1, around 6 to 1. The other advantage is the one standard BICS per row or column of the memory array,

tinguish upsets that occur in the PMOS region to depending on the memory size.'MOS region. This can help to precisely map the

he circuit design. Results have demonstrated that the standard BICS can not be used

to detect SET. In other hand, the proposed bulk-BICS canof current in the virtual power-bus (VDD' and successfully detect SETs and it presents less than 9.5% ine level in the gate of transistors MP2 and MN2 performance degradation, where connected to a case studied

VDD and Gnd. The behaviour of this modified combinational circuit, while the embedded standard BICS can

to the one explained in section 2, only replacing present up to 938.8% in performance degradation. Results also

[3 by MP2. showed that the bulk-BICS presents less power dissipation

cation can be done in the bulk-BICS. For Bulk- overhead compared to the standard one.current transient is generated, there are two In addition, some modifications in the BICS were proposed to

upset is due to a particle which charges drain allow the BICS to inform if the upset has occurred in the PMOS

levice that is off, then, the gate of MP2 or NMOS transistors. This can generate a more precise evaluation

oltage smaller than VDD; or if the upset is due to of the corrupted region. Future work will focus in create a more

discharges the drain of the NMOS device that is precise methodology to detect the SETs in the combinational logic

te of MN2 is charged to a voltage greater than that will cause soft errors by using the bulk-BICS and to test this

BICS in more complex combinational logic circuits.

66

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[6] Anghel, L., Alexandrescu, D. and Nicolaidis, M.. Evaluationof a soft error tolerance technique based on time and/or spaceredundancy. In: Symposium on Integrated Circuits andSystems Design, SBCCI, 13., 2000. Proceedings... LosAlamitos: IEEE Computer Society, 2000. p. 237-242.

[7] http://www-device.eecs.berkeley.edu

[8] Wirth, G., Vieira, M. and Kastensmidt, F. L.. ComputerEfficient Modeling ofSRAM Cell Sensitivity to SEU. In:Proceedings of the 6th IEEE Latin America Test Workshop,2005. pp. 51-5

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