Ultra low-voltage bidirectional current mirror using

clocked semi-floating-gate transistors

Yngvar Berg

Nanoelectronics

Department of Informatics

University of Oslo

N-0316 Oslo, Norway

Email: yngvarb@ifi.uio.no

Abstract—In this paper we present an ultra low-voltage bidi-rectional and continuous time current mirror based on clockedsemi-floating-gate transistors. The current mirror may be usedwith supply voltages down to 250mV and frequencies up toseveral hundred MHz. The simulated data presented are obtained

using the Spectre simulator provided by Cadence and valid for a90nm TSMC CMOS process.

I. INTRODUCTION

Current mirrors are widely used circuits for analog and

mixed-signal applications. Normally the supply voltage re-

quirements are restricted to one threshold voltage plus at least

two saturation voltages. As supply voltages are forced down

by digital constraints, new circuit techniques must evolve to

preserve the precision of analog functions in a mixed-signal

system [1]. It is necessary that the analog power supply be

at least equal to the sum of the magnitudes of the n-channel

and p-channel thresholds. This implies that low voltage analog

circuits are incompatible with the CMOS technology trends of

the future. The challenge is to develop circuit techniques that

are compatible with future standard CMOS technology trends

[2].

Floating-gate (FG) gates have been proposed for ultra

low voltage (ULV) and low power (LP) logic [3]. However,

in modern CMOS technologies there are significant gate

leakage which undermine non-volatile FG circuits. FG gates

implemented in a modern CMOS process require frequent

initialization to avoid significant leakage. By using floating

capacitances to the transistor gate terminals the semi-floating-

gate (SFG) nodes can have a different DC level than provided

by the supply voltage headroom [3].

In this paper we examine ultra low voltage CMOS current

mirrors based on floating-gate transistors. In most practical

applications the supply voltage will higher than used in the

simulation examples. In order to process inputs using the

available headroom the current mirror presented will combine

a pMOS and a nMOS current mirror [4].

In section II the ultra low voltage switched transistors

are presented followed by the continuous time clocked-semi-

floating-gate (CSFG) current mirror in section III. The CSFG

symmetric and continuous time current mirror is described in

section IV. Simulated data for the current mirrors are included

in section V.

II. ULTRA LOW VOLTAGE SWITCHED TRANSISTORS

A switched symmetric non-continuous time ULV current

mirror is presented in [4]. By using two current mirrors

operating in opposite phases we obtain a continuous time

clocked current mirror with an inherent auto-zero function.

Cinp

Out

φ

φVin

nMOS pMOS

recharge

transistor

Cinn

Out

φ

φ

FG1

recharge

transistor

Cinn

φ

φ

FG2

recharge

transistor

Cinp

φ

FG1 FG2

φ

recharge

transistor

Vin

Vo!set+

Vo!set- Vo!set-

Vo!set+

Fig. 1. The nMOS and pMOS continuous time clocked semi floatinggate (CCSFG) transistors. The input signal is applied to one of theFG nodes depending on the clock signal. The other FG node will beforced to VDD simultaneously.

The continuous time clocked-semi-floating-gate (CCSFG)

transistors are shown in Fig. 1. The recharge transistors

are drawn vertically and the evaluate transistors are drawn

horizontally. By powering up the gate to source voltages in an

initialization phase we are able to reduce the supply voltage

without decreasing the ON current provided by the enhanced

transistors. The aim is to maintain a high current level com-

bined with a very low supply voltage. The enhancement can

be viewed as a active threshold voltage shift. Note that the

recharge transistor and the evaluate transistor are clocked

by inverse signals which will, to some degree, reduce the

capacitive noise imposed to the semi-floating-gate. In order

to reduce the charge injection we may add a dummy recharge

switch. The noise imposed through parasitic capacitance’s and

charge injection may be reduced by a symmetrical, i.e. quasi

differential, design approach.

III. CONTINUOUS TIME CSFG CURRENT MIRROR

By separating the gate terminals of the transistors as shown

in Fig. 2 we obtain the split gate CSFG current mirror. The gate

terminals are recharged by two separate recharge transistors.

More interestingly, the transistors do not share a common

978-1-4244-6613-9/10/$26.00 ©2010 IEEE 93

φ

Vin

Cinn1

φ

Vout

Cinpφ

φ

Current mirror, split gate

Iin Iout

Cinn2

φCinn2

Fig. 2. CSFG split gate current mirror with minimum sized transis-tors.

input capacitor. An advantage of the split gate approach is an

increase in transconductance due to less capacitance associated

with the floating gates.

The input capacitors may be exploited to compensate for the

inaccuracy due to channel length modulation. By changing the

relative capacitance of the input capacitors, Cinn1 and Cinn2

we may compensate for the inaccuracy due to the Early effect.

Assuming that V2 ≈ VDD − V1 we may express the currents

in the evaluation phase Ie1 and Ie2 as

Ie1 = Ir · ek1

(

V1−VDD

2

)

·

(

1 + λ

(

V1 −VDD

2

))

Ie2 = Ir · ek2

(

V1−VDD

2

)

·

(

1 + λ

(

VDD

2− V1

))

,

where Ir, called the recharge state current, is the current

running through a CSFG transistor assuming that all inputs

are VDD/2, i.e. the circuit state after recharge and prior to

any input transitions. We may exploit k1 and k2 to minimize

the inaccuracy of the current mirror by solving the equation

Ie2 = Ie1

Ie2 = Ie1

k2 ≈ k1 +

ln

(

1+λ·VDD

2

1−λ·VDD

2

)

VDD

2

Cinn2 ≈ C1 + CT nUT ·

ln

(

1+λ·VDD

2

1−λ·VDD

2

)

VDD

2

,

which for VDD = 0.175V , λ = 5.7, Cinn1 = 2fF ,

CT = 6fF and n = 2 yields Cinn2 ≈ 6fF . The increased

transconductance of the output transistor compensates for the

output conductance of both transistors. If the current mirror

operates in strong inversion the capacitance Cinn2 needs to be

increased furthermore due to the reduced relative transconduc-

tance gm/I . The lower bound for the input current is limiting

A

φ

φ

FG1

Cinn1

φ

φ

FG2

Cinn2

B

FG3

Cinn2

φ

FG4

Cinn1

Cinp

VinCinp Cinp

φ

Cinp

φ

nMOS Current Mirror

Vo!set+

Vo!set-

Vo!set+

Vo!set-

Vo!set+

Vo!set-

Vo!set+

Vo!set-

IoutIin

E3E2E1 E4

B1A2A1 B2

FGA1 FGA2 FGB1 FGB2

Fig. 3. The continuous time ULV current mirror. A current sourceand a current sink are included for simulation purposes. The currentsrunning through the recharged evaluate transistor are neglect-able.

the timing response of the current mirror. In order to maintain

a timing response limited by the recharge current and not by

the lower bound we need to apply a pMOS current mirror

in addition to a nMOS current mirror. The accuracy of the

current mirror, assuming matched transistors and capacitors,

is above what can expected for the ultra low supply voltage

and minimum sized evaluate transistors. The compensation for

the finite output resistance, presented in [4], works well. The

current headroom, however, is very low.

The continuous time ULV current mirror is shown in Fig.

3 and resembles an auto zero circuit sampling an input

signal. Input and output stages are included for the purpose

of providing typical current sources and loads. E1 and E2

are input transistors operating in opposite phases, and E3

and E4 are output transistors operating in opposite phases.

When φ = 0 transistor E1 and E4 will be evaluating any

input changes while transistors E2 and E3 will recharge to

Voffset+. When φ switches from 0 to 1 the floating gates of

transistor E2 and E3 will be equal to Voffset+. Any input

changes will affect the two floatings gates and produce a

effective gate to source voltage of these transistors according

to

VE1effective= Voffset+ + ke1∆VA

VE4effective= Voffset+ + ke4∆VA

where ke1 = Cinn1/CTE1, ke4 = Cinn2/CTE4

, CTE1is the

total capacitance seen by the floating gate of transistor E1

and CTE4is the total capacitance seen by the floating gate of

transistor E4. The input capacitance’s are used to compensate

for the difference in currents due to the finite output resistances

of output and input transistors [4].

We may evaluate the response of an input signal when φ =

0:

1) At the switching point when φ switches from 1 to 0.

94

C2

φ

φ

Vo set+

Vo set-

Ep

En

Rp

Rn

In2

VoutIp2

C1

φ

φ

Vo set+

Vo set-

Ep

En

Rp

Rn

In1

Ip1

IoutIin

φ

φ

C1

C2

Vfgn1

Vfgn2

Vfgp1Vfgp2

Fig. 4. Symmetric ULV current mirror.

a) Assume Vin ≈ 0, and hence VA ≈ VDD . We may

assume that VFG1 = VFG4 = Voffset+, VFGA2 =

VFGB1 = Voffset−, VFG2 ≈ VFG3 > Voffset+

and VFGA1 ≈ VFGB2 < Voffset−. Furthermore

we may assume that VB ≈ 0. The currents IE1 ≈IA2 ≈ IE4 ≈ IB1, Iin = IA2 − IA1 = IE1 − IE2

and Iout = IE4 − IE3 = IB1 − IB2. Independent

of the previous current of the operative transistors

right ahead of the transition the current level will

be reset to the initial recharge currents determined

by the offset voltages. We may expect only a minor

change in the active current pulling nodes A and Bdue to the switching of operative transistors from

E2 to E1 and E3 to E4, even though the actual

current level is changed significantly.

b) We may expect a small voltage drop for A and a

small increase in B. The voltage change will be

small because the effective voltage of A2 and E1

are equal. This holds for E4 and B1 as well.

c) A positive input transition occurs. If transistors A2

and E1, and E4 and B1 are matched, we will see a

voltage change of A equal to ∆Vin in the opposite

direction, or more precisely ∆VA = −∆Vin.

d) VA falls due to a positive input signal and the

currents IE1 and IE4 will decrease and the node

B will rise. We may expect that ∆VB = −∆VA =

∆Vin.

2) If Vin ≈ VDD we will experience the opposite case as

explained previously. The circuit is symmetric and the

circuit performs according to (a).

IV. SYMMETRIC AND CONTINUOUS TIME CSFG CURRENT

MIRROR

The symmetric ULV current mirror is shown in Fig. 4. We

may examine the circuit response to a recharge operation.

During recharge the nMOS floating gate voltages are fixed

to Voffset+ while the pMOS floating gate voltages are equal

to Voffset−, the node voltages at input and output are

equal to VDD/2 and the currents are equalized, i.e. In1 =

In2 = −Ip1 = −Ip2 = Ir, where Ir is the recharge current

determined by the offset voltages applied. Furthermore the

input and output currents are assumed to be 0. Assume that

the input current increases compared to Ir. This will lead to an

increased voltage at the input, i.e assuming a pMOS transistor

feeding a positive current into input node. As a result the

currents In1 and In2 will increase and Ip1 and Ip2 will be

reduced accordingly. We may express the

∆In1 − ∆Ip1 = ∆Iin

∆In1 = ∆Iin + ∆Ip1

∆In2 = ∆Iin + ∆Ip2

∆In2 − ∆Ip2 = ∆Iin

∆Iout = ∆Iin (1)

The input stage will act as a current to voltage converter and

the output stage will act as a voltage to current converter. The

change in input and output currents can be negative or positive

and thus the current mirror is bidirectional. The actual input

and output current can be expressed as

Iin = ∆Iin

Iout = ∆Iout

Iout = Iin

The input current Iin will pull the input terminal towards VDD

or gnd depending on the polarity of the current. A negative

current will pull the input terminal down and a positive input

current will pull the input up. The input current will be

matched by a current provided by the inverter in the I to V

converter. The I to V converter will generate an input voltage

to drain the actual input current. If the input current is equal to

the recharge current the circuit is stable and the input voltage is

equal to VDD/2. Any change in the input current will affect the

floating gate voltages such that the input current is drained by

the inverter in the I to V converter. The drained input current

will be available at the output due to a corresponding change

in the floating gate of the inverter producing the output current.

The symmetric and continuous time CSFG current mirror is

shown in Fig. 5. The input current Iin and the output current

Iout are distributed into four paths according to

Iin = Ip1 + Ip2 − In1 − In2

Iout = Ip3 + Ip4 − In3 − In4.

The current mirror in Fig. 5 is symmetrical in terms of

clock phases. If we assume that φ = 0 we can analyze

the response of the circuit in more detail. Transistors EN1,

EP1, EN4 and EP4 are recharging and the currents drawn

by these transistors depend on the voltage of the input and

output of the current mirror. We may assume that the output

voltage voltage are dependent on the input voltage according

95

Iin Iout

C1

C2

φ

φ

φ

φ

φ

φ

φ

φ

φ

φ

φ

φ

φ

φ

Vo set+ Vo set+ Vo set+ Vo set+

Vo set- Vo set- Vo set- Vo set-

Iin Iout

In1Ip1

In2Ip2

In3Ip3

In4Ip4

C1 C1

C1 C1

C2

C2

C2

C2

EN3EN2EN1 EN4

EP3EP2EP1 EP4

Current mirror

Fig. 5. The symmetric and continuous time CSFG current mirrorand simplified symbol representation including a current source anda current sink.

to Vout ≈ VDD − Vin. The recharging transistors will affect

the currents in the current mirror. If the input and output

voltages are VDD/2 we may assume that current mirror is

in a initial state, for example right after a clock edge φchanges from 1 to 0, and the active transistors EN2 and

EP2 provides currents equal to the recharge state current

Ir determined by effective gate to source voltages equal to

Voffset+ and Voffset− − VDD for transistors EN2 and EP2

respectively, hence In2 = |Ip2|. In this state the current

running through the recharged transistors are non-significant

due to the reverse biasing of these transistors and the effective

gate to source voltages are equal to Voffset+ − VDD/2 and

Voffset−−VDD/2 for transistors EN1 and EP1 respectively.

Furthermore, assuming matched transistors, In1 = |Ip1| and

hence will not affect the input current. The same arguments

hold for the current IE4 and IP4 as well. The input current

will be provided by a symmetric CSFG circuit, typically a

symmetric and continuous time inverter similar to the output

stage of the current mirror. After each clock edge the current

mirror, the circuit proving the input current and the circuit

draining the output current will be in a state with no current

flowing between the different circuits.

V. SIMULATION RESULTS

The bidirectional ULV current mirror was simulated using

a supply voltage equal to 250mV and offset voltages equal

to 400mV and -150mV. The recharge frequency applied in

the simulation examples are 25MHz. The usable recharge

frequency range is determined by the offset voltages and

supply voltage applied. For low supply voltages and low

offsets both the leakage current and the active currents are

small and the recharge frequency may be reduced, although

maintained high enough to secure a complete recharge of the

floating gates and to avoid problems due to leakage currents.

The input frequency may vary and is limited by the timing

response, i.e. current level determined by the supply voltage

and offsets applied.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 10−7

−6

−4

−2

0

2

4

6

8x 10

−7

Time [s]

Cu

rre

nt

[A]

In1

In1

In4

In4

Ip1

Ip4

Ip1 Ip4

In1

In4

Ip1

Ip4

In2

In3

Ip2

Ip3

In2 In3

Ip2 Ip3

In2 In3

Ip2 Ip3

Fig. 6. The response of the current mirror to sine input with afrequency equal to 50MHz.

In Fig. 6 the positive and negative components of the

input and output currents are shown when a sine input

with a frequency equal to 50MHz is applied. If the input

frequency is lower than the recharge frequency the auto-zero

function performed at each reacharge clock edge becomes

more evident. In this case the current amplitude is reduced

and the reponse may be modelled using equation 1.

The output currents are slightly larger than the input currents

due to a larger output capacitance C2 compared to the input

capacitance C1. The mismatch in the nMOS current mirror is

larger than the mismatch in the pMOS current mirror and is

most evident for low nMOS currents, hence when the pMOS

currents dominate.

In Fig. 7 the input signal is a sine with a frequency equal

to 50MHz and the input, i.e Iin = Ip1 + Ip2 + In1 + In2, and

output currents, i.e Iout = Ip4 + Ip3 + In4 + In3 are shown.

The output current as a function of the inputs current is shown

in Fig. 8. The mismatch in the nMOS current mirrors can be

observed as a small current gain for positive input and output

currents.

96

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 1 0−7

− 4

− 3

− 2

− 1

0

1

2

3

4

Time [s]

x 1 0−7

Curr

ent [A

]

- - - output currentinput current

Fig. 7. Input (solid) and output (dashed) currents of the ULV currentmirror. Input frequency equal to 50MHz.

−3 −2 −1 0 1 2 3 4

x 1 0−7

− 4

− 3

− 2

− 1

0

1

2

3

4x 1 0

−7

Outp

ut curr

ent [A

]

Input current [A]

Fig. 8. The output current relative to the input current for a sine

input with a frequency equal to 50MHz.

In Fig. 9 the positive and negative components of the input

and output currents are shown when a sine input with a

frequency equal to 200MHz is applied. In Fig. 10 the input

signal is a sine with a frequency equal to 200MHz and the

input and output currents are shown. In this case the recharge

clock edges are arriving when the input currents are low or

high compared to the average level, ie.e at time 0.4× 10−7s.

This can be seen as a distortion in the transient response

of the current mirror and is most evident in Fig. 10. The

output current as a function of the inputs current is shown

in Fig. 11. The distortion due to the auto-zero function of the

current mirror is not influencing the performance of the circuit

because the both the input and aoutput current are auto-zeroed

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 10−7

−6

−4

−2

0

2

4

6

8x 10

−7

Time [s]

Cu

rre

nt

[A]

In1

In1

In4

In4

Ip1Ip4

Ip1 Ip4

In1In4

Ip1Ip4

In2In3

Ip2

Ip3

In2 In3

Ip2 Ip3

In2 In3

Ip2 Ip3

Fig. 9. The response of the current mirror to sine input with afrequency equal to 200MHz.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 1 0−7

− 4

− 3

− 2

− 1

0

1

2

3

4

Time [s]

x 1 0−7

Curr

ent [A

]

- - - output currentinput current

Fig. 10. Input (solid) and output (dashed) currents of the ULV currentmirror. Input frequency equal to 200MHz.

simultaneously. The higher input frequency is favorable in

terms of leakage effects which is observable as larger current

amplitudes and this effect can bee seen as a more linear current

mirror response. The delay of the circuit is observable as a

small mismatch for increasing and decreasing input currents.

In Fig. 12 the positive and negative components of the

input and output currents are shown when a sine input with

a frequency equal to 10MHz is applied. The accuracy of the

current mirror for low input frequencies may be improved by

decreasing the output to input capacitance ratio C2/C1. The

output current as a function of the inputs current for a sineinput with a frequency equal to 10MHz is shown in Fig. 13. In

this case the delay of the circuit is neglecable and the response

97

−4 −3 −2 −1 0 1 2 3 4 5− 4

− 3

− 2

− 1

0

1

2

3

4

5

x 1 0−7

x 1 0−7

Outp

ut curr

ent [A

]

Input current [A]

Fig. 11. The output current relative to the input current for a sine

input with a frequency equal to 200MHz.

1.3 1.4 1.5 1.6 1.7 1.8 1.9 2

x 10−7

−6

−4

−2

0

2

4

6x 10

−7

Time [s]

Cu

rre

nt

[A]

Ip4Ip1

In4

In1

Ip3

Ip2

In3

In2

Fig. 12. The response of the current mirror to sine input with afrequency equal to 10MHz

is not influenced by inreased or decreased input currents.

VI. CONCLUSION

We have presented a ultra low-voltage bidirectional ultra

low-voltage current mirror based on a ultra low-voltage digital

logic style. Clocked semi floating gate transistors are used to

provide current mirrors operating at supply voltage close to

or even below the inherent threshold voltage of a advanced

CMOS process. The current mirror is recharged or initialized

in the same way as ULV digital logic. We have presented a

split-gate current mirror which exploit relative capacitances to

compensate for inaccuracy due to channel length modulation.

Simulated data provided are valid for a 90nm TSMC CMOS

process.

−2 −1.5 −1 −0.5 0 0.5 1 1.5 2− 2

− 1.5

− 1

− 0.5

0

0.5

1

1.5

2

x 1 0−7

x 1 0−7

Outp

ut curr

ent [A

]

Input current [A]

Fig. 13. The output current relative to the input current for a sine

input with a frequency equal to 10MHz.

REFERENCES

[1] S. Chatterjee, Y. Tsvidis and P. Kinget: “Ultra-Low Voltage AnalogIntegrated” Circuits. IEICE Transactions on Electronics. 2006 E89-C(6):673-680.

[2] S. Yan and E. Sanchez-Sinencio: “Low Voltage Analog Circuit DesignTechniques: A Tutorial”,IEICE Transactions on Analog Integrated Cir-

cuits and Systems, vol. E00-A, no. 2, February, 2000.[3] Y. Berg, D. T. Wisland and T. S. Lande: “Ultra Low-Voltage/Low-

Power Digital Floating-Gate Circuits”, IEEE Transactions on Circuits

and Systems, vol. 46, No. 7, pp. 930–936,july 1999.[4] Y. Berg and O. Mirmotahari: “Clocked Semi-Floating-Gate Ultra Low-

Voltage Symmetric and Bidirectional Current Mirror”, In Proceedings

of the 2009 International SOC Conference, Irland. IEEE conference

proceedings, Belfast september 2009.

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