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Presentation on

Boundary Scan and JTAG [ IEEE 1149.1]By

Vysakh PAmrita School Of Engineering

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BOUNTARY SCANBOUNTARY SCAN

[IEEE 1149.1 / JTAG standard][IEEE 1149.1 / JTAG standard]

Presentation by:Vysakh P

ASE

Aum Sri Gurubhyo Namah:

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OverviewOverview

Boundary scan: A method for testing interconnects onPCBs or IC sub-blocks

The Joint Test Action Group (JTAG) developed a

specification for boundary scan testing that was

standardized in 1990 as the IEEE Std. 1149.1-1990.

In 1994, a supplement that contains a description of theBoundary Scan Description Language (BSDL) was added

which describes the boundary-scan logic content ofIEEE Std 1149.1 compliant devices. (1149.1a)

Boundary scan is nowadays mostly synonymous with JTAG.

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Bed of NailsBed of Nails

Predecessor to the boundary scan test method

Employs small spring loaded test probes to makeconnections with solder pads on the bottom of theboards.

Viable only in low density board designs (layers)

Test points increased board size and complexity

Custom made (expensive)

Much of the testing could not be performed until

design is complete.

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Bed of NailsBed of Nails

Bed of nails testing got

exacerbated as board

dimensions got

smaller andsurface mound

packaging

technology improved.

If devices were

mounted on

both sided of a circuitboard

no attachments were

left for

test equipments.

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Boundary ScanBoundary Scan

Tests interconnects and clusters of logic,memories etc.. without using physical test probes.

Adds 'test cells to each pin of that can selectively override thefunctionality of that pin.

These cells can be programmed via the JTAG scan chain to drivetest signals.

Cell at the destination can then be programmed to read the value at

the pin, verifying the board trace

Boundary scan inside IC logical design blocks as if they werephysically independent circuits.

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Interconnect Test exampleInterconnect Test example

Assume that a short between twonets behaves as a wired-ANDand an open is sensed as logic 1.

Typical Board with Boundary-Scan Components

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Testability report prior to PCB layout

enhances Design For Testability DFT.

Find packaging problems prior to PCB layout. Little need for test points.

More control over the test process.

Quickly diagnose (with high resolution) Iinterconnect problems without writing any

functional test code.

Program code in flash devices. Put design configuration data into CPLDs.

JTAG emulation and source-level debugging.

Why Boundary scan???

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JTAGJTAG

The Joint Test Action Group (JTAG) developed a

specification for boundary scan testing that wasstandardized in 1990 as the IEEE Std. 1149.1-1990.

Signal lines in the Test Access Port (TAP)

TDI (Test Data In)

TDO (Test Data Out)

TCK (Test Clock)TMS (Test Mode Select)

TRST (Test Reset) [optional].

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The basic TAP ideaThe basic TAP idea

The protocol is necessarily serial.

Configuration is performed by manipulating a state machine onebit at a time through a TMS pin.

One bit of data is transferred in and out per TCK clock pulse atthe TDI and TDO pins, respectively.

Different instruction modes can be loaded to Read the chip ID Sample input pins Drive (or float) output pins Manipulate chip functions Bypass (pipe TDI to TDO to logically shorten chains

of multiple chips). Perform any function as per the designers wish

The operating frequency : 10-100 MHz typically (varies with chip design)

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Chip architecture showing TAPChip architecture showing TAP

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The JTAG State machine and functionalityThe JTAG State machine and functionality

The TCK and TMS inputs determine whether an instruction registerscan or data register scan is performed.

The TAP consist of a small controller design, driven by the TCK input,

which responds to the TMS input as per a state diagram

The main state diagram consists of six steady states: Test Logic Reset

Run-Test/Idle Shift-DR Pause-DR Shift-IR and

Pause-IR

Only one steady state exists when TMS is set high:the Test Logic Reset state.

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TAP Registers

Registers: There are two types of registers associated

with boundary scan. Each compliant device has

One instruction register

Two or more data registers.

Instruction Register

Holds the current instruction.

Content used by the TAP controller to

decide what to do with signals that are

received.

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TAP Registers.....

The instruction register must be at least two bits long to

allow coding of three mandatory instructions.

BYPASS : For testing of other devices in the JTAG

chain

EXTEST: Allows the user to set and read pin states

SAMPLE/PRELOAD: The BSR can be accessed by adata scan operation to take a sample of the functional

data entering and leaving the device

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TAP Registers.....

Data Registers:Three primary data registers,

Boundary Scan Register (BSR)

BYPASS registerIDCODES register.

BSR : Main testing data register used to move data to and

from the pins on a device.BYPASS: Allows other devices in a circuit to be tested with minimaloverhead. (TDI to TDO.)

IDCODES: Contains the ID code and revision number for thedevice.

This information allows the device to be linked to its Boundary ScanDescription Language (BSDL) file.

The file contains details of the Boundary Scan configurationfor the device.

Other data registers may be present, but they are not required as part of theJTAG standard.

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Scans consist of 3sprimary steps:

CAPTURE

SHIFTUPDATE

6-state TAPprovides 4 majoroperations:

RESET RUN-TEST

SCAN-DR SCAN-IR

The JTAG State machineThe JTAG State machine

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The TAP is forced into the test logic reset state by

driving TMS high and applying five or more TCK s.

TAP issues the reset signal that places all test logic in

a condition that does not impede normal operation

of the host IC.

When test access is required a protocol is applied

causing the TAP to enter the test logic reset state

and move through the appropriate states.

TAP FunctionalityTAP Functionality

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First action: Capture operation.

o For the data registers, the capture-DR state

captures the data into the serial data path.

o If boundary scan register selected register the

normal data inputs are captured .

o The capture-IR state is used to capture status

information into the instruction register.

TAP FunctionalityTAP Functionality

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TAP functionality

From the capture state, the TAP transitions to

either the shift or exit one state .

Normally the shift state follows the capture state so

that test data or status.

Information can be shifted out for inspection andnew data shifted in.

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Extended applications:

Some designs have defined proprietary extensions

that use the JTAG capability to implement software

debug functions. Often JTAG interface

Download code and memory values from CPU.

Access to any part of or the device that is

accessible in the CPU enabling easy debugging.

Flash programming of devices.

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JTAG provides a backdoor to the CPU

(Thus if not carefully architectured can cause

spurious access into the CPU and code)

Common JTAG hacks includes uncapping of cable

modems, cell phone network uncapping, Xbox mods

etc.

Extended applications..

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Conclusion:Conclusion:

Advantages: Eliminates the need for large number of test

vectors, which are normally needed to properly

initialize sequential logic. Shorter test times

Higher test coverage

Increased diagnostic capability

Lower capital cost . (Equipment)

If not carefully architectured, can act as a backdoor

into the proprietary design

No better Solution!!!

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Thank You

Aum Sri Gurubhyo Namah: