ICCAD 2017 Tutorial Standard Cell Design and Optimization ... · Standard cell library design and...
Transcript of ICCAD 2017 Tutorial Standard Cell Design and Optimization ... · Standard cell library design and...
©2017ArmLimited
StandardCellDesignandOptimizationMethodology
forASAP7PDKXiaoqingXu,NishiShah,AndrewEvans,
SaurabhSinha,BrianClineandGregYericArmInc
[email protected]/15/2017
ICCAD2017Tutorial
©2017ArmLimited2
Outline
ASAP7PDK
StandardCellLibraryDesignandOptimization
DesignSynthesisandExploration
HowtoDownloadandUse
Summary
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ASAP7PDK
Predictive7nmProcessDesignKit– ArmandASU:http://asap.asu.edu/asap/
• FinFET withdiscretetransistorsizing
Transistorgeometries
• 20/54nmgatelength/pitch,27nmfinpitch.
Keydesignrules
• 18/36nmmetal-1width/pitch(two-dimensionallayoutwithEUV)
• Metalminimumtip-to-tip31nm,metalminimumtip-to-side:25nm
• Minimumhorizontaldistancebetweendiff-netactiveareas:92nm
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KeyImplicationsonLayoutDesign
Keydesign-ruleconstraints:• Diffusionbreak• Horizontalmetalrouting• Verticalmetalrouting• Gatecontact• Gatecutusage
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KeyImplicationsonLayoutDesign
Keydesign-ruleconstraints:• Diffusionbreak• Horizontalmetalrouting• Verticalmetalrouting• Gatecontact• Gatecutusage
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KeyImplicationsonLayoutDesign
Keydesign-ruleconstraints:• Diffusionbreak• Horizontalmetalrouting• Verticalmetalrouting• Gatecontact• Gatecutusage
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KeyImplicationsonLayoutDesign
Keydesign-ruleconstraints:• Diffusionbreak• Horizontalmetalrouting• Verticalmetalrouting• Gatecontact• Gatecutusage
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StandardCellLibraryDesignandOptimization
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StandardCellArchitecture
9-Trackand7.5-Track
SCarchitecture 9-track 7.5-trackTotal#offins 12 10
#offinspertransistor 4 3
# ofmetal-1tracksforsignalrouting
8 5.5
#ofmetal-2trackforsignal routing
8 6
metal-2 andmetal-1trackoffset(nm)
0 9
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ExhaustiveTransistorSizing
NAND2_X1Nunder7.5-trackarchitecture
• Exhaustivetimingsimulationstochoosethebalancedrisingandfallingslew/delay
• NAND2_X1RandNAND2_X1F,rising/fallingdominatedcells
(2p,2n) (2p,3n) (3p,2n) (3p,3n)
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TransistorPlacement
AOI31_X2N:consistentEulerpathforpull-upandpull-downlogic
A0
A0
A1 A2
A1
A2
B0
B0
A0 A0 A1 A1 A2 A2
B0 B0
B0 B0
A0 A0
A1 A1
A2 A2
pull-up logic
pull-down logic
(A0,B0,B0,A0,A1,A2,A2,A1)
[Uehara+,DAC’1979][Maziasz+,DAC’1987]
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GeneralizedEulerPath
MXT2_X1N:pass-gate-basedmultiplexer
• MultigraphsforPMOS/NMOSarenolongerdual
ny
ns0
BAS0
ny
PMOS
NMOS
S0 AS0 ns0
B
S0
(S0,A,S0,ns0,B,ny)
(S0,A,ns0,S0,B,ny)
S0
A
B
ns0ns0
S0
S0
ns0
Yny
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GeneralizedEulerPath
MXT2_X1N:pass-gate-basedmultiplexer
• Area-compactplacementleadstoroutability issues:pinAisblocked
S0
A
B
ns0ns0
S0
S0
ns0
Yny
(S0,A,0,S0,ns0,B,0,0,ny)
(S0,A,ns0,S0,0,B,0,0,ny)PinA
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GeneralizedEulerPath
MXT2_X1N:pass-gate-basedmultiplexer
• Area-compactplacementleadstoroutability issues:pinAisblocked
S0
A
B
ns0ns0
S0
S0
ns0
Yny
(S0,A,0,S0,ns0,B,0,0,ny)
(S0,A,ns0,S0,0,B,0,0,ny)PinA
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GeneralizedEulerPath
MXT2_X1N:pass-gate-basedmultiplexer
• Adifferentarea-compactplacementsolution:pinAisaccessible
S0
A
B
ns0ns0
S0
S0
ns0
Yny
(S0,ny,0,0,S0,ns0,0,B,A)
(S0,ny,0,0,0,ns0,S0,B,A)Adifferentpath
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GeneralizedEulerPath
MXT2_X1N:pass-gate-basedmultiplexer
• Adifferentarea-compactplacementsolution:pinAisaccessible
S0
A
B
ns0ns0
S0
S0
ns0
Yny
(S0,ny,0,0,S0,ns0,0,B,A)
(S0,ny,0,0,0,ns0,S0,B,A)Adifferentpath
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CellLayoutComparisons
LATNQ_X1N
7.5-track:13poly-pitchwideNormalizedarea:97.5Singlegatediffusion
9-track:11poly-pitchwideNormalizedarea:99
Gatecutusage
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FO4Comparisons
Fan-out-4(FO4)forbasiclogiccells
• 9-trackcellsprovidesmallerdelaybyconsuminghigherpower/area
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DesignSynthesisandExploration
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DesignSynthesisFlow
Arm®Cortex®- M0processorfromArmDesignStartTM portal
7.5-track/9-trackminimum/alphaSClibrary
Cadence®GenusTM SynthesisSolution,v15.12&InnovusTM ImplementationSystem,v15.10
SC Library Design RTL
Logic Synthesis
Partitioning & Floorplanning
Placement & Routing
Design Closure
CadenceReferenceFlow:up-topostrouting stageEvaluationmetrics:• Frequency,Power,Leakage,WNS• TNS,Utilization,gatecountandarea
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ExploreStandardCellArchitecture
Totalnegativeslack(TNS)andworstnegativeslack(WNS):9-tracklibpushesthefrequency
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ExploreLibraryRichness- 9-tracklibraries
Totalnegativeslack(TNS)andworstnegativeslack(WNS):alphalibpushesthefrequency
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HowtoDownload
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ArmDesignStart Portal
ArmDesignStart – UniversityProgram
https://developer.arm.com/products/designstart/university-program
Comingsoon!!!
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SuggestedResearchTopicswiththeASAP7StandardCellLibrary
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SizingwithOne-FinTransistor
Currentlibrariesaredesignedwithminimum2finspertransistor
• One-fintransistorhasvariationconcernsbutbenefitscelltiming/power
ResizetheSDFFQ_X1Nwithone-fintransistor
• Setuptime:11.8psà 9.6ps(18.6%),Clock-to-Qdelay:42.1psà 40.0ps(5%)
• Energydelayproduct(EDP):8.15à 7.13(10-17 J*s) (12.5%)
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ResearchTopicsforStandardCellDesignMethodology
Transistorsizing
• Howtoavoidbrute-forceeffortsfortransistorsizing?
• Whatisthelibrary-leveladvantageofenablingone-fintransistor?
Squeezethetrackheight
• Howfarcanyoureducethetrackheight?
• 5-trackcells– IMECatIEDM2016
Multi-rowheightcells– designanddesignautomation
• Howtoplaceandroutetransistorsacrossmultiplerows?
• Whatsetofcells(notjustflops)shouldbedesignedacrossmultiplerows?
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BroaderResearchTopics
AutomaticCellSynthesis
• themultigraphisnotalwaysEulerian
• the“best”transistorplacementisnotalwaysroutable
• the“best”solutioncouldbetechnology/architecture-dependent
• Automaticcellsynthesistobeatour“alpha”qualityintermsofPPA?
Technology-independentstickdiagramgeneration
• placementandroutingareco-optimizedunderlexicalcostformulation
• generatemore-than-onesolutiontobreaktechnology/architecturedependence
Design-technologyco-optimization,reliability,hardwaresecurityandacceleratordesigns
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ASuccessfulandPublishedExampleforAgingResearch
Layout-dependentagingbehaviors
Agingmitigationforcritical-pathtiming
• Agingmodelsw/ASAP7PDK- PekingUniversity
• Agingoptimizationwithdetailedplacement- UTDA
• Che-Lun Hsuet.al,“Layout-DependentAgingMitigationforCritical-PathTiming”atASP-DAC2018
SA↓ NBTI, HCI&PBTI↑ODS↓ NBTI, HCI&PBTI↑SPM↓ NBTI ↓
SA– LengthbetweengateandedgeofdiffusionODS– ActivetoactivespacingSPM– Polyextensionfromactive
[Ren+,IEDM’2015]
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Summary
Standardcelllibrarydesignandoptimizationmethodology
• Transistorsizing,placementandrouting
• Front-endandback-endviewsbuilt,testedandfreelyavailableforacademicusages
Vt options Trackheights PVT corners Cellviews
RVTLVTSLVT
7.5-track9-track
ff_typical_max_0p77v_25cff_typical_max_0p77v_m40css_typical_max_0p63v_125css_typical_max_0p63v_25ctt_typical_max_0p70v_25c
cdl,db,db-ccs-tngds2,gds2-ascii,LEF,lib,lib-ccs-tn,spice,
verilog
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Summary
Standardcelllibrarydesignandoptimizationmethodology
• Transistorsizing,placementandrouting
• Front-endandback-endviewsbuilt,testedandfreelyavailableforacademicusages
DesignSynthesisandExploration
• Libraryarchitectureandrichnessexplorations
HowtoDownloadandUse
• ArmDesignStart portal– universityprogram
• Multipleresearchtopicsofinterestandasuccessful/publishedresearchstudyJ
Freq.(GHz)
SCarch. TNS(ps)
Power(mW)
Gatearea(um2)
1.0 7.5.track -893 2.26 1537.99-track 0 2.21 1646.9
0.7 7.5-track 0 1.29 1306.99-track 0 1.41 1463.5
3232
ThankYou!Danke!Merci!谢谢!ありがとう!Gracias!Kiitos!감사합니다धन्यवाद
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