IC Transistors and Resistors Chris Kendrick Jan. 29, 2003 BiCMOS Design I.Resistors II.Bipolar...
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Transcript of IC Transistors and Resistors Chris Kendrick Jan. 29, 2003 BiCMOS Design I.Resistors II.Bipolar...
IC Transistors and Resistors
Chris KendrickJan. 29, 2003BiCMOS Design
I. ResistorsII. Bipolar TransistorsIII. MOSIV. DMOS
Resistor Voltage Coefficient
Figure 1 A p type region in an n type tub forms the resistor.
http://adev.onsemi.com/knowledge_net/index.html
Resistor Voltage Coefficient
% Change PHV Resistance vs. Body Bias
0.00%
5.00%
10.00%
15.00%
20.00%
25.00%
0 10 20 30 40 50
Body Bias (V)
% C
ha
ng
e R
esi
sta
nce
30x300
12x300
6x300
12x120
12x30
VApplied = 5V
Resistor Temperature Coefficient
PHV Resistance vs. Temperature
-40.0%
-20.0%
0.0%
20.0%
40.0%
60.0%
80.0%
-100 -50 0 50 100 150 200
Temperature (C)
% C
ha
ng
e in
Re
sist
an
ce
30x300
12x300
6x300
VBody = 5V
Resistor Voltage limits
Diffusion Breakdown (V)
Buried Layer – Isolation 95
PWell – Epi 95
PHV – Epi 60
NHV - PWell 43
PSD - Epi 30
NSD - PWell 17.5
NSD – PHV 12
NSD – PSD (in PWell) 5.8
• The maximum resistor voltage is NOT defined by the tub it’s sitting in!
• The voltage rating of the tub determines the spacing of PHV to Epi
Lateral PNP Saturation
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Low current NPN/PNP biasing
• What’s the lowest current bipolars can be biased at?
Lateral PNP
ICmin ~ 5uA
PNP (PHV/Epi - Emitter 21x 21 UDR) cross-section
Epi
Substrate
EC
PSD
FOX
PHV NSDPSDPSD PHV
B
PHV
FOX FOX
Low current NPN/PNP biasing
• What’s the lowest current bipolars can be biased at?
Vertical PNP
ICmin ~ 20nA
PWell
PNPV (PSD/NHV - Emitter 28 x 28 UDR) cross-section
Epi
Substrate
B
PSDNHVPSD
PSD PHV
C
PHV
E
NSDNSD
C
FOXFOX
Low current NPN/PNP biasing
• What’s the lowest current bipolars can be biased at?
NPN
ICmin ~ 20nA
PWell
NPN (NSD/PWell - Emitter 21 x 21 UDR) cross-section
Epi
Substrate
E B
PSD PHV NSDNSDPSD PHV
FOX
C
FOX FOX
MOS Safe Operating Area
• Hot carrier injection limits NMOS operating voltage
Low Voltage NMOS cross-section
Epi
Substrate
PWell
FOX FOXBPSG BPSG
Poly S G D
NSD
0.0E+00
5.0E-06
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.0E-05
3.5E-05
4.0E-05
0 1 2 3 4 5 6
Gate Voltage (V)
Bu
lk C
urr
en
t (A
)
LV LVT NMOS 100x6Time to 10% IDlin degredation vs. Vds
1.0E+05
1.0E+06
1.0E+07
1.0E+08
1.0E+09
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22
1/Vds (V-1)
Tim
e @
10
% Id
lin d
eg
red
ati
on
10 yrs -> Vds=4.6V
LV NMOS Hot Carrier Injection
• Maximum Vds determined from HCI measurements 10% degradation in 10 yrs
• Transient Vds rating based on 10% duty cycle
Measured Vds Max (V) Id 10%
Device 1 yr. 10 yr.
LV NMOS 100x6 5.5 5.1
LV NMOS 100x16 6.8 6.5
LV LVT NMOS 100x6 5.1 4.6
LV LVT NMOS 100x16 6.4 6.1
LV LVT PMOS drain-source leakage• Drain-source leakage determines maximum Vds at high temperature• Minimum channel length targeted based on process variation and independent
SEM measurement
LV LVT PMOS Leakage vs. Gate Length (Vds=5V)L29894, wf #19
1.0E-16
1.0E-15
1.0E-14
1.0E-13
1.0E-12
1.0E-11
1.0E-10
1.0E-09
1.0E-08
1.0E-07
1.0E-06
4.5 5.0 5.5 6.0 6.5 7.0 7.5
Gate Length (UDR)
Le
ak
ag
e C
urr
en
t (A
/um
)
Flat_27
Flat_150
Center_150
Top_27
Top_150
Flat_poly1_27
1.69um
1.70um
1.43um
Minimum Poly2 CD = 1.57um
150C
27C
DMOS Specific Rdson
Rsp = Rdson x transistor active area
Active Area width
Act
ive
Are
a le
ngth
Ex : LDMOS transistor
Device Rdson () Area (cm2) Rsp. (m.cm2)
LV NLDMOS 0.66 5.19E-4 0.34
MV1 NLDMOS 1.93 7.32E-4 1.41
LV PLDMOS 2.58 5.19E-4 1.34
MV PLDMOS 4.92 7.32E-4 3.6
VDMOS_HEC 1.53 1.77E-3 2.7
transistor active area = # cells x cell area
DMOS Specific Rdson
N-Buried Layer
N-Epi
PHV PHV PWN+
SinkerN+ N+ N+P+ P+
P-substrate
S G D
• More components to Rdson than just channel resistance RCH + REpi + RBL + RMetal
0.0E+00
1.0E-02
2.0E-02
3.0E-02
4.0E-02
5.0E-02
6.0E-02
0 2 4 6 8 10 12
VGS (V)
IDS
(A
)
• Series resistance causes ‘bend’ in ID vs. VG curve
A useful way to extract DMOS series resistance
DSV
TV
GSV
L
WoxC
DI )( S
RDI
DSV
DSV
L
WCOX
2))(1(TV
GSV
SR
DSV
GSVDSI
MG
SDDSTGS
D
RIVVV
I
(1)
(2)
(3)2
))((
D
DSTGSMDS I
VVVGIR
Device size (cells) R-series (Ohms) Total rdson (OHMs) % series resistance
NLDMOS_13V 5x20 0.37 0.69 54 %
NLDMOS_30V 5x20
NLDMOS_45V 5x20 1.44 1.99 72 %
PLDMOS_13V 5x20 1.25 2.66 47 %
PLDMOS_45V 5x20 2.8 5.0 36 %
VDMOS_HD 15x46 1.63 1.84 89 %
VDMOS_HEC 13x46
Substituting (2) into (3) gives,
DMOS Clamped Inductive Switching• Clamping the flyback voltage below the DMOS breakdown increases energy
capability.• Power dissipation eventually allows parasitic bipolar to turn on, killing device
-5.00x10-4 -2.50x10-4 0.00 2.50x10-4 5.00x10-4 7.50x10-4
-10
0
10
20
30
40
50
60
70
80
Vd
Dra
in V
olta
ge (
V)
Time (sec.)
-0.5
0.0
0.5
1.0
1.5
2.0
to
Id
Energy CapabilityDevice Comparison
y = 1.7849x0.6421
y = 1.9762x0.6223
y = 2.8072x0.6032
0
50
100
150
200
250
300
0 500 1000 1500 2000 2500
Time (uS)
En
erg
y (
mJ
/mm
2)
47V VDMOS_HD
47V VDMOS_HEC
47V MV2_NLDMOS
Power (47V VDMOS_HD)
Power (47V VDMOS_HEC)
Power (47V MV2_NLDMOS)
Energy capability can determine device size
DMOS Rdson vs. Energy Capability
0.0
5.0
10.0
15.0
20.0
25.0
30.0
0.0E+00 2.5E-03 5.0E-03 7.5E-03 1.0E-02
Area (cm 2)
Rd
son
(
)
0.00
20.00
40.00
60.00
80.00
100.00
120.00
140.00
160.00
Rdson
Energy Capability