IC Technology and

Device Models

1. The planar process for integrated circuit fabrication

2. Review of DC and AC Diode Models 3. Review of dc and ac JFET models 4. Review of dc and ac bipolar transistor models 5. Review of dc and ac MOS transistor models

1.1 The planar process for integrated circuit

fabrication

The configuration is called the monolithic integrated circuit because it is formed on a single silicon chip.

Wafer preparation Very high purity Silicon wafer cylinder 10, 12.5, 15 or 20 cm in diameter and 1 m in length. This crystal is then sliced (like a loaf of bread) to produce wafers 200 micron thick and the surface is then polished to a mirror finish. Impurities can then be added on purpose to the pure silicon in a process known as doping, to allow controlled alteration of the electrical properties of the silicon.

Oxidation It refers to the chemical process of silicon reacting with oxygen to form SiO2. The oxide layer grown has excellent electrical insulation properties. With dielectric constant of about 3.5, it can be used to form excellent capacitors. It can also be used as a masking layer, allowing the introduction of the dopants into the silicon only in regions that are not covered with oxide.

Diffusion The process of introducing impurity atoms (dopants) into silicon to change its doping is known as diffusion. The two most common impurities used as dopants are Boron (p-type) and Phosphorus (n-type). Both dopants are effectively masked by thin SiO2 layer – the process is called Photolithography. Photolithography refers to the process to produce mask for SiO2 on all layers resulting in ‘windows’ in the layer for subsequent diffusion process.

Ion implantation It is a method superior than diffusion to introduce impurities into Silicon with the aid of electric field. It is much more accurate process and can be performed at room temperature.

Chemical vapor deposition It is a process by which gases or vapours are chemically reacted leading to the formation of a solid on a substrate. It can deposit the SiO2 layer at a faster rate and lower temperature.

Metallization The process of metallization is to interconnect the various components of the IC to form the desired circuit. Metallization involves the deposition of the metal (Al) over the entire surface of the Silicon. The required interconnection is then etched selectively.

Packaging A finished silicon wafer may contain thousands of chips, which are tested while in wafer form. The circuits are then separated from each other and good circuits are then mounted in hermetically sealed plastic packages with necessary connection legs.

Advantages of monolithic IC as compared with discrete components Low cost (due to large quantities processed, no manual assembly) Small size, low power consumption High reliability (All components are fabricated simultaneously and there are

no soldered joints) Improved performance (Because of low cost, more complex circuitry may be

used to obtain better functional characteristics)

1.2 Review of DC and AC Diode Models

If a negative voltage is applied to the diode anode, no current flows and the diode behaves as an open circuit. Diodes operated in this mode are said to be reverse-biased, or operated in the reverse direction.

On the other hand, if a positive current is applied to the anode, the ideal diode behaves as a short circuit in the forward direction.

Simplified diode models

iD = 0, vD VD0

iD = (vD – VD0) / rD, vD VD0

where VD0 is the intercept of line B on the voltage axis and rD is the inverse of the slope of line B.

The small signal model There are

applications in which a diode is biased to operate at a point on the forward i-v characteristic and a small ac signal is superimposed on the dc quantities. For this situation the diode is best modeled by a resistance equal to the inverse of the slope of the tangent to the i-v characteristic at the bias point.

A dc voltage VD, represented by a battery, is applied to the diode; and a time varying signal vd(t), assumed (arbitrarily) to have a triangular waveform, is superimposed on the dc voltage VD. In the absence of the signal vd(t) the diode voltage is equal to VD, and correspondingly the diode will conduct a dc current ID

given byID = Ise

VD/VT ----------------------(1.1)

When the signal vd(t) is applied, the total instantaneous diode voltage vD(t) will be given by

VD(t) = VD + vd(t) -------------(1.2)

Correspondingly, the total instantaneous diode current iD(t) will be

iD(t) = IsevD/VT --------------(1.3)

Substituting for vD from eq (1.2) gives

iD(t) = Is e(VD + vd) / VT

which can be rewritten asiD(t) = Is e

(VD/VT) evd/VT

using equ. (1.1) we obtainiD(t) = ID evd/VT -----------(1.4)

Now if the amplitude of the signal vd(t) is kept sufficiently small such that

Vd / VT << 1

Then we may expand the exponential of eq 1.4 in a series and truncate the series after the first two terms to obtain the approximate expression

iD(t) = ID(1 + vd / VT)

This is the small-signal approximation. It is valid for signals whose amplitudes are smaller than about 10 mV.

1.3 Review of dc and ac JFET models The figure shows the basic structure of

the n-channel JFET. It consists of a slab of n-type silicon with p-type regions diffused on its two sides. The n region is the channel, and the p-type regions are electrically connected together and form the gate. Current flow between two of the device terminals is established by a voltage applied to the third terminal (gate terminal). The operation of the device depends upon the reverse biasing applied between the gate and the channel. It is a unipolar transistor, in which current is conducted by charge carriers flowing through one type of semiconductor only. It is characterized by very high input impedance and therefore is implemented in the input stage of an integrated-circuit op-amp. Since gate to channel junction is almost always reverse biased, very small leakage current (of the order of 10-9 A) will flow in the gate terminal, giving very high input impedance.

Operation of n-channel JFET with vDS small Consider the n-channel JFET with small vDS applied. With vGS =

0, the application of a voltage vDS causes current to flow from the drain to the source. When a negative vGS is applied, the depletion region of the gate-channel junction widens and the channel becomes correspondingly narrower; thus the channel resistance increases and the current ID (for a given vDS) decreases. Because vDS is small, the channel is almost of uniform width. The JFET is simply operating as a linear resistance rDS whose value is controlled by vGS. That means the JFET is operating as a voltage controlled resistance. If we keep increasing vGS in the negative direction, a value is reached at which the depletion region occupies the entire channel. At this value of vGS the channel is completely depleted of charge carriers (electrons); the channel has in effect disappeared. This value of vGS is called the pinch off voltage(Vp) or the threshold voltage of the device, Vt.

vDS

iD

-V1

-V2

-V3

VGS= 0

Operation with vDS increased Now consider the case where vGS is

constant at a value greater than Vt, and vDS is increased. Since vDS appears as a voltage drop across the length of the channel, the voltage increases as we move along the channel from source to drain. It follows that the reverse-bias voltage between gate and channel varies at different points along the channel and is highest at the drain end. Thus a channel acquires a tapered shape and the ID-vDS characteristic becomes nonlinear.

When the reverse bias at the drain end, vGD, falls below the threshold voltage Vt, the channel is pinched off at the drain end and the drain current saturates.

IDSS = ID with vGS = 0 and vDS = -Vp

Static characteristics Triode region - JFET operates as a linear resistance Pinch off region - JFET operates beyond pinch-off voltage These two regions are separated by a parabolic boundary given by vDS = vGS -

Vp.

The JFET operates in the triode region forvDS vGS -Vp

and the corresponding drain current is given byiD = K[2(vGS – Vp)vDS – v2

DS]

or, iD = IDSS[2(1-vGS/Vp)(vDS/-Vp) – (vDS/Vp)2]

for small vDS, iD 2IDSS/-Vp (1-vGS/Vp) vDS

giving rDS = vDS/ID = [2(IDSS /-Vp) (1 – vGS/Vp)]-1

At the boundary between triode and pinch off region, vDG = -Vp giving VDS = vGS -Vp,, iD = IDSS (vDS / Vp)

2 (parabola) The JFET operates in saturation (pinch-off) for VDS vGS - Vp The drain current is given by

iD = IDSS (1 – vGS / Vp)2 (1 + vDS)

where 1/VA is a positive constant included to account for the dependence of iD on vDS in pinch off.

Small Signal Analysis It is important to note that the small-signal model parameters gm and ro

depend on the dc bias point of the JFET.

gm = 2IDSS / |Vp| (ID / IDSS) gm (max) = gmo = 2IDSS / |Vp|

[IDmax = IDSS at VGS = 0] The drain current of a practical JFET depends on vDS in a linear manner.

Such dependence is modeled by a finite resistance ro between drain and source, whose value is given approximately by

ro |VA| / IDwhere ro is in the range 10 to 1000 k.

Since gate to channel junction is reverse biased, depletion capacitances exist between gate and source, and between gate and drain. Typically

Cgs = 1 to 3 pF and Cgd = 0.5 to 1 pF.

1.4 Review of dc and ac bipolar transistor models The figure shows the signal

components of the BJT amplifier circuit. It shows the expressions for the current increments ic, ib and ie obtained when a small signal vbe

is applied. These relationships can be represented by a circuit. Such a circuit should have three terminals , C, B, and E, and should yield the same terminal currents indicated in fig 1.12. The resulting circuit is then equivalent to the transistor as far as small-signal operation is concerned, and thus it can be considered an equivalent small-signal circuit model.

The hybrid- Model

voltage-controlled current source

ic =gmvbe, ib = vbe / r, ie = vbe / re current of the controlled source

ic = ib

1.5 Review of dc and ac MOS transistor models Metal-oxide semiconductor field effect transistor (MOSFET) can be

enhancement or depletion type. Depending upon the semiconductor used for forming channel, it is named “p channel” or “n-channel” MOSFET.

Enhancement type MOSFET(OFF until turned ON)

Four terminals gate (G), Drain (D), Source (S) and body (substrate) (B) are brought out of the device.

The substrate forms pn junctions with the source and drain regions. In normal operation these pn junctions are kept reverse-biased at all times.

Operation with no gate voltage With no bias voltage applied to the gate, two back-to-back diodes exist

in series between drain and source. These back-to-back diodes prevent current conduction from drain to source when a voltage vDS is applied.

Creating a channel for current flow

When a sufficient number of electrons accumulate near the surface of the substrate under the gate, an n region is created, connecting the source and drain regions. Current flows through the channel if voltage is applied between source and drain. The induced n region thus forms a channel for current flow from drain to source.

Operation with small vDS After the creation of a channel,

a small positive voltage is applied between drain and source which causes a current iD to flow through the induced n channel. Current iD depends upon the electron density of the channel and the magnitude of vGS. Specifically, for vGS = Vt the channel is just induced and the current conducted is still negligibly small. As vGS exceeds Vt, more electrons are attracted into the channel thus the channel depth is increased. The result is a channel of increased conductance or equivalently reduced resistance.

Operation as vDS is increased Let vGS be held constant

at a value greater than Vt. Now the appplied voltage vDS appears as a voltage drop across the length of the channel. Since the channel depth depends on this voltage, we find that the channel is no longer of uniform depth; rather, the channel will take the tapered form, being deepest at the source end and shallowest at the drain end.

When vDS is increased to the value that reduces the voltage between gate and channel at the drain end to Vt – that is, vGS – vDS = Vt or vDS = vGS – Vt – the channel depth at the drain end decreases to almost zero, and the channel is said to be pinched off. Increasing vDS beyond this value has little effect on the channel shape, and the current through the channel remains constant at the value reached for vDS = vGS – Vt.

The drain current thus saturates at this value, and the MOSFET is said to have entered the saturation region of operation.

Static characteristics Triode region (ohmic region) For the MOSFET to be operated in triode region, following conditions

should be fulfilled. i)   vGS >Vt ii) vGD > Vt iii) vDS < VGS - Vt

Then, iD = k [ 2(vGS –Vt) vDS –vDS2]

where k is a constant given by k = 1/2 n Cox (W/L)

Pinch-off region For the MOSFET to operate in the pinch off region, the following

conditions should be fulfilled.

i) vGD Vt, ii) vGS Vt, iii)  vDS vGS - Vt

Then, iD = k(vGS –Vt)2 which is a voltage controlled current source.

Taking the channel length modulation effect into consideration, the drain current is given by

iD = k (vGS – Vt)2 (1 + vDS / VA)

At the boundary between triode region and pinch off region iD = k vDS

2

Depletion-type MOSFET (ON until turned OFF) The depletion MOSFET has a permanently implanted channel. Thus an n-

channel depletion type MOSFET has an n-type silicon region connection the n+ source and the n+ drain regions at the top of the p-type substrate. Thus if a voltage vDS is applied between drain and source, a current iD flows for vGS = 0. In other words, there is no need to induce a channel, unlike the case of the enhancement MOSFET.

Positive vGS enhances the channel by attracting more electrons into it. A negative gate voltage causes electrons to be repelled from the channel; and thus the channel becomes shallower and its conductivity decreases. The negative vGS is said to deplete the channel of its charge carriers, and this mode of operation is called depletion mode. As the magnitude of vGS is increased in the negative direction, a value is reached at which the channel is completely depleted of charge carriers and iD is reduced to zero even though vDS may be still applied. This negative value of vGS is the threshold voltage of the n-channel depletion-type MOSFET. Thus a depletion-type MOSFET can be operated in the enhancement mode by applying a positive vGS and in the depletion mode by applying a negative vGS.

Triode regionBecause the threshold voltage Vt is negative, the depletion NMOS will operate in the triode region as long as the drain voltage does not exceed the gate voltage by more than |Vt|. That is

vDG < -Vt

vDS < vGS – Vt

theniD = IDSS [2(1 – vGS/Vt) (vDS/-Vt) – (vDS/Vt)

2]

Pinch-off regionFor the device to operate in the saturation, the drain voltage must be greater than the gate voltage by at least |Vt|.

vDG -Vt

vDS vGS – Vt

iD = IDSS ( 1 – vGS/Vt)2

Small-signal analysis of enhancement MOSFET For a given MOSFET, gm is proportional to the square root of the dc bias current.At a given bias current, gm is proportional to (W/L)1/2. Hence to obtain relatively large transconductance the device must be short and wide.

Transconductance of the bipolar junction transistor (BJT) is proportional to the bias current and is independent of the physical size and geometry of the device.

gm = (2nCox)1/2 (W/L)1/2 (ID)

1/2

Example

Consider the MOSFET with ID = 1 mA and nCox = 20 A/V2. Then transconductance of the device for different values of W/L ratio is

gm = 0.2 mA/V for W/L = 1

gm = 2 mA/V for W/L = 100

In contrast, a BJT operating at a collector current of 1 mA has gm = 40 mA/V. However, in spite of their low gm, MOSFET have many other advantages, including high input impedance, small size, low power dissipation, and ease of fabrication.