IC Mask Design - gbv.de
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IC Mask Design Essential Layout Techniques Christopher Saint Judy Saint McGraw-Hill New York | Chicago | San Francisco | Lisbon | London | Madrid Mexico City | Milan | New Delhi | San Juan | Seoul Singapore | Sydney | Toronto
Transcript of IC Mask Design - gbv.de
IC Mask Design Essential Layout Techniques
Christopher Saint
Judy Saint
McGraw-Hill
New York | Chicago | San Francisco | Lisbon | London | Madrid
Mexico City | Milan | New Delhi | San Juan | Seoul
Singapore | Sydney | Toronto
Contents
Introduction xiii Acknowledgments xv Open Letter to Circuit Designers xvii
Chapter 1 Digital Layout 1
Chapter Preview 1 OpeningThoughts on Digital Layout 1 Design Process 2
Verifying the Circuitry Logic 2 Compiling a Netlist 3
Drive Strength 4 Clock Tree Synthesis 5
Layout Process 7 Floorplanning 7
Block Placement 7 Gate Grouping 8 Block Level Connectivity 8 Using Flylines 9 Timing Checks 10
Placement 11 I/ODrivers 12
Routing 13 Power Nets 13
Strapping 14 Clock Net Wiring 15 Other Critical Nets 16 Remaining Nets 16 Finishing the Wiring by Hand 17
Prefabricated Gate Array Chips 18 Verification 19
Design Verification 19 Physical Verification 20
Vi | CONTENTS
GDSIIFile DRC and LVS Checks
Library Management Summary and Flowchart Closure on Digital Layout Here's What We've Learned
20 20 21 22 23 24
Chapter 2 Standard Cell Techniques 25
Chapter Preview OpeningThoughts on Standard Cell Techniques Standardized Grids
Grid-Based Systems Determining Grid Size Rule-Based Routers
Directional Layer Technique Library Rules for Grid-Based Systems
Input and Output Alignment Fixed Height, Variable Width Determining Wire Gauge Common N Well Half-Grid Cell Sizing Half Design Rule Routing Channels
Channel Routers Antenna Rules
Standardized Input and Output Cells UsingStandardization in Analog Mask Design Closure on Standard Cell Techniques Here's What We've Learned
25 25 26 26 26 28 29 32 32 34 35 35 37 38 39 43 45 45 46 47 48
Chapter 3 Analog Layout 49
Chapter Preview 49 Opening Thoughts on Analog Layout 49 Digital Skills vs. Analog Skills 50
Difference of Scale 50 Difference ofPrimary Objective 51 Difference of Teamwork 51 Difference of Completion Schedule 52 Difference of Innovation 52 Difference of Constraints 52 Difference of Understanding Circuit Techniques 53
Three Key Questions 53
Contents | vii
QUESTION 1: What does this circuit do? 55 QUESTION 2: How much current does it take? 56
Calculating Current Densities 57 QUESTION 2a: Where are the high and low current paths? 58 Device Orientation 59 QUESTION 3: What matching requirements are there? 64 Additional Questions 64
Bipolar Analog 65 Expectations of an Analog Mask Designer 66 Closure on Analog Layout 70 Here's What We've Learned 70 Appendix: Key Questions Discussion 71
Chapter 4 Parasitics 79
Chapter Preview OpeningThoughts on Parasitics Parasitic Capacitance
Wire Length Metal Selection Metal over Metal
Parasitic Resistance Calculating IR Drops Wiring Options
Parasitic Inductance Device Parasitics
CMOS Transistor Example Bipolar Transistor Example Füll Custom Options
Closure on Parasitics Here's What We've Learned
79 79 80 81 82 84 86 86 88 91 92 92 93 94 94 95
Chapter 5 Matching 97
Chapter Preview OpeningThoughts on Matching Importance of Layout Importance of Communication Simple Matching Root Device Method Interdigitating Devices Dummy Devices Common Centroid
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Cross-Quading Symmetry Matching Signal Paths Device Size Choices Closure on Matching Here's What We've Learned Rules of Matching
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Chapter 6 Noise Issues 121
Chapter Preview OpeningThoughts on Noise Issues Noisy Neighbors Common Sense Noise Solutions
Turn Down the Volume Rock Band Moves Inside Their House Go Inside Your Own House Close All Windows Call the Sheriff Move to a New Neighborhood
Wire Solutions Coaxial Shielding Differential Signals Decoupled Power Rails Stacked Power Rails Harmonie Interference
Closure on Noise Issues Here's What We've Learned
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Chapter 7 Floorplanning 141
Chapter Preview OpeningThoughts on Floorplanning Primary Drivers of Floorplanning
Pin-Driven Planning Effect ofPin Placement ESD Supply Strategies
Block-Driven Planning Signal-Driven Planning
Reshaping Blocks Sizing Estimates
Leaving Enough Room Estimating with Existing Circuitry
Closure on Floorplanning Here's What We've Learned
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Contents | ix
Chapter 8 General Techniques 161
Chapter Preview 161 General Techniques 161
#1 Pick Five or Six Non-minimum Design Rules 162 #2 Get Thee to the Lowest Parasitic Metal 165 #3 Plenty of Wide Wiring and Vias 165 #4 Don't Believe Your Circuit Designer 167 #5 Use a Consistent Orientation 168 #6 Don't Go Overboard 169 #7 Keep Off the Blocks 169 #8 Care for Your Sensitive and Noisy Signals Early 170 #9 If It Looks Nice, It Will Work 170
#10 Learn Your Process 171 #11 Don't Let Noise Find the Substrate 172 # 12 Spread Your Spinach around Your Dinner Plate 172 #13 Copy and Rename Cells before Making Changes 175 #14 Remember Your Hierarchy Level 176 #15 Build-in Easy Metal Revisions 177 #16 Draw Big Power Buses 182 #17 Break Up Large Circuits 184
Closure on General Techniques 184 Ancient Secrets of Mask Design 185
Chapter 9 Packaging 187
Chapter Preview OpeningThoughts on Packaging Bonding Methods
Ultrasonic Wedge Bonding Ultrasonic Ball Bonding Flip Chip Technology Multi-Tier Packaging
Issues in Packaging Overall Appearance 45-Degree Rule Minimal Silicon Overlap Wire Length Päd Distribution
Sizing Estimates Pad-Limited Design Core-Limited Design Package Maximum Check
Final Die Size Calculations Filling Päd Gaps Closure on Packaging Here's What We've Learned
187 187 188 189 190 191 192 193 193 194 195 195 196 197 197 199 200 200 206 207 208
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Chapter 10 Ver i f icat ion 209
Chapter Preview Opening Thoughts on Verification Checking Software
Design Rule Check (DRC) Boolean Command Lines
AND Function OR Function NOT Function
Rule Checking Command Lines Layout Versus Schematic (LVS)
Netlists Problem Solving
1. Check Number of Devices 2. Check Types of Devices 3. Check Number of Nets 4. Solving Complex Net Problems
a. Power Supplies b. Named Nets
5. Don't Trust Your Circuit Designer 6. Check for Possible Swapping Over 7. Check for a Top Level Short 8. Check for Ninja Invisibility 9. Know Your Circuits
10. Let Others Help Closure on Verification Here's What We've Learned
Chapter 11 Data Formats
Chapter Preview OpeningThoughts on Data Formats Industry Standard Database Formats
Header Information Coordinating Resolutions
Pattern Generation Know Your Grids Closure on Data Formats Here's What We've Learned
Case Study #1 CMOS Amplifier
209 209 210 211 211 212 214 215 218 220 221 222 222 223 224 226 226 228 229 230 232 232 233 234 234 235
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The New Job Assignment Bill Reasons His Floorplan Bill Thinks Through His Layout
247 255 259
Contents | x i
Ted Returns 272 Bill Rethinks 280 The Chip Is Assembled 304 Packaging 325 Appendix 326
Case Study #2 Bipolar Mixer 3 4 1
Introduction to Case Study 2 The Assignment
"What Does the Circuit Do?" "What Are the Circuit Requirements?"
Bipolar Transistor Review First Layout
Initial Overview Current Source
Transistors Resistors
Lower Pair Emitters Bases Collectors
Upper Quad Emitters Bases Collectors
Loads Output Resistors
Analysis of First Layout Bipolar Transistor Layout—Wrap-Around Technique Second Layout
Current Source Emitters Bases Collectors Resistors
Lower Pair Interdigitation Plan Emitters Collectors Bases Inputs
Upper Quad Interdigitation Plan
341 342 342 345 345 346 346 349 349 349 351 352 353 354 355 355 357 358 358 358 361 362 362 365 365 367 368 368 368 370 370 371 371 373 373 375 375
XÜ | CONTENTS
Emitters Collectors Bases Inputs
Loads Interdigitation Plan Resistors Outputs
Analysis of Second Layout Third Layout
Lower Pair Cross-Quading Plan Emitters Collectors Bases Inputs
Final Analysis Comparison of Case Study 1 and Case Study 2
Beglnnings The Four Engineers Outtakes Contact Us Suggested Readings and Resources Educational Programs Glossary Index
376 377 377 380 380 380 382 383 384 385 386 387 387 388 388 390 393 393
395 409 411 415 417 419 421 445
