IC Package, Assembly Technology

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An integrated circuit is a small but sophisticated device implementing several electronic functions.It is made up of two major parts: a tiny and very fragile silicon chip (die) and a package which is intended to protect the internal silicon chip and to provide users with a practical way of handling the component.

This presentation describes the various “front-end” and “back-end” manufacturing processes. This technology is used for the majority of the ICs manufactured.

I C – Integrated Circuit

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THE FABRICATION OF A SEMICONDUCTOR DEVICE

The manufacturing phase of an integrated circuit can be divided into two steps. The first, wafer fabrication, is the extremely sophisticated and intricate process of manufacturing the silicon chip.

The second, assembly, is the highly precise and automated process of packaging the die. Those two phases are commonly known as “Front-End” and “Back-End” that includes two test steps: wafer probing and final test

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Front End Process

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WAFER FABRICATION ( FRONT-END )

Identical integrated circuits, called die, are made on each wafer in a multi-step process. Each step adds a new layer to the wafer or modifies the existing one. These layers form the elements of the individual electronic circuits.

The main steps for the fabrication of a die are summarized in the following table. Some of them are repeated several times at different stages of the process. (The order given here doesn't reflect the real order of fabrication process.)

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Photo Masking Process

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Etching Process

Diffusion Process

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Metal Deposition Process

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Backend Process

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IC Packaging

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leadframe

plastic compoundwire

die pad

die attach

IC Package Compositionsilicon chip

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•Through-hole mount packages •Surface mount packages

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CompanySet-up

(Y1966)

His

tory Start IC

Assembly(Y1969)

Start IC Testing(Y1974)

Set up IC PKGDev’t Center(Y1987)

Start IC Wafer testing(Y1989)

QFP packageIntroduction (Y1992)

1966 1980 1995 2000 2005 (Year)

Matrix

LFBGA

HSOP-24

SO-14/16/24/32..5

6

QFP-32/48/..80

Resistor

capacitor

VSO-40/56

SIL-9

SIL-13/17/23

DBS37P

DIP-16/18/24…40

SDIP-24/32…64

SSOP-16/20

VSO-101

HDIP-18

LQFP48

QFP-100…208

TrimmerIntroduction(Y1968)

Film ResistorIntroduction(Y1969)

Packag

e D

istr

ibu

tion

QFP stacked die(QFP MCM)

Chip Sorting

BGA PKGIntroduction

(Y2000)

COF/Leadfree Introduction

(Y2002)/(Y2005)

TFBGA

HBGA

COF

Flip Chip

Package Roadmap (APK)

Dark Green compound Intro

(Y2006)

POP

2007

PoP sbSiP

(Y2007)

sbSiP

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LQFP208 Single Chip

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In past 7 years, APK delivered > 550Mpcs of MCP products

MCP (multi-chip package) products

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Stacked die product

In past 3 years, APK delivered > 100Mpcs of stack-die products

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APK MCP products

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OM48102OM6115

OM48102

OM48316

QFP100_3-stacked dies

LQFP100_4-stacked dies

OM48316

OM48102OM48102

Dummy

OM6115

Multi Chip Stacked Die

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Stack die assembly of QFP100

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APK stacked die productQFP100 (PCD80716H) QFP100 (PCD8017H) SDIP56 (SAA4849PS)

LFBGA228 (PCF5213-1) LFBGA81 (PCD87750) HTQFN48 (BGB204)

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PCD8017H

OM48316

OM48102

OM6115 OM48102

OM48102OM6115

OM48102

OM48316

QFP100_3-stacked dies RFS in Nov.’03

LQFP100_4-stacked dies to be evaluated

OM48316

OM48102

OM48102

Dummy

OM6115

Conception – for 4-stacked dies pre-development

Package thickness=2.8mmDie thickness=200um

Package thickness=1.4mmDie thickness=100um

Glue

B-stage/DAF

add a dummy spacer

Assy, F/T, Reliability test

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Bottom die - top die

L/F to top die(overhang)

Die-die-die bonding

BSOB under top die

APK 4-stacked die concept development

BSOB under top die

Overview

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- The BGT215 is designed for TV-enabled cellular handsets (TVoM). This complete, low-power front-end solution is the fast way to add TV functionality to a cellular phone.

- Related technologies :

- Flip chip on substrate

- Flip chip on die

- Stack dies

- Package : HLQFN 7x7x1.2 mm

- One lot reliability result available:

- MSLA passed Level 2

- THB 1000 hr passed

- 110 C UHST 264 hr passed

- TMCL 500 cycle passed

- About 16 K samples produced, assembly yield is about 98 %

BGT215 MCM with flipchip

Substrate

BBPICS

TUNER

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BGT215 Construction

Interconnect Tuner/PICS

Interconnect BB/substrate

Interconnect wire/Pics

Interconnect wire/substrate

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PNX0151 / LFBGA169

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PNX0151 / LFBGA169

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PNX0151 / LFBGA169

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(tbd)

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IC Package Assembly Process

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Glossary L/F – leadframe

Substrate; laminate; PI(poly-imide) tape; film

D/A - die bond, die attach

die attach, glue, epoxy glue, alloy, soft solder, DAF, die attach film

W/B - wire bind, ball-stitch bond

Au wire, AuPd wire, Cu wire, Al wire

T/M - transfer molding, molding, encapsulation

EMC(epoxy molding compound), compound, plastic

Deflash

M/K; L/M - marking, laser marking

T/P - tin plating, solder plating, plating, strip plating

D/J - dejunk; dambar cutting

T/F - trim/form, lead cut/bend

B/M - ball mount

S/G - sawing, singulation

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Leadframe

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Different Carriers : leadframe, laminate, film…

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Grind/Sawing Die Bond Wire Bond Molding

Trim/Form Plating

Wafer-test

Shipment

Wafer

Testing Marking

TAIWANP32P4910ABE2

C636604 9647SB

TAIWANP32P4910ABE2

C636604 9647SB

Typical Assembly Flow ChartTypical Assembly Flow Chart

CC+Cure

Cure

Dambar cut, D/J

PMCPacking

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Die bonding

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Glue dispenser -needle dispenser (dot)-pen writer (pattern)

•Glue volume/dispenser control•Die placement/bond force control

•Bond line thickness (BLT)•Fillet height•Glue wetting•Die position

Epoxy glue-normal oven cure (1-2hrs)-snap/fast cure (couple minutes)

curing

Die bonding

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Wire bonding

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Wire bonding

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Wire bonding

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1st bond (ball)

2nd bond (stitch)

•Metal peeling off (MPO)•Chip out under bond (COUB)•Incorrect ball size•Loose/lift ball bond•Losing tail•Ball short/shift•Ball deformation (e.g. golf)•Ball neck crack/broken

•Loose stitch bond•Misplaced stitch•Stitch broken

•Wrong wire loop•Wire damage/scratch•Wire short•Wire broken

Wire bonding – typical failure mode

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1st bond (ball) 2nd bond (BSOB)

Die 1 Die 2

Die-to-die wire bonding for MCM

Wire bonding – MCM

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top mold

bottom mold

transfer plunger

mold pellet air vent

primary runner

secondary runner

gate

void

Molding

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• Void (internal/external)

• Incomplete Fill

• Wire Sweep

• Wire Deformation/Broken/Short between

• Resin Bleed/Flash

• Mould Sticking

• Gate Remains • Body Chip Out

• Body Shift

• Die Crack

• Die Paddle Shift

de-gate

Molding – typical failure mode

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QFN package

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What is QFN?

QFN is a package in lead-frame based technology

With lower parasitic impedance and thermal resistance, small size and light, the package is suitable for middle to low pin count with high frequency applications

The cost is also low. For all the reasons, the package is now drawing high attention in the market

The external-exposed die-paddle and shorter wire path and leads have improved the power dissipation and reduced the parasitic impedance

The size of the package is around ½ of the size of QFP in the same pin count when replacing it with QFN.

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Source: Prismark

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Body size (mm) Lead count Thick (mm)

2.5x2.5 (or below) 4/8/10/12/14 0.85

3x3 4/8/10/12/16 0.85

4x4 12/16/20/24 0.85

5x5 16/20/28/32/36 0.85

6x6 20/28/32/36/40/48/52 0.85

7x7 28/32/44/48 0.85

8x8 32/40/52/56/68 0.85

9x9 36/44/60/64 0.85

10x10 44/52/68/72 0.85

12x12 88/100 0.85

Miniaturized body

High I/O

HVQFN standard configuration options

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HVQFN inside view

HVQFN bottom view

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Cross-section of HVQFN soldering Schematic of daisy-chain

PCB footprint design of HVQFN

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HVQFN cross-section

*Tape at the bottom of leadframe

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half-etching

HVQFN 5x5

* QFN L/F taping

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HVQFN 10x10

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Typical HVQFN assembly processDie attach

Glue curing

Wire bond

Plasma

Molding

Tape detach

Post mold cure

Deflash (chemical)

Laser marking

Sawing

Manual, to remove the tape on the backside of leadframe

Clean the leadframe to provide a better mold adhesion

Epoxy glue (soft-solder optioned for high thermal)

Au/AuPd wire

Plastic encapsulation for leadframe strip with backside taping

Remove plastic residue on exposed pads/lands

Laser mark product ID codes on package body

Sawing mold map into package unit

Oven cure for hardening molding compound completely

Oven/snap cure to solidify epoxy glue

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BGA package

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BGA – category in JEDEC

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BGA – substrate

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BGA

top side

bottom side

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BGA – substrate

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BGA – assembly flow

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BGA molding

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BGA fluxing (ball mount)

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BGA (fluxing ) ball mount

(fluxing)

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BGA ball mount defects

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IC Package MSL

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prec

ondi

tioni

ng

SHIPMENT

Reflow for SolderingReflow for Soldering245~260 °245~260 °CC

PCBPCB

Application

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What is MSL (Moisture Sensitivity Level)What happens to the product ?

1

3

2

4

MSL=1 : NOT moisture sensitive product

MSL>1 : Moisture sensitive product

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solder

solder

MSL levels applicable to :SMD packages

–in REFLOW soldering process

–in WAVE soldering process

MSL levels NOT applicable to :Through Hole packages (WAVE soldering)

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Source: Infineon

POPCORN

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MSLAssessment is used to:- Rate Moisture Sensitivity of package part

- MSL 1, 2, 3 etc.

- Determine safe packing method for delivery

- Dry Pack – Yes (L>1) or No (L=1)

- Determine safe handling procedures

- Let the customer know how to handle parts

- Prevent reflow related package failures (popcorn)

- No Customer Complaints

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Peak Body (Classification) temperatures defined by:

-Package Thickness (incl LF/ substrate)

-Package Volume

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MSLA Procedure

►SCAT Test - As received parts

►Moisturize parts - Condition for MSL level

►3x Reflow parts - Per JEDEC Profile

►( Electrical Test )

►SCAT Test

►Cross-section

►Rate MSL Level and Report

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Industry Specs:

–IPC/JEDEC J-STD-020C MSLA (July 2004)

–IPC/JEDEC J-STD-033 (Handling/Packing)

–Jeita ED4701

MSL levels vs floor life

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MSL levels and Peak Body temperatures are printed on packing labels to alert customers on how to handle.

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Handling Moisture Sensitive Packages

Keep parts in dry bags until use

Use Floor Life based on MSL level

Once dry bag is opened Floor Life Clock can’t be stopped

- Special 1 hour rule - can open and reseal bag within 1 hour

Short Duration Exposure rule - If parts exposed to factory ambient for less than 8 hours Floor Life clock can be reset by 5X exposure time in dry box (< 10% RH)

If parts exceed Floor Life they must be baked before reflow

For Failure removal from Board part must be dry and low temperature should be used

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External Cracks

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Internal Cracks Intersecting Bond Wire

Ball bond

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Internal Crack Extending to Lead Finger

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Internal Crack more than 2/3

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Swelling (popcorn)

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Die Lift

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Stitch/Downbond CrackingPLCC44 Stitch Cracks

SCAT inspection after MSL level 1.

SCAT inspection after MSL level 2. SCAT inspection after MSL level 3.

SEM photo of stitch bond crack after MSL SEM photo of stitch bond crack after level 1 test. MSL level 2 test.

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Die Delamination

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Delamination on Wire Bond Surface

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IC Package Reliability

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Reliability The probability that a IC package will perform a requiredfunction without failure– under specified conditions– for a stated period of time

First Level– Stand alone IC package, not soldered on a PCB– Second level: Board Level Reliability

First Level Reliability

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Probability: “Bath-tub Curve”

Failu

re r

ate

(

)

Time

Intrinsic FailureRegion

MTBF applied in this range

Wear OutRegion

0 168 hrs

1000 hrs

EarlyFailureRegion

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prec

ondi

tioni

ng

SHIPMENT

Reflow for SolderingReflow for Soldering245~260 °245~260 °CC

PCBPCB

Application

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Reliability Stress Test

PCBPCB

Precon TestPrecon Test((shipment and mountingshipment and mounting))

Environmental TestEnvironmental Test((field applicationfield application))

Test to asses the endurance of encapsulated semiconductor devices by “accelerating” the conditions in shipment, SMT & application

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preconditioning

Electr. M. / Inspection*

*Inspectione.g. SCAT

Reliability Stress Test Flow

temperaturecycling

unbiasedhumidity

biasedhumidity

hightemp. storage

Finished Products

Electrical Measurement / Inspection*

Electrical Measurement / Inspection*

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• HAST (UHST with bias): 130 °C / 85% RH Horizontal chamber

• Alternatives: - 85 °C / 85% RH (THB) - 110 °C / 85% RH

Biased humidity: HAST

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PurposeTo assess the sensitivity of non-hermetic packaged solid-state devices, after shipment (environmental stresses), to PCB mounting (hot convection reflow soldering)Conditions are according to the assessed Moisture Sensitivity Level (MSL)

PRECON Test

PCBPCB

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PurposeTo asses the endurance of non-hermetic packaged solid-state devices exposed to mechanical stress as a result of expansion and contraction by high and low temperature

Conditions -55/+125 °C or -65/+150 °C

TMCL Test

- 55 °CAir

125 °CAir

Expansion

Contraction

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PurposeTo assess the resistance of non-hermetic packaged solid-state devices to the effect of moisture intrusion

Conditions

PPOT: 121 °C, 100% RH (103.4 Kpa)

UHST: 130 °C, 85% RH (263 Kpa)

PPOT/UHST Test

PPOTCHAMBER

Accelerated intrusion of moisture

Towards electrochemically sensitive areas(e.g. die surface: bond pad corrosion)

Through the surrounding moulding compound

or directly via gaps, cracks and delaminated areas(as a result of Precon)

MoistureMoisture

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PurposeTo evaluate the reliability of non-hermetic packaged solid-state devices in humid environments where temperature, humidity, and bias accelerate the penetration of moisture

Conditions

THB: 85 °C, 85% RH with bias

HAST: 130 °C, 85% RH with bias

THB/HAST Test

THB/HAST

CHAMBERV

Accelerated intrusion of moisture & drift of impurities; extra driving force: E-field

Towards electrochemically sensitive areas; extra driving force: V(e.g. die surface: bond pad corrosion)

Tthrough the surrounding moulding compound

or directly via gaps, cracks and delaminated areas(as a result of Precon)

Moisture

V

-

--

++

+Emax = V / dmin

MoistureMoisture

VV

-

--

--

----

++

+

++++

++Emax = V / dmin

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PurposeTo asses the endurance of IC products when exposed to a high temperature for a long time period

Condition

150 °C

HTSL Test

HTSL150 °C

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Environmental Stress Test Abbr. Stress Conditions

Requirement

Highly Accelerated Stress Test HAST 130°C, 85% RH,biased

96 hr

Temperature Humidity Bias, Static/ Cycled Test

THBS/THBC

85°C, 85% RH,biased

1000 hr

Preconditioning PRECON per MSL,1/2(a)/3/4/5(a)/6

passlevel

Unsaturated Pressure Cooker UHST 130°C, 85% RH,unbiased

96 hr

Pressure Cooker test PPOT 121°C, 100 % RH, unbiased

96 hr

Temperature Cycling Test, (Condition C)

TMCL “C” -65°C to +150°C,unbiased

200 cls

Temperature Cycling Test, (Condition B)

TMCL “B” -55°C to +125°C,unbiased

500 cls

High Temperature Storage Test HTSL 150°C 1000 hr

Environmental Tests & Conditions

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PRECON: solder migration

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PRECON: external package crack

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PRECON: internal package crack

External crack

Delamination propagates into a package crack and severs the ball bond.

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PRECON: popcorn

SCAT / B-ScanSCAT / C-Scan

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PRECON/TMCL: die lift

die crack & delamination

diedie

underfillunderfilldelaminationdelamination

crackcrack

die lift

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PRECON/TMCL: Stitch Bond Break

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PRECON/TMCL: ballneck break

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PRECON/TMCL: bond ball lift

chip out under bond

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PRECON/TMCL: solder ball crack

Bump Crack (solder fatigue) as a result of delamination

DieDie

UnderfillUnderfill

Bump CrackBump Crack

BumpBump

Flip Chip - PASSI on laminate: CTE- mismatch between substrate and die- solved by selection and applying underfill

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TMCL: passivation crack / pattern shift

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TMCL: package Crack

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PPOT/UHST/THB/HAST:wet bondpad corrosion

Micro gap

Ionmigration

Moisturepenetration

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PPOT/UHST/THB/HAST:dendritic growth & leakage path formation

Pin 6 Pin 7

Ag dendrite formation / current leakage

Cu dendrite formation / current leakage

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THB/HAST: charge creep

HV (x100 V)

- +

• no catastrophic failure;

• but a leakage resulting in circuit malfunction (reversible, can be baked out)

Circuit malfunction in high voltage devices (typically a few hundred volts) due to charge accumulation at the silicon-to-plastic interface

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HTSL: dry corrosion

ball delamination

Cu

Cu9Al4

CuAl

CuAl2

Al

Delamination starting at ball edges

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HTSL: Kirkendall voiding

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