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Transcript of IBM T. J. Watson Research Center Frontiers of Extreme Computing, October 25 2005 Presentation...
IBM T. J. Watson Research Center
Frontiers of Extreme Computing, October 25 2005 © 2005 IBM Corporation
Device Technology and the Device Technology and the Future of ComputingFuture of Computing
Thomas N. Theis, Director, Physical Sciences, IBM Research
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 2
Moore’s Law is an observation about the number of devices that can be placed on a chip at a given time.
There is no fundamental physical reason why device densities cannot follow the Moore’s Law trend for many more decades.
– Lithographic dimensions will eventually be shrunk to atomic scale and lithographic processes can seamlessly combine with synthesis.
– New devices can circumvent the scaling limits of FETs.
My view…
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 3
Making devices smaller is not the problem!
Silicon CMOS Technology will be extended for at least a decade
The “ultimate” FET may not be made of silicon
Non-silicon memory devices will scale to very small dimensions. New devices may enable adiabatic computing and reversible logic.
Topics
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 4
0.0001
0.001
0.01
0.1
1
10
100
1000
1800 1850 1900 1950 2000 2050 2100
Min
imu
m m
ach
ine
d d
ime
nsio
n (
mic
ron
s)
A Brief History of Miniaturization
Moore’s Law (1965)
90 nm Manufacturing (2004)
193 nm immersion
2004 commercial niche lithographies
2004 best lab practice
industry roadmap
EUV
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 5
The silicon transistor in manufacturing …
35 nmGate Length
90 nm technology generation
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 6
… and in the lab.
TSi=7nm Lgate=6nm
Source Drain
Gate
B. Doris et al., IEDM , 2002
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 7
Still, we are approaching some limits.
0.010.110.001
0.01
0.1
1
10
100
1000
Gate Length (microns)
Active Power
Passive Power
Po
wer
Den
sity
(lo
g s
cale
)
1.0 0.1 0.01Gate Length (microns)
1.0 0.1 0.01
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 8
min
IBM Confidential 0.4 s per frame
Total ~ 80s
Filmstrip during bootup:
Thermal images during bootup:
max
Active Power Can Better Managed!Thermal Mapping of Fully Operating IBM Microprocessor (2 GHz, 1.4 V) in a System Environment
H. Hamann (IBM), ISSCC 2005
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 9
Access to data cache Access to memory controller
Te
mp
era
ture
sP
ow
er
map
data cache
data cache
memorycontroller
memorycontroller
max
min
Better Information for Layout and High-level Design
H. Hamann (IBM), ISSCC 2005
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 10
The Problem with Passive Power Dissipation:You Can’t Scale Atoms!
Direct tunneling through the gate insulator will be the dominant cause of static power dissipation.
Single atom defects can cause local leakage currents 10 – 100x higher than the average current, impacting reliability and generating unwanted variation between devices.
Field effect transistor
Source Drain
Gate
1.2 nm oxynitride
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 11
10S Tox=11A
High-k/Metal Gate Stack
90nm Gate Dielectric:Tinv = 19AToxGL = 11A
High-k/Metal Gate Stack:Tinv = 14.5AToxGL = 16A
90nm SiON
The Work-Around: High-k Insulator / Metal Gate Stack
Oxide interlayer
High-k material
Metal gate electrode
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 12
Improving Performance
Since the 90’s7
nitrogen
N
9
fluorine
F
Before the 90’s
1
hydrogen
H5
boron
B
8
oxygen
O
15
phosphorus
P14
silicon
Si
33
arsenic
As
Device Elements:
20
calcium
Ca
38
strontium
Sr
56
barium
Ba
43
Ruthenium
Ru
77
iridium
Ir
45
rhodium
Rh
27
cobalt
Co
78
platinum
Pt
45
palladium
Pd
28nickel
Ni
35Br35Bromine
Br30
zinc
Zn32
germanium
Ge
83
bismuth
Bi
6carbon
C
2
helium
He
57
lanthanium
La
58
cerium
Ce59
Praeseodymium
Pr
60
neodymium
Nd
62
samarium
Sm
63
europlum
Eu
64
gadollinium
Gd
65
terbium
Tb
66
dysprosium
Dy
67
holmium
Ho
68
erbium
Er
69
thullium
Tm
70
ytterbium
Yb
22Ti22titanium
Ti
74
Tungsten
W74
tungsten
W73
Tantalum
Ta73
tantalum
Ta
39yttrium
Y
71
barium
Lu
40
zirconium
Zr
72
hafnium
Hf
23
vanadium
V
41
niobium
Nb
24
chromium
Cr
42molybdenum
Mo
75
Rhenium
Re
21
scandium
Sc
Beyond 2005
No longer possible by scaling alone– New Device Structures
– New Device Design point
– New Materials
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 13
Innovation Will Continue: Transistor Roadmap Options
2004 2007 2010 2013 2016 2020
37 nm 25 nm 18 nm 13 nm 9 nm 6 nm Physical Gate
Double-Gate CMOS
depletion layer
isolation
buried oxide
halo
raised source/drain
Silicon Substrate
doped channel
High k gate dielectric FinFET
Strained Si, Ge, SiGe
isolation
buried oxide
Silicon Substrate
Ultrathin SOI
In general, growing power dissipation and increasing process variability will be addressed by introduction of new materials and device structures, and by design innovations in circuits
and system architecture.
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 14
SLm-1
SLm+1
SLm
WLn-1
WLn+1
WLn
Memory may be easier to shrink than logic.
Everyone is looking for a dense (cheap) cross-point memory. It is relatively easy to identify materials that show bistable hysteretic
behavior (easily distinguishable, stable on/off states).
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 15
Relative Maturity of Nonvolatile Memory Technologies
02468
101214161820
ProductSampling
Development Single CellDemo
Charts, NoParts
Tech
nolo
gy C
ham
pion
s (C
ompa
nies
)
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 16
16Mbit Magnetic Random Access Memory (MRAM) Demo
• 4 active bits / block
• Good power supplydistribution
• Write currentstrimmed by block
Pads / peripheral circuits
Redundancy control &Write current trimming
Pads / peripheral circuits
8Mbunit
4 active 128Kb blocks
8Mbunit
• 4 active bits / block
• Good power supplydistribution
• Write currentstrimmed by block
Pads / peripheral circuits
Redundancy control &Write current trimming
Pads / peripheral circuits
8Mbunit
4 active 128Kb blocks
8Mbunit
Chip image: Cross-section:
MTJ
-2000 -1500 -1000 -500 0 500 10000
20
40
60
80
100
120
140
a258-03 J4
MR
(%
)
Prior to Anneal Anneal 360°C
-200 -100 0 100 2000
20
40
60
80
100
120
140
Field (Oe)
1995
TM
R (
%)
Field (Oe)
Materials Advances
-150 -100 -50 0 50 100 1500
50
100
150
200
250
300
350
400
TM
R (
%)
290K
Field (Oe)Field (Oe)
2005
TM
R (
%)
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 17
Post-Silicon CMOS: The Quest for the Ultimate FET
W200nm
Self-Aligned Carbon Nanotube FET: Extension Contacts Based on
Charge-Transfer Chemical Doping
Vertical Transistor Based on Semiconductor Nanowires
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 18
10-5
10-4
10-3
10-2
10-1
100
101
|Id| [
A]
-2 -1 0 1 2
Vgs [V]
Vds -0.7 V -0.5 V -0.3 V -0.1 V
20
15
10
5
0
|Id|
[A
]
-1.2 -0.8 -0.4 0.0
Vds [V]
-1.2 V
-0.8 V
-0.4 V
0 V 0.4 V
Vds = -1.6 V
12
8
4
0
gm
[S
]
-2.0 -1.0 0.0 1.0Vgs [V]
90 K 300 K
Pd Pd
nanotube
Subthreshold Characteristics
Output Characteristics
Temperature dependence
Simple back-gated CNTFET
Intrinsic Performance of Cabon Nanotube FETs
Yu-Ming Lin et al. (IBM), EDL 2005
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 19
2m
Tg
gf
CCut-off Frequency
Lin et al.(IBM)
Javey et al. (Stanford)
Seidel et al. (Infineon)
Diameter ~ 1.8 nm ~ 1.7 nm ~ 1.1 nm
Gate Dielectric 10-nm SiO2 8-nm HfO2 12-nm SiO2
Maximum gm 12.5 S 27 S 3.5 S
Cg/L 38 pF/m 120 pF/m 32 pF/m
fT @ Lg = 65 nm 800 GHz 550 GHz 260 GHz
Cg : gate capacitance
Intrinsic Switching Speed of CNFETs
Yu-Ming Lin et al. (IBM), EDL 2005
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 20
Dual-Gate CNTFET
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
I d (A
)
-1.2 -0.8 -0.4 0.0
Vg-Al (V)
Vgs-Si = -2.5 V
S=63 mV/dec
Bulk switching
Sub-thermal S through band-to-band tunneling
Steep Sub-threshold Slopes for Low-Voltage Operation
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 21
Adiabatic Computing and Reversible Logic
Can we operate FETs at or below the “kT” limit?
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 22
How much energy must be dissipated to charge a capacitor?
Adiabatic Computing
Trade-off depends strongly on
device physics!
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 23
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 24
Applications of Adiabatic Charging
Drive specific capacitances which cause large dissipation.
– Power supplies
– Energy conserving data bus drivers
Broadly implement reversible logic.– Retractile cascade, reversible pipelines
– High-efficiency regenerative power supply (very complex)
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 25
Reversible Logic: Implementation with FETs
It is conceptually possible to build general purpose reversible computers with energy dissipation per operation going asymptotically to zero as frequency goes to zero.
But, frequency must be reduced by about 1/1000 to achieve benefits with respect to conventional approaches to CMOS logic.
Dissipation of 4 bit ripple counter (D. J. Frank, 1995)
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 26
Recent Optimized Power vs Frequency Assessment
DJ Frank, MIT Workshop on Reversible Computation, February 14, 2005
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 27
Qualitative Overall Comparison
TSPC (a fast non-energyrecovering dynamic CMOS logic family)
2N-2N2P (an energy-recovering logic family)
Conventional CMOS with fixed supply
Highly reversible
Scaled static CMOS (estimate)
DJ Frank, MIT Workshop on Reversible Computation, February 14, 2005
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 28
Are there devices that are better suited than FETs for the implementation of
reversible logic?
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 29
Beyond Charged-Based Logic?
Spins
Photons
Nanomechanics
DNA Chemistry
p -GaAssubstrate
+
AlGaAs
GaAsquantum wellEF
MgO
AVT IC
CoFe
Collector
Magnetic Field
e-
Luminescence AlGaAs
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 30
Nanoelectronics Research Initiative (NRI) AMD, Freescale, Micron, TI, IBM, Intel
Joint Industry funding of University Research
Leveraging existing NSF and new (joint NSF/NRI) funding
Promoting both – Invention / Discovery (distributed research, “let many flowers bloom”)
– Proof of Concept (focused university consortia with outstanding facilities)
“Extend the historical cost/function reduction, along with increased performance and density … orders of magnitude beyond the limits of CMOS”
– Non-charge-based logic
– Non-equilibrium systems
– Novel energy transfer mechanisms for device interconnection
– Phonon engineering
– Directed self-assembly of complex structures
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 31
Conclusions
Silicon CMOS logic will be extended at least another 10 years. – New materials and transistor structures
– Cooperative circuit and device technology co-design
The “ultimate FET” may not contain silicon.
New, dense, cheap memory devices are on the way.
Reversible logic is possible, but may be practical only with devices that are “beyond the FET”.
The search for logic devices “beyond the FET” is underway,(but there should be more focus on devices suitable for adiabatic computation and reversible logic)
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 32
Thanks!
IBM Research
© 2005 IBM CorporationFrontiers of Extreme Computing, October 25, 2005 33
Non-Si FET The potential of carbon nanotubes (CNT)
– Metallic & semiconducting nanotubes: interconnects (up to ~109A/cm2) & switches.
– 1D transport (low elastic and inelastic scattering low energies, ballistic or quasi-ballistic transport, fT≤1THz.
– Low energy dissipation (power density problem, no electromigration)
– Good control of electrostatics (“thin body devices”, no mobility degradation).
– Inert (no dangling bonds to passivate, wide choice of gate insulators – high k materials)
– Direct band-gap materials (integrate electronic & opto-electronic devices using the same material).