IBM Research | IBM - On-chip Interconnect: Design and ......2 independent measurement sessions...

IBM Labs in Haifa© Copyright 2004 IBM Corporation

On-chip Interconnect:Design and Modeling

Methodology

Presented by: David GorenIBM Haifa Research Lab

IBM Burlington Design Automation Dept

IBM Labs in Haifa

© Copyright 2004 IBM Corporation

2

Major Events

� June 1998 – Research starts at IBM Haifa Research Labs

� January 2000 – Start of joint work with MD (Burlington) Design Automation Department

� January 2001 – T-line Geometries + models inside IBM Design kit

� December 2002 – IBM Research Accomplishment Award

� Up to May 2004 – 8 IEEE papers published + 4 patents filed (more in preparation…)

Key players:

� HRL: David Goren, Rachel Gordin, Shlomo Shlafman, Roi Carmon, Israel Berger

� MD: Wayne H Woods, Essam Mina

IBM Labs in Haifa


3

High speed Silicon chip design: The costly methodology gap

� Analog & mixed signal design methodology is not adequate � State of the art in interconnect extraction is mostly RC. Even around

1GHz, inductance starts to impact longer lines behavior� Fully automated inductance extraction is impossible without exact

knowledge of the return paths, which is not always practical at post layout extraction

� Post layout extraction for high frequency design is usually too late

� Microwave design methodology is not adequate as well� Traditional microwave concepts (Impedance matching, S - Matrix)

are not applicable for many A&MS designs � Fully nonlinear, large signal transient SPICE simulations required� Mixed signal simulations required

IBM Labs in Haifa


4

Proposed solution :

� Combine design automation with designer’s wisdom

� On chip Interconnect Design of critical wires rather than extraction� Use predefined T-line geometries as parameterized design templates� Support the specific technology details (given metal stack, copper..)� Semi-Analytical, high bandwidth, time & frequency domain models –

optimized for the specific technology bandwidth (today from DC up to 200 [GHz] !)

� Easy usage in different circuit simulators and design environments� Support all simulation kinds: transient, AC, PSS, S-param, mixed-mode� Easy custom modeling for specific designs (HSS, RFICs).

IBM Labs in Haifa


5

HRL-MD Solution (patent filed) :The interconnect-aware design flow

� Sorting wires into 2 groups: � critical, small group� non-critical, most of the wires

� Design of critical wires:� Predefined set of parametrized T-line

structures as design components� Pcell based: T-line device =

symbol+schematic+layout views � DRC and LVS clean layout� Monitoring T-line parameters is

enabled

� Smart extraction� Use T-line models for critical wires� Use RC extract for non-critical wiring -

sufficient accuracy� Back-annotate final T-lines parameters

Schematic design including T-line models

Smart Extraction

Physical Design. T-lines as p-cells

Final Simulation

High Level Design

FloorplanArchitecture

Identify critical interconnect

Vision: On-chip T-lines become an industry standard.

IBM Labs in Haifa


6

Production level T-line cross sections (1)

Microstrip T-lines�

�

��

�

��

�

via

via

��

�

via

via

IBM Labs in Haifa


7

Production level T-line cross sections (2)

Coplanar T-lines

��

��

��

��

IBM Labs in Haifa


8

IBM T-line model interface in Cadence environment

IBM Labs in Haifa


9

Estimation of crossing line effects(patent filed)

�

�

�

Power grid

��

��

��

��

��

Bus

IBM Labs in Haifa


10

IBM On-Chip T-line Modeling :

Optimalgeometry

Semi-AnalyticModeling

Equivalent RLC

network

� Closed electromagnetic environment� Only Physics-based semi-analytical explicit expressions are used� Inherent passivity by construction � Full bandwidth RLC networks (from DC to FT)� Verified by measurments up to 110 GHz, by EM simulation up to 200[Ghz]� Covers both skin effects and silicon substrate effects

Previous approaches:Previous approaches:�� Trying to solve undefined electromagnetic environmentTrying to solve undefined electromagnetic environment�� Mainly numerical approaches ( convergence, time & accuracy problMainly numerical approaches ( convergence, time & accuracy problems)ems)�� Many suffer from stability problemsMany suffer from stability problems

Our approach:Our approach:

IBM Labs in Haifa


11

Modeling technique:ZY-network

��

��

��

��

!

"

!

"

!

"

!!##��$��$��

�#��

!

"

""##��$��$��

��

��

��

IBM Labs in Haifa


12

Modeling the Z-element:problem description

��

�

��

��

%��

��

��

��

�

��

��

�� !��"��#�� !��"��#��

��#��!��$��#��!��$��

IBM Labs in Haifa


13

Modeling the Y- element:problem description

��

�

��

�

��

��

�

��

��

s

s

�21

relf�

�

�

�� $��

�� !��

IBM Labs in Haifa


14

On-Chip T-line test cage

IBM Labs in Haifa


15

Hardware measurements setup�2 independent measurement sessions performed in IBM

Haifa and Burlington on different units of the same test chip. In Burlington, top polyamide passivation removed

� IBM Burlington: Agilent HP8510XF 110GHz 2-port Vector Network Analyzer, used for single T-lines; LRRM calibration on standard alumina substrate

� IBM Haifa: Agilent 8720ES 20GHz Vector Network Analyzer with an ATN-4112A 4-port unit, used for both single and coupled T-lines; SOLT calibration on standard alumina substrate

� Balanced (GSG & GSGSG) coplanar probes used in both cases

� Combined Y and Z-parameter parasitics de-embedding for bottom shielded on-chip pads in both cases

IBM Labs in Haifa


16

Measured S-parameters of bent T-line structures versus their straight reference

%�� &'� �� (�� )��

��&��' ��&��'

��&��'��&��'

IBM Labs in Haifa


17

S-parameters of a single T-lineNew generation model

�� *�� ++��,-�� *��" ./��$�� !��#��)�

��&��' ��&��'

��&��'��&��'

IBM Labs in Haifa


Vision:on-chip T-lines will be in any chip technology

and EDA environment

Models interact with other tools:-Extractors-SubstrateStorm-VoltageStorm

+ ASIC, VLSI

Scalablemodels

Power grid modeling

+ SoC

Partially autonomous models (someinteraction with design neighborhood )

Dense A&MS designs

Fully autonomous models (closedenvironment):Sparce A&MS Designs, microwave

Development of BEOL (PCell based) design methodology

More design automation is requiredMore design automation is required

IBM Labs in Haifa


19

Custom design example – 4:1 transformer at 60[GHz]Simulated only Performance(to be measured):

�26 dBm (400mW) RF power at 60GHz�Up to ±9V voltage swing in 100�

(BVceo = 1.7V)�20 dB gain (two stage)�Wilkinson power divider used to

distribute input power �Extremely compact design�Can be used for input impedance

transformation too

Wilkinson Divider

Transformer

Input StageWilkinson Power Divider

IBM Labs in Haifa


20

Patents/Publications1) Patent filed: David Goren et al, "An Interconnect-Aware

Methodology for Integrated Circuit Design", Pat. No. 10/091,934 filed March 6 (2002)

2) Patent filed: Rachel Gordin, David Goren and Michael Zelikson“Interconnect-Aware integrated circuit design” Pat. No. 10/723,752 filed November 26 2003.

3) Patent filed: Rachel Gordin and David Goren, “Modeling Capacitance of On-Chip Coplanar Transmission Lines over the Silicon Substrate”

4) Patent filed: David Goren et al, “Device and method for reducing dishing of critical on-chip interconnect lines”

5) D. Goren et al, "An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40GHz) on-chip Transmission Line Approach", IEEE DATE02 Conference, Paris, March (2002).

6) R. Gordin, D. Goren and M. Zelikson, "Modeling of On-Chip Transmission Lines in High Speed A&MS Design - The Low Frequency Inductance Calculation", IEEE Signal Propagation On Interconnects Conference, Pisa, May (2002).

IBM Labs in Haifa


21

6) D. Goren, M. Zelikson and R. Gordin, “Interconnect-Aware Design Methodology for Analog and Mixed Signal Design in Silicon Based Technologies using High Bandwidth On-Chip Transmission Lines”, IEEE 2002 conference in Israel.

7) D. Goren, Rachel Gordin and Michael Zelikson, “Modeling Methodology for On-Chip Coplanar Transmission Lines over the Lossy Silicon Substrate”, IEEE Signal Propagation on Interconnects conference, Siena (2003).

8) R. Gordin, D. Goren and M. Zelikson, “Study of On-Chip Coplanar Transmission Lines over the Lossy Silicon Substrate”, IEEE Signal Propagation on Interconnects conference, Siena (2003).

9) D. Goren et al, “On-Chip Interconnect-Aware Design and Modeling Methodology, based on High Bandwidth Transmission Line Devices”, IEEE DAC 2003 conference, Anaheim 2003.

10)R. Gordin and D. Goren, “Modeling Capacitance of On-Chip Coplanar Transmission Lines over the Silicon Substrate “, IEEE Signal Propagation on Interconnects Conference (2004).

11)Thomas Zwick, Youri Tretiakov and David Goren, On-Chip Transmission Line Measurement and Modeling in IBMs SiGeTechnology up to 110GHz, IEEE Microwave and Wireless Components Letters

IBM Research | IBM - On-chip Interconnect: Design and ......2 independent measurement sessions...

Documents

Transcript of IBM Research | IBM - On-chip Interconnect: Design and ......2 independent measurement sessions...