IBIS MODELING FOR WIDEBAND EMC APPLICATIONS

Razvan A. Ene

High Design Technology - Italy

DAC 1999 - New Orleans - USA

Modeling for EMC and High

Frequency Devices

1

High Design Technology

2


• What degree of accuracy of the models

is needed in order to correctly simulate

the signals and the radiated

electromagnetic field of PCBs?

• A way of avoiding such precise

description using IBIS models is

foreseen.

Motivation 3


• Why predict S.I. and e.m. emissions?

• Device modeling and related problems

• Electrical modeling for EMC

• Comparison with measurements

• Conclusions about S.I. and EMC

simulation

• Improving IBIS

Topics of Discussion 4


Considering S.I. & EMC aspects in PCBs

only through compliance tests on the

first prototype raises some problems

• completion date

• costs

Solution: Predict wave forms & radiated

emission at the design stage using

post-layout simulation

Why predict S.I. & e.m. emission? 5


C_comp

L_pkg R_pkg

C_pkg

1

23

4FallRise

5

Elements of an IBIS Model 6


Device modeling (for S.I.)

SUBCKT name 1 2 10 20

COUT 2 0 value

RSWVCC 7 2 1 0 PWL(0V 1E6 1V 0 2V 0) C=2P

PVCC 7 8 1_static_char C=2P

E1 8 9 1 0 dtf stf 0.1NS

VCOMP 10 91 DC(5)

Bvcc 91 9 dtf2

RSWGND 17 2 1 0 PWL(-1V 0 0V 0 1V 1E6) C=2P

PGND 17 18 0_static_char C=2P

Bgnd 99 19 dtf2

TD 99 20 C=6P

.ENDS name

o u t

v c c

g n d

C o u t

2

1 0

2 0

P v c c

V c o m p

E 1

R S W v c c

+

+

P g n d

R S W g n d

+

E 0

T d

S T F

S T F D T F

D T F

1

i n

B v c c

B g n d

7



• name is the name of the electrical

model

• value is the value of the

output capacitance

• 0_static_char is the static characteristic

of the output at "0" logic level

• 1_static_char is the static characteristic

of the ouput at "1" logic level

I

Vv 1 , i 1

v n , i n

I

V

v 1 , i 1

v m , i m

5

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•stf is the static transfer function

of the output

• dtf is the dynamic transfer function

of the output

• dtf2 is the dynamic transfer function

of the clamping diode

v o u t

v i n0 . 5

5

s ( t )

t1 N

1

s ( t )

t

- 1

9


Measuring the D.T.F.of the output impedance

TDR

BIAS

DUTlaunchcable

biasprobe

power supply

controllaunch cable

DUT

gnd plane

gnd

connection

power supply

decoupling capacitor

bias

bias probe

The bias probe is used to setup the bias condition at the DUT pin. It can be a simple 10kW 1/8W resistor or a series of a 3.3mH inductor and a 330W 1W resistor (the inductor on the DUT side). The purely resistive probe can be used for biasing CMOS input stages, because no biasing current is required. The RL probe is needed to bias output stages or input clamping diodes, that require a current source or sink at DUT pin.

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Actual TDR responses of the AC74 input in

clamping condition for two foundries

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00

TIME[nS] -1.00 rho

-0.75 rho

-0.50 rho

-0.25 rho

0.00 rho

0.25 rho

A

B

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Simulated response of an inter- connection between two AC74

50.00 55.00 60.00 65.00 70.00 75.00 80.00

TIME[nS] -2.00 V

-1.00 V

0.00 V

1.00 V

2.00 V

3.00 V

4.00 V

5.00 V

B

A

Only the dynamic response of the ground protection diode is

different in the simulations A and B

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Identifying the problem

C_comp

L_pkg R_pkg

C_pkg

1

23

4FallRise

5

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Silicon implementation Concentrated vs. distributed clamp diodes

small inductive effect large inductive effect

dedicated clamp diode distributed protection diode

fast clamping slow clamping

over shoot

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Simulation vs. measures at 155Mb/s

Comparison between

simulation and

measures of high-

speed multiboard

system (155Mbit/s)

* 50000 elements

* 32 simultaneous

input sequence

* 16000 time points

* 25 min. simulation

time ( SUN Ultra 1)

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Important factors

• physical layout on the die

• spreading of the parameters

• accurate problem description

• adequate modeling of the problem

• high precision instrumentation

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Some equivalences

• wide band models = accurate time

domain characterisation (depends on

your simulation engine)

• accurate simulation of the waveforms =

accurate model of the components

actualy mounted on the PCB

Wasn’t all about design phase?

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EMC measurement setup

• Semi-anechoical room at Lille

University

• Measurements in far field

• The geometry:

3 m

1.7 m0.7 m

shielded oscillator

antenna

ground floor

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Test case

PCB with one microstrip

10 MHz CMOS oscillator

Shielded box

PCB local

plane

tfall=2.18 ns

Period of 100 ns

trise=2.76 ns 5 Volts

Source: Digital gate AC 244

50W

PCB track10Mhz

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Problems

Predicted e.m. field is very different from

the measurements although we used:

• Accurate models for vias, pins and

microstrip

• Special precautions in order to ensure

lack of parasitic effects

• Green transfer function

Driver model

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Electrical modeling for EMC

• modify dtf in the device model

• in IBIS is given as a slope

Measure dtf using a good probe (with

low parasitic parameters)

• insert a dtf block instead of Cout in

the model

Measure it using a Time Domain

Reflectometer (TDR)

v o u t

v i n0 . 5

5

s ( t )

t1 N

1

s ( t )

t

1

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Electrical modeling for EMC

TDR

BIAS

DUTlaunchcable

biasprobe

power supply

controllaunch cable

DUT

gnd plane

gnd

connection

power supply

decoupling capacitor

bias

bias probe

• Measuring dtf

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Frequency spectrum of the signals

0.01 0.11 0.21 0.31 0.41 0.51 0.60 0.70 0.80 0.90 1.00

FREQ[GHz]

-100.00

-90.00

-80.00

-70.00

-60.00

-50.00

-40.00

-30.00

-20.00

-10.00

0.00

10.00

dBV

genericmodel

specialmodel

measured

Validity limit forgeneric model

Validity limit forspecial model

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Signals on the trace

100.00 110.00 120.00 130.00 140.00 150.00 160.00 170.00 180.00190.00 200.00

TIME[nS]

-1.00 V

-0.50 V

0.00 V

0.50 V

1.00 V

1.50 V

2.00 V

2.50 V

3.00 V

3.50 V

4.00 V

4.50 V

5.00 V

5.50 V

simple model

special model

measured

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EMC spectrums

IMPORTANT OBSERVATION: Although is a low speed circuit, EMC simulation requires a model valid until VERY HIGH frequencies

2 5


Conclusions

• Good agreement with measurement is

obtained using appropriate models and

simulation techniques

• The algorithm and modeling techniques

are thus validated

• The aim of the designer is to keep the

radiated fields under the standards, i.e.

a worst case analysis

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Conclusions

• During design phase is not realistic to

measure each component (remember

also the spread in the components

characteristics)

• Make use in an appropriate mode of

the typical, min. and max. values in

IBIS model (EMC compliance = Signal

Integrity = Timing Simulation)

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Advises for a successful designer

• have fully knowledge of the advantages

and limitations of your simulation engine

• have clear ideas about what simulation

can give, and what practical use one can

make of the results

• make appropriate choice of the model

parameters (it is more usefull having the

spreading rather than a single

measurement)

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Improving IBIS

• fill in all min. / max. fields

• introduce a field that, for critical

parameters like Cout, gives the

statistical distribution of the values

spreading

• revive the Rise and Fall waveform

voices, in order to handle corectly

the waveforms of the open output

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Improving IBIS

• introduce supplementary fields in order

to support the TDR measurements of

the dynamic behaviour of the output

impedance in both normal and

clamping condition (high and low

level); in this way even far more

complex problems can be addressed

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IBIS MODELING FOR WIDEBAND EMC APPLICATIONS

Technology

Transcript of IBIS MODELING FOR WIDEBAND EMC APPLICATIONS