I3C V1.1 Family for Sensor and IoT Applications...Clock Domain Crossing Synchronization HDR Engine...
Transcript of I3C V1.1 Family for Sensor and IoT Applications...Clock Domain Crossing Synchronization HDR Engine...
I3C is a new a standard from the MIPI Alliance that unifies and extends the legacy interfaces of I2C and SPI and adds new powerful features to support modern mobile, automotive, and IOT applications. The range of I3C products from Silvaco allows customers to take full advantage of the high performance and low power features of I3C V1.1.
I3C V1.1 Family for Sensor and IoT Applications
ApplicationsOverview• Mechanicalsensing(Gyroscopes,MEMS,etc.)
• Environmentalsensing(Light,pressure,temperature,humidity,etc.)
• Biometrics(Fingerprinting,glucose,heartrate,breathalyzer,etc.)
• Communication(Near-fieldsensors,infraredremotes,etc.)
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MagnetometerTarget
GyroscopeTarget
AccelerometerTarget
Ambient LightTarget
PressureTarget
HumidityTarget
TemperatureTarget
Application Processor
ColdFireCPU
RTC/WDTTimer
SoundWire
ColdFireCPU
MEMORIES
NVM SECURITY
ADC
DATAPATH
I3C
CAN FD
CAN
LIN
FLEXRayUART
AMBA INTERCONNECTFABRIC
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Sensor Connections
SCL I3C
SDA
APB APB Registers
I3C MainController
I3C SecondaryController
I3C Advanced
Target
I3C Autonomous
TargetI2C
Target
MCUSubsystem
MCUSubsystem
GlueLogic
GlueLogic
I3C Controller
2-5
The I3C Advanced Controller is a highly configurable I3C controller that can be used in microcontroller-basedenvironments to provide I3C connectivity to any device. It contains controller capabilities as well as many of the same features as the I3C Advanced Target. It can be configured in a number of different ways to allow the core to use the minimum amountoflogictoreducebotharea(cost)andpower.
Features• Highlyconfigurablecorethatallowscustomertominimize
unneeded logic
• CompliantwithMIPII3CV1.1specification
• Dynamicaddressing
• SingleDataRate(SDR)
• Errordetectiontypes(S0-S5,M0,M2,M3)
CLK APB INT DMA
SDA/SCL
InterruptsDMA
& Flow ControlMemory Mapped Registers
Clock Domain Crossing Synchronization
HDREngines
SDR TargetEngine
CCCHandling
DynamicAddress
Assignment
Block Diagram
I3C Advanced Controller• AdvancedI3Cfeatures
• HDR-BTwithupto100Mbpsbandwidth• Multilanewith1,2,or4SDAlanes• Hot-join• In-bandinterrupts• TimingControl • AsynchronousMode0 • SynchronousMode• AllCommonCommandCodes(CCCs)supported• Targetreset
• AMBAAPB(v3)applicationinterface
• Memorymappedregisters• DMA,flowcontrolfeatures• FIFOoptions • Internal2-byteping-pongbuffer • InternalFIFO(or32wordsforHDR-BTmode)
•LegacyI2Ccoexistence,includingI2Cmessaging
•StaticI2Caddresssupport
•SupportforI2Cpadswith50nsglitchfilter
ApplicationRegisters
ApplicationRegisters
In-Band Interrupt
Change Notification
SDA/SCL
HDREngine
SDR TargetEngine
CCCHandling
DynamicAddress
Assignment
Generated Interface
I3C Autonomous Target
Block Diagram
The I3C Autonomous Target is intended for simple, data acquisition types of applications where a microprocessor is not needed to process the data. Instead, data is exchanged via a simple set of register interfaces to the application and the controller autonomously manages all of the communication to an upstream I3C Controller.
Features• Highlyconfigurablecorethatallowscustomertominimize
unneeded logic
• CompliantwithMIPII3CV1.1specification
• Dynamicaddressing
• SingleDataRate(SDR)
• Errordetectiontypes(S0-S5)
• AdvancedI3Cfeatures
• Hotjoin• In-bandinterrupts• TimingControl • AsynchronousMode0 • SynchronousMode• High-speedmode(HDR-DDR)• Groupaddressing• Targetreset• AllCommonCommandCodes(CCCs)supported
• StaticI2Caddresssupport
• LegacyI2Ccoexistence,includingI2Cmessaging
• SupportforI2Cpadswith50nsglitchfilter
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CLK APB INT DMA
SDA/SCL
InterruptsDMA
& Flow ControlMemory Mapped Registers
Clock Domain Crossing Synchronization
HDREngine
SDR TargetEngine
CCCHandling
DynamicAddress
Assignment
External FIFO
I3C Advanced Target
Block Diagram
The I3C Advanced Target is a highly configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivity to any device. It can be configured in a number of different ways to allow the core to use the minimum amount oflogictoreducebotharea(cost)andpower.
Features• Highlyconfigurablecorethatallowscustomertominimize
unneeded logic
• CompliantwiththeMIPII3CV1.1specification
• Dynamicaddressing
• SingleDataRate(SDR)
• AdvancedI3Cfeatures
•Hotjoin• In-bandinterrupts• TimingControl • AsynchronousMode0 • SynchronousMode• High-speedmode(HDR-DDR)• Groupaddressing• Targetreset• AllCommonCommandCodes(CCCs)supported
•StaticI2Caddresssupport
•LegacyI2Ccoexistence,includingI2Cmessaging
•SupportforI2Cpadswith50nsglitchfilter