I2C
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![Page 1: I2C](https://reader036.fdocuments.in/reader036/viewer/2022062419/557d7a54d8b42a75548b4b7b/html5/thumbnails/1.jpg)
Mr.Tejas DaveChovatiya RaviJitendra EdleSachin Nigam
Prepared by:- Guide by:-
“I2C Bus ProtocolImplementation”
THAKUR INSTITUTE OF CAREER ADVANCEMENT
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Shorthand for an “Inter-integrated circuit” bus Developed by Philips Semiconductor for TV sets in
the 1980’s I2C devices include EEPROMs, thermal sensors,
and real-time clocks Used as a control interface to signal processing
devices that have separate data interfaces, e.g. RF tuners, video decoders and encoders, and audio processors.
I2C bus has three speeds: Slow (under 100 Kbps) Fast (400 Kbps) High-speed (3.4 Mbps) – I2C v.2.0
Limited to about 10 feet for moderate speeds
What is I2C?
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WISHBORNInterface
Prescale Register
Command Register
TransmitRegister
Status Register
ReceiverRegister
Addr000
Addr001
Addr011
Addr100
Addr101
Addr110
Data IOShift
Register
Bit & Byte Controller
ClockGenerator
SDA
SCL
Internal structure I2C Master Core
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External connection
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Register ListName Addres
sWidth Access Description
PRERlo
000 8 RW Clock Prescale Register Lo-byte
PRERhi
001 8 RW Clock Prescale Register Hi-byte
CTR Null 8 RW Control Register
TXR 101 8 W Transmit Register
RXR 110 8 R Receive Register
CR 011 8 W Command Register
SR 100 8 R Status Register
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Control register
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Transmit Register
Receive Register
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Command Register
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Status Register
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I2C Bus Configuration
2-wire serial bus – Serial data (SDA) and Serial clock (SCL)
Half-duplex, synchronous, multi-master bus No chip select or arbitration logic required Lines pulled high via resistors, pulled down
via open-drain drivers (wired-AND)
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I2C Protocol
1. Master sends start condition (S) and controls the clock signal
2. Master sends a unique 7-bit slave device address3. Master sends read/write bit (R/W) – 0 - slave receive, 1
- slave transmit4. Slave with matching 7-bit device address always sends
acknowledge bit (ACK) 5. Transmitter (slave or master) transmits 1 byte of data
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I2C Protocol (cont.)
6. Receiver issues an ACK bit for the byte received7. Repeat 5 and 6 if more bytes need to be transmitted8. Master always sends stop condition (P)
a. For write transaction (master transmitting), master issues stop condition (P) after last byte of data.b. For read transaction (master receiving), master does not acknowledge final byte, just issues stop condition (P) to tell the slave the transmission is done
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Start – high-to-low transition of the SDA line while SCL line is high
Stop – low-to-high transition of the SDA line while SCL line is high
Ack – While transmitter allows SDA to float, the receiver pulls SDA low throughout the entire next clock pulse on SCL.
Data – transition takes place while SCL is low and is valid while SCL is high
I2C Signals
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Bit Command Controller
I
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A B
I2C SignalsC D I
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Write 1 byte of data to a slave
Generate start command Write slave address+write bit Receive acknowledge from slave Write data Receive acknowledge from slave Generate stop command
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Read 1 byte of data to a slave
Generate start command Write slave address+write bit Receive acknowledge from slave Write data Receive acknowledge from slave Generate stop command
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Receive acknowledge from
slave Generate repeated start signal Write slave address + read bit Receive acknowledge from
slave Read byte from slave Write no acknowledge to
slave,indicationg end of transfer
Generate stop signal
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I2C Features “Clock stretching” – when the receiver needs more
time to process a bit, it can pull SCL low to keep it from going high a bit longer. This technique is called clock stretching . On SDL low, the transmitter can send its next data value, but this value will not be interpreted as a valid data symbol by the receiver until after the slave is ready to release SCL to go high.
“General call” broadcast – addresses every device on the bus
10-bit extended addressing for new designs. 7-bit addresses all exhausted
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Start countinglow period
waitstate
Start countinghigh period
SCL1
SCL2
SCL
Master1 SCL
Master2 SCL
wired-AND SCL
Clock Synchronization
If two or more masters simultaneously try to control the bus, a clock synchronization procedure determines the bus clock.
Because of the wired-AND connection of the I2C signals a high to low transition affects all devices connected to the bus.
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Master :- Initiate a message Slave :- Response to message
Multiple Devices
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Master detect arbitration loss
Multi-Master Support
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Reduce IC Pins, Cost and Area Reduce PCB Size And Cost
Advantages Of I2C
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WISHBORNInterface
Prescale Register
Command Register
TransmitRegister
Status Register
ReceiverRegister
Addr000
Addr001
Addr011
Addr100
Addr101
Addr110
Data IOShift
Register
Bit & Byte Controller
ClockGenerator
SDA
SCL
Internal structure I2C Master Core
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References
I2C: http://www-us2.semiconductors.p
hilips.com/acrobat/various/
I2C_BUS_SPECIFICATION_1995.pdf
http://www.esacademy.com/faq/i2c/index.htm
http://www.embedded.com/story/OEG20020528S0057
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