I V V be be I V ln I S Answers to question 1: O R V R I S ...Figure 1. Answer to Question 2.b;...
Transcript of I V V be be I V ln I S Answers to question 1: O R V R I S ...Figure 1. Answer to Question 2.b;...
EE3-01 Analogue Integrated Circuits and Systems 1
Answers to question 1: 1.a i) Bookwork Student must explain they are self-biased current references and explain the need
and role of the startup circuit based on equations. [4 points] Equation for output current:
If we self bias and force IIN/IO = 1 with top current mirror, then ln(1) = 0
Require IIN/IO > 1 In Figure 1.1, IIN/IO = n=2 So, assuming matched devices
[4 points] Must elaborate that the circuit in Fig. 1.1 has a better temperature coefficient that that of fig 1.2 and show equations for Temperature coefficient.
Fig 1.1 is a Improved TCF using VT Referenced Current Source/Sink
[1 point] Fig 1.2 is a Vbe Referenced Sink/Source with a temperature coefficient:
[1 point] [Total 6 points] b) For Fig 1.1:
[3 points] For Fig 1.2
( )
=
=−
=O
S
S
INTO
INT
bebeO
I
I
I
I
R
V
R
I
IV
R
VVI 2
1
21 ln
ln
2lnR
VI T
O =
TCF =1
VT
æ
èç
ö
ø÷dVTdT
-1
R
æ
èç
ö
ø÷dR
dT
TCF =1
Vbe1
æ
èç
ö
ø÷dVbe1dT
-1
R
æ
èç
ö
ø÷dR
dT
TCF =1
T-
1
R
æ
èç
ö
ø÷dR
dT
=1
300-1500x10-6æ
èç
ö
ø÷ =1833ppm/ºC
EE3-01 Analogue Integrated Circuits and Systems 2
Assume VBE=0.7
[3 points] [Total 6 points] c. ) Bandgap voltage reference circuit which has almost zero temperature coefficient,
used mainly as stable voltage reference in ICs.
I2 Q
3
Q1
Q2
V0
+ V
IB
R1
R2
R3
I1
[4 points for figure] For BG reference,
1;3221 +=− RIVV BEBE
=−2
121 ln
II
VVV TBEBE
temproomassumeI
IVV
II
VR
RVV
sTBETBEo
=
+= 33
2
1
3
23 ln;ln
=
=
2
1
3
23 ln0I
I
R
R
T
V
TV
TV
For TBEo
19
23
106.1
1038.15.2
−
−
=
−=
T
Vand
CmV
TV
Since TBE
283.129ln2
1
3
2 ==
oV
I
I
R
R
[4 points for derivation]
[Total 8 points]
TCF =1
Vbe1
æ
èç
ö
ø÷dVbe1dT
-1
R
æ
èç
ö
ø÷dR
dT
TCF =1
0.7
æ
èç
ö
ø÷ -2.5mV( ) - 1500x10-6( )
= -5100ppm/ºC
EE3-01 Analogue Integrated Circuits and Systems 3
Answer to question 2: a)
In the folded cascode we are unstacking the conventional cascode and spreading it out. The AC current path is folded and this allow a reduction in power supply. The conventional cascode requires a 2-stage architecture and since the impedance at (x) is high requires internal compensation. The folded cascode can be used as a single stage architecture, node x is low impedance so the only high impedance node will be at the output.
Gain of the folded cascode Av=gm1/Go. [2]
[4]
[Total 6 points]
b)
EE3-01 Analogue Integrated Circuits and Systems 4
𝐺𝐵𝑃 =
𝑔𝑚
2𝜋𝐶𝐶=1.76MHz
[8] In a 2-stage opamp the load contributes to the 2nd pole hence reducing load increases stability. With a single-stage, the load forms the dominant pole hence reducing the load increases bandwidth.
[2] [Total 10 points]
c.
2. Useanulling resistor RZ
Effectively using aresistor totry andbootstrapCC,sothat at high
frequencies it breaksthefeed forward path.This is achieved bymaking
RZ=1/gm6 sothatthevoltageacrosstheresistorwillcancelthesignalvoltage
onthelefthandplateofthecapacitor.
Elimination of“TheZero”(2)
40
Fig.12
EE3-01 Analogue Integrated Circuits and Systems 5
[Total 4 points]
Answers to question 3: a) Explain sigma delta operation (bookwork).
[5]
[5]
b)(i) Explain how the conversion works (bookwork)
[3] Draw a cascade of blocks whereby N=8
EE3-01 Analogue Integrated Circuits and Systems 6
[4]
c) KT/C noise limits the resolution of a sampled data converter.
[3]
Answers to question 4:
a) Operating conditions:
[4]
The Bulk is not connected to the source due to void VBS from becoming a forward biased diode. [2]
[Total 6 points] b)
EE3-01 Analogue Integrated Circuits and Systems 7
[3]
[3]
[Total 6 points]
Since
Tuning Range determined byVCwhich is independant ofthesignal unlike thesingle
MOSFET.Notethevalidity oftheabove only forVDS <(VC – VT),hence largeVC,
larger VDS andsowider range oflinearity.Results inabout twice linearrange of
previous circuit.
I = I1 + I2
Then
[ ]TC
ABDS
VVL
KWR
I
V
-÷ø
öçè
æ==
2
1LINEAR
EE3-01 Analogue Integrated Circuits and Systems 8
[5]
[3] [Total 8 points]
Answer to question 5
a) Regulated Cascode:
DoubleDifferential MOSActiveResistor (2)CircuitAnalysis
Principal Equations
( )( ) ( ) úû
ùêë
é-----=
2
11112
12 VVVVVVVI TCD b
( )( ) ( ) úû
ùêë
é-----=
2
11222
12 VVVVVVVI TCD b
( )( ) ( ) úû
ùêë
é-----=
2
22232
12 VVVVVVVI TCD b
( )( ) ( ) úû
ùêë
é-----=
2
212142
12 VVVVVVVI TCD b
Byexpanding each expression out,it canbeshown that
R(transresistance)≈
V1 -V2
I 1 - I2=
1
2b VC1 -VC2( )
Hence R has avery widetuning
range andexcellent linearity,
independent ofVT
Note:We nowmustensureV1,V2 <(VC1 – VT),(VC2 – VT)
i.e.VDS <VGS - VT
Fullydifferentialtuneableintegratorswithtimeconstant:
Thusintegratortime-constantcanbetunedbyVC1 orVC2.Fullydifferentialhas
advantagesofcancellingoffsets,andcommon-modevoltagessuchasnoisein
additiontocancellingnon-linearityasdemonstratedintheresistorrealisation.
t =C
2b VC1 -VC2( )
EE3-01 Analogue Integrated Circuits and Systems 9
+ V
IB
I0
Q2
Q1
Q3
X
VC
[4] A regulated cascode current sink/source. The drain-source voltage of Q1 is regulated by the feedback amplifier Q2. It has a very high output impedance as a result equivalent to that of a double cascode. [2]
[Total 6 points] b. From notes:
Annotation of VGS’ of each transistor:
EE3-01 Analogue Integrated Circuits and Systems 10
[Total 6 points]
c)The two and four transistor potential dividers depicted in figure below.
0;5;5;1;/8;/17 22 =−=+===== OutSSDDTpTnpn VVVVVVVVVAKVAK
For the two transistor potential divider
( ) ( )22
21
21
Tpddout
Qp
Qp
pTnssout
Qn
Qn
nQnQp VVVL
WKVVV
L
WKII −−=−−==
156.064
10;073.0
136
10====
Qp
Qp
Qn
Qn
L
W
L
W
For the four transistor potential divider
( ) ( )
( ) ( )2
2
2
22
1
1
1
2
2
2
22
1
1
1
2211
21
21
21
21
TpGSp
Qp
Qp
pTpGSp
Qp
Qp
p
TnGSn
Qn
Qn
nTnGSn
Qn
Qn
nQnQpQnQp
VVL
WKVV
L
WK
VVL
WKVV
L
WKIIII
−=−=
−=−====
VVV
VV SSOutGSnGSn 5.2
221 =
−==
VVV
VV DDOut
GSpGSp 5.22
21 =−
==
523.0125.19
10
2
2
1
1 ===n
n
n
n
L
W
L
W
110
10
2
2
1
1===
p
p
p
p
L
W
L
W
The aspect ratio of the transistors in the four-transistor potential divider is much less than the two-transistor circuit, therefore, its consuming area will be less. For example, assuming common width of 10 units, for the two transistor configuration the active area becomes 10*(64+136)=2000 units while for the four transistor it becomes 10*2*(10+19.125)=582.5 units.
EE3-01 Analogue Integrated Circuits and Systems 11
Figure 1. Answer to Question 2.b; potential Divider circuits
Drawing the potential divider with two transistor [2] Drawing the potential divider with four transistor [2]
Calculating the required transistor sizes for each potential divider and comparing their area [4]
[Total 8 points]
Answer to question 6 a)Derivation from notes
EE3-01 Analogue Integrated Circuits and Systems 12
[10]
b. (i) 3rd-order Chebyshev low pass switched-capacitor ladder filter.
[5]
General transformation rules for ladder prototypes:
Inductor:
Capacitor:
Resistor Rs=dummy scalar. The circuit is equivalent to an RLC prototype
fcL2
Rs=CL2
CuCc3
Cu= fcRsC3
EE3-01 Analogue Integrated Circuits and Systems 13
[5]
ii. For switched capacitor equivalent: Cc1=Cc3=5.08 pF CL2=3.49 pF. Cu=1pF Assume scaling Rs=Ri=Ro=1Ω Therefore L2= CL2/fc= 3.49/100x103=3.49x10-5 H
Normalised 1rad/sec we multiply by 2πf0
L2=3.49 x10-5 x 2π x 5 KHz =1.096 H C1=C3=Cc3/fc = 5.08/100x103 =5.08x10-5 f Normalised value C1=C3=1.596