I Ointerface in mp

Advanced Microprocessor 1

I/O Interface

Programmable Keyboard/Display Interface - 8279

• A programmable keyboard and display interfacing chip.

• Scans and encodes up to a 64-key keyboard. And Controls up to a 16-digit numerical display. • Keyboard section has a built-in FIFO 8 character buffer.

• The display is controlled from an internal 16x8 RAM that stores the coded display information.

• 8279 has 8 control words to be considered before It is programmed


I/O Interface

Basic Description of the 8279

• A0: Selects data (0) or control/status (1) for reads and writes between micro and 8279.

Output that blanks the displays.

• CLK: Used internally for timing. Max is 3 MHz.

• CN/ST: Control/strobe, connected to the control key on the keyboard.

• Chip select that enables programming,

reading the keyboard, etc.

DB7-DB0: Consists of bi-directional pins that

connect to data bus on micro.


I/O Interface

• IRQ: Interrupt request, becomes 1 when a key is pressed, data is available.

• OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant nibble of display.

• : Connects to micro's IORC or RD signal, reads data/status registers.

• RESET: Connects to system RESET.

• RL7-RL0: Return lines are inputs used to sense key depression in the keyboard matrix.

•Shift: Shift connects to Shift key on keyboard.

• SL3-SL0: Scan line outputs scan both the keyboard and displays.


I/O Interface

Interfacing the 8279 to the Microprocessor

• The 8279 is decoded to function at 8-bit I/O address 10H & 11H

10H – data port

11H – control port

• PAL16l8 is used to decode the I/O address for 8279

• A0 selects either the data or control port

• IRQ, since it is a interrupt pin, this signal is not connected to microprocessor.


I/O Interface

8279 interfaced to 8088 microprocessor :


I/O Interface

Keyboard Interface:

• The keyboard matrix can be any size from 2x2 to 8x8.

• The I/O port number decoded is the same, 10H & 11H

• The 74LS138 drives active low column strobe signals for the keyboard on one line at a time .

• Selection Pins SL2-SL0 sequentially scan each column of the keyboard

• The internal circuitry of 8279 scans RL pins, searches for key closure.

•RL pins incorporate internal pull-ups, no need for external resistor pull-ups.


I/O Interface

Programming the Keyboard Interface :

• before any keystroke is detected, the 8279 must be programmed

• the first 3 bits of the number sent to the control port (11H) select one of the 8 different control words


I/O Interface

Programming the Keyboard Interface :


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First three bits given below select one of 8 control registers (opcode).

Control Word Description:

000DDMMM

Mode set: Opcode 000.

DD sets displays mode.

MMM sets keyboard mode.

DD field selects either:

• 8- or 16-digit display

• Whether new data are entered to the rightmost or leftmost display position.


I/O Interface


MMM field:

• Encoded Mode: SL outputs are active-high, follow binary bit pattern 0-7 or 0-15 depending on 8 or 16 digit display.

• Decoded Mode: SL outputs are active-low (only one of the four outputs will be low at any time).Pattern output: 1110, 1101, 1011, 0111.

MMM


I/O Interface


• Strobe : An active high pulse on the CN/ST input pin strobes data from the RL pins into an internal FIFO for reading by micro later.

• 2-key lockout/N-key rollover: Prevents 2 keys from being recognized if pressed simultaneously/Accepts all keys pressed from 1st to last.

001PPPPP

• The clock command word programs the internal clock driver.

• The code PPPPP, is a prescalar that divides the clock input pin (CLK) to achieve the desired operating frequency, e.g. 100KHz requires 010102 for a 1 MHz CLK input.

(1MHz) / (100 X 103 ) = 10


I/O Interface


010Z0AAA

The read FIFO control word selects the address (AAA) of a keystroke from the FIFO buffer (000 to 111).

Z selects auto-increment for the address.

011ZAAAA

The display read control word selects the read address of one of the display RAM positions for reading through the data port.

Z selects auto-increment for the address.

100ZAAAA

write display Selects address – to write address of one of the

Display. Z selects auto-increment so subsequent writes go to subsequent display positions.


I/O Interface

Control Word Description:1010WWBB

The display write inhibit control word inhibits writing to either the leftmost 4 bits of the display (left W) or rightmost 4 bits (right W).

BB works similarly except that they blank (turn off) half of the output pins.

1100CCFA

The clear control word clears the display, FIFO or both

Bit F clears FIFO and the display RAM status, and sets address pointer to 000.

If CC are 00 or 01, all display RAM locations become 00000000.

If CC is 10, --> 00100000, if CC is 11, --> 11111111.1110E000

End of Interrupt control word is issued to clear IRQ pin to zero in sensor matrix mode


I/O Interface

Clock must be programmed first. If 3.0 MHz drives CLK input, PPPPP is programmed to 30 or 111102.

• Keyboard type is programmed next.

The previous example illustrates an encoded keyboard, external decoder used to drive matrix.

• Program the operation of the FIFO.

• Once programmed never reprogrammed done, until a procedure is needed to read prior keyboard codes .

• To determine if a character has been typed, the FIFO status register is checked.

When the control port is addressed by the IN instruction, the contents of the FIFO status word is copied into register AL:


I/O Interface

FIFO status register

•Code given in text for reading keyboard.

•Data returned from 8279 contains raw data that need to be translated to ASCII:


I/O Interface

• Row and column number are given the rightmost 6 bits (scan/return).

•This can be converted to ASCII using the XLAT instruction with an ASCII code lookup table.

•The CT and SH indicate whether the control or shift pins were pressed.

•The Strobed Keyboard code is just the state of the RLx bits at the time a 1 was 'strobed‘ on the strobe input pin.


I/O Interface

Six Digit Display Interface of 8279

Display Interface

• The Interface uses a PAL16L8 to decode the 8279 at I/O Ports20H for Data21H for Control/Status

• The Segment data are supplied to the displays thru the OUTA & OUTB of 8279

• Bits are buffered by a segment driver (2003A) to drive the segment inputs to the display


I/O Interface

Six Digit Display Interface of 8279


I/O Interface

Programmable Interval Timer: 8254

•Three independent 16-bit programmable counters (timers).

Each capable in counting in binary or BCD with a maximum frequency of 10MHz.

•Used for controlling real-time events such as real-time clock, events counter, and motor speed and direction control.

The timer usually decoded at port address 40H-43H and has following functions:

- Generates a basic timer interrupt that occurs at approximately 18.2Hz. Interrupts the micro at interrupt vector 8 for a clock tick.

-Causes DRAM memory system to be refreshed.

- Provides a timing source to the internal speaker and other devices.


I/O Interface

8254 Functional Description


I/O Interface


•Timer 0 is programmed to generate an 18.2Hz signal that interrupt the microprocessor at interrupt vector 8 for a clock tick

• Timer 1 is programmed for 15µs, used in PC’s to request a DMA action used to refresh DRAM

• Timer 2 is programmed to generate tone on the PC’s speaker

• D0 to D7, read, write, Chip select & Address pins A1 and A0are connected to Microprocessor • the address inputs used to select any of the internal register for programming, reading, or writing to a counter

Tick is used for time program or events


I/O Interface


A1, A0:The address inputs select one of the four internal registers with the 8254 as follows:

CLK: The clock input is the timing source for each of the internal counters. It is often connected to the PCLK signal from the bus controller.


I/O Interface


CS: Chip Select enables the 8254 for programming, and reading and writing.

G: The gate input controls the operation of the counter in some modes.

OUT: A counter output is where the wave-form generated by the timer is available.

: Read/Write causes data to be read/written from the 8254 and often connects to the


I/O Interface

Each counter is individually programmed by writing a control word, followed by the initial count.

The control word allows the programmer to select the counter, model of operation, binary or BCD count and type of operation (read/write).


I/O Interface

Programming the 8254

Each counter may be programmed with a count of 1 to FFFFH.

Minimum count is 1 all modes except 2 and 3 with minimum count of 2.

Each counter has a program control word used to select the way the counter operates.

If two bytes are programmed, then the first byte (LSB) stops the count, and the second byte (MSB) starts the counter with the new count.

There are 6 modes of operation for each counter:

Mode0, Mode1, Mode2, MOde3, Mode4, Mode5


I/O Interface


Modes of operation Mode 0: An events counter enabled with G.

The output becomes a logic 0 when the control word is written and remains there until N plus the number of programmed counts.

Mode 1: One-shot mode.

The G input triggers the counter to output a 0 pulse for count clocks.Counter reloaded if G is pulsed again.


I/O Interface


Modes of operationMode 2: Counter generates a series of pulses 1 clock pulse wide.

The separation between pulses is determined by the count.

The cycle is repeated until reprogrammed or G pin set to 0.

Mode 3: Generates a continuous square-wave with G set to 1.

If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer.


I/O Interface


Modes of operation

Mode 4: Software triggered one-shot (G must be 1).

Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

Trigger with count of 5


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Read Operations

There are three possible methods for reading the counters:

• a simple read operation

• the Counter Latch Command

• the Read-Back Command

Simple read operation :

• The Counter which is selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic.

• Otherwise, the count may be in the process of changing when it is read, giving an undefined result.


I/O Interface

Counter Latch Command:

• SC0, SC1 bits select one of the three Counters• two other bits, D5 and D4, distinguish this command from a Control Word

• If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued.


I/O Interface

Read-back control command:

• The read-back control, word is used When it is necessary for the contents of more than one counter to be read at a same time.

Count : logic 0, select one of the Counter to be latchedStatus : logic 0, Status must be latched to be read status of a counter is accessed by a read fromthat counter


I/O Interface

Status register:• shows the state of the output pin• check the counter is in NULL state (0) or not• how the the counter is programmed


I/O Interface

16550 Programmable Communications Interface:

• 16550 , A universal asynchronous receiver/transmitter (UART).

• it capable of operating speed: 0 to 1.5M Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity).

•It includes:

- A programmable Baud rate generator.

- Separate FIFO buffers for input and and output data (16 bytes each).

Asynchronous serial data:

Asynchronous serial data are transmitted and received without a clock or timing signal.

Two 10-bit frames of asynchronous serial data, start bit, 7 data bit, parity & stop bit.


I/O Interface

16550 functional description:

• this device is available as 40-pin DIP( dual in-line package) or as a 44-pin PLCC ( plastic lead less chip)

• two separate sections are responsible for data communications - Receiver & Transmitter

• can function : - simplex: transmit only,

eg:FM radio station -half-duplex: transmit and receive but not simultaneously eg: CB( citizen band) station - full-duplex: transmit and receive simultaneously

eg : telephone


I/O Interface

•main feature, has internal receiver & transmitter FIFO memories, each 16 Bytes deep.

• the UART, requires attention only from the microprocessor after receiving 16 bytes of data

• it holds 16 bytes before the microprocessor must wait for the ‘ transmitter.

• the FIFO makes UART ideal when interfacing to high speed systems


I/O Interface

The 16550 can control a modem through

and

the modem is called the data setthe 16550 is called the data terminal.

16550 Pin function:

A0, A1 and A2: Select an internal register for programming and data transfer.

.


I/O Interface

: Address strobe used to latch address and chip select. Not needed on Intel systems - connected to ground.

: Clock signal from Baud rate generator in transmitter.

CS0, CS1, : Chip selects must all be active enable the 16550 UART

: Clear to send -- indicates that the modem or data set is ready to exchange information. (Used in half-duplex to turn the line around).

D7-D0: The data bus pins are connected to the microprocessor data bus.

: The data carrier detect -- used by the modem to signal the 16550 that a carrier is present.

DDIS: Disable driver output -- set to 0 to indicate that the microprocessor is reading data from the UART. Used to change direction of data flow through a buffer.


I/O Interface

: Data set ready is an input to 16550, indicates that the modem (data set) is ready to operate.

: Data terminal ready is an output, indicates that the data terminal (16550) is ready to function.

INTR: Interrupt request is an output to the microprocessor, used to request an interrupt. Receiver error, Data received, Transmit buffer empty

MR: Master reset , connect to system RESET : User defined output pins for modem or other device.

RCLK: Receiver clock, clock input to the receiver section of the UART. Always 16X the desired receiver Baud rate.


I/O Interface : Ring indicator input , set to 0 by modem to indicate telephone is ringing.

RD, : Read inputs (either can be used), cause data to be read from the register given by the address inputs

:Request-to-send, signal to modem, indicating UART wishes to send data.

SIN, SOUT: Serial data pins, in and out. : Receiver ready, used to transfer received data via DMA techniques.

:Transmitter ready, used to transfer transmitter data via DMA WR, :Write (either can be used) , connects to microprocessor write signal to transfer commands and data to 16550.

XIN, XOUT: Main clock connections -- a crystal oscillator can be used.


I/O Interface

Programming 16550:• the programming is a two part process

- initialization dialog- operational dialog

Initializing 16550:

•Initialization dialog, occurs after a hardware or software reset, Consists of two parts

- line control register - baud rate generator

must be programmed

•Line control register selects: number of stop & parity bit( even or odd)

•Baud rate generator: programmed with a divisor that determine the baud rate of the transmission section


I/O Interface

Line control register:• programmed by outputting information to I/O ports 011• Right most 2 bits, selects the number of transmitted data bits (5,6,7or 8)

• Stop bits: S = 1, 1.5 stop bits used for 5 data bits, 2 used for 6, 7 or 8.• next 3 bits: ST(stick), P and PE used to send even or odd parity, to send no parity or to send a 1 or a 0 in the parity bit position for all data.


I/O Interface

•SB = 1 , used to send a break to be transmitted on SOUT. A break is at least two frame of logic 0 data.software is responsible for timing the transmission,

to end the break SB return to logic 0

•DL = 1, enables programming of the baud rate divisor.


I/O Interface

Programming the baud rate: Baud rate generator is programmed with a divisor that sets baud rate of transmitter.

• Baud rate generator is programmed at 000 and 001 ( A2,A!,A0). Port 000 used to hold least significant part, 001 most significant part

Value used depends on external clock/crystal frequency.For 18.432MHz crystal :- 10,473 divisor value 110 band rate, - 30 divisor value gives 38,400 baud

Note : the actual number programmed into baud rate generator causes, to produce a clock that is 16 times the desired baud rate eg : if 240 is programmed into baud rate divisor,

Baud rate = 18.432 MHz/(16X240) = 4800 baud.


I/O Interface

FIFO control register for 16550:• register enable the transmitter & receiver and clears the transmitter & receiver FIFO.• provides control for 16550 interrupts

Sending serial data : line status register, contains the information about

- error conditions - state of the transmitter & receiver

• the register is tested before a byte is transmitted or can be received


I/O Interface

Suppose a program wants to send data out SOUT.•It needs to pool the TH bit to determine if transmitter is ready to receive data.

Receiving serial data: •To receive information, the DR bit is tested.


I/O Interface

UART error: Operation:It is also a good idea to check for errors.

•Parity error: Received data has wrong error, transmission bit flip due to noise.

•Framing error: Start and stop bits not in their proper places. This usually results if the receiver is receiving data at the incorrect baud rate.

•Overrun error: Data has overrun the internal receiver FIFO buffer. Software is failing to read the data from UART before the FIFO is full.

•( BI )Break indicator bit: Software should check for this as well, i.e. two consecutive frames of 0s.


I/O Interface

Examples, 16550 interfaced to the 8088 at ports 00F0H – 00F7H


I/O Interface

•Here port F3H accesses the line control register

•F0H & F1H access the baud rate divisor register

• after the line control register & baud rate divisor are programmed , still it is not ready to function

• program the FIFO control register, at port F2H

I Ointerface in mp

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