I. CIRCUIT BASICS

Electrical quantities

Current: dt

dqI [Units: C/s = Amps (A)] Voltage:

dq

dwV [Units: J/C = Volts (V)]

Power: VIPdt

dq

dq

dw

dt

dw

[Units: J/s = Watts (W)]

avg power: T

TdttVtIP

0

1 )()(

P = IV > 0: power delivered

P = IV < 0: power extracted

Primitive circuit elements

Voltage Source Current Source

Resistor – follows Ohm’s Law: V IR (note polarity)

R = resistance [Units: V/A = Ohms ( )]

G = 1/R = conductance [Units: Siemens (S)]

Resistor power dissipation: R

RIIVP V 22

n

k

keq RR

1

Circuit definitions

Node – point where 2 or more circuit elements are connected

Series elements – same current flows through all elements

Parallel elements – same voltage across all elements

II. CIRCUIT ANALYSIS BASICS

KCL (Kirchhoff’s Current Law)

Sum of all currents entering a node = 0

Sum of all currents leaving a node = 0

(currents in) = (currents out)

KVL (Kirchhoff’s Voltage Law)

Sum of voltage drops around a loop = 0

Sum of voltage rises around a loop = 0

(voltage drops) = (voltage rises)

Series resistors: • Parallel resistors: n

k keq RR1

11

2R1RReq 21

2121 ||

RR

RRRRReq

321

1111

RRRReq

Voltage divider • Current divider

SV

RR

RV

21

22

SV

RRR

RV

321

33

SI

RR

RI

21

12

SI

RRR

RI

321

33 111

1

Source combinations (series voltage sources and parallel current sources)

III. CIRCUIT ANALYSIS METHODS

Nodal Analysis – finds unknown node voltages in a circuit; once all node voltages are known,

currents can be found through IV relationships of circuit elements (e.g., Ohm’s Law)

1. Choose a reference node (“ground”)

2. Define unknown voltages (those not fixed by voltage sources)

3. Write KCL at each unknown node, expressing current in terms of node voltages

- use IV relationships of the circuit elements (e.g., I=V/R for resistors)

4. Solve the set of independent equations (N eqn’s for N unknown node voltages)

Supernode – for a floating voltage source (where both terminals are unknown voltages), define

a supernode around the source, write KCL at supernode, and use the voltage source equation

xyF

yx

VVV

R

V

RV

II21

21

Superposition – In any linear circuit containing multiple independent sources, any I or V in the

circuit can be calculated as the sum of the individual contributions of each source acting alone

o Linear circuit – circuit with only independent sources and linear elements (linear RLC,

linear dependent sources). Linear elements have linear IV characteristics.

1. Leave one source on and turn off all other sources

replace voltage source with short circuit (V=0)

replace current source with open circuit (I=0)

2. Find the contribution from the “on” source

3. Repeat for each independent source.

4. Sum the individual contributions from each source to obtain the final result

Note: Superposition doesn’t work for power, since power is nonlinear (P=I2R=V

2/R)

Thevenin/Norton Equivalent Circuit Models – Any linear 2-terminal network of independent

sources and linear resistors can be replaced by an equivalent circuit consisting of 1 independent

voltage source in series with 1 resistor (Thevenin) or 1 independent current source in parallel

with 1 resistor (Norton). The circuit models have the same IV characteristics.

Three variables: Vth=Voc, Rth=RN, IN=Isc.

Thevenin/Norton relationship: Vth=INRth only 2 of the 3 variables are required

Vth = Voc: open-circuit voltage – Leave the port open (IL=0) and solve for Voc.

IN = Isc: short-circuit current – Short the port (VL=0) and solve for IN.

Rthc: Thevenin/Norton resistance – Turn off all independent sources (leave the dependent

sources alone). If there are no dependent sources, simplify the resistive network using

series and parallel reductions to find the equivalent resistance. If dependent sources are

present, attach Itest or Vtest and use KCL/KVL to find Rth=Vtest/Itest.

test

testth

I

VR

note the direction of Itest

and the polarity of Vtest

Source Transformations – conversion between Thevenin and Norton equivalent circuits

Maximum Power Transfer Theorem

power transferred to load resistor RL

is maximized when RL=Rth

Load-line Analysis – graphical method solving circuits with 1 nonlinear circuit element

graph the IV curves for the nonlinear circuit element and the Thevenin/Norton equivalent of

the rest of the circuit on the same axes; the operating point is where the two curves intersect

IV. CAPACITORS AND INDUCTORS

Capacitor – passive circuit element that stores electric energy

Capacitance: C = Q/V [Units: Coulombs/Volt = Farads (F)]

IV relationship: dt

dvc

cCi

Energy stored: Ec = ½CV2

voltage across capacitor vc cannot change instantaneously: vc(0-)=vc(0

+)

note polarity!

in steady-state, capacitor is an open circuit (dvc/dt=0 ic=0)

low freq: open circuit; high freq: short-circuit

Parallel capacitors: • Series capacitors: n

k

keq CC

1

n

k keq CC1

11

Capacitive voltage divider

SV

CC

CV

21

12

SV

CCC

CV

321

33

111

1

Inductor – passive circuit element that stores magnetic energy

Inductance: L = /I [Units: Webers/Amps = Henrys (H)]

IV relationship: dt

diL

LLv

Energy stored: EL = ½LI2

current through inductor iL cannot change instantaneously: iL(0-)=iL(0

+)

note polarity!

in steady-state, inductor is a short circuit (diL/dt=0 vL=0)

low freq: short circuit; high freq: open-circuit

Series inductors: • Parallel inductors: n

k

keq LL

1

n

k keq LL1

11

Capacitor and Inductor Summary :

Capacitor Inductor

IV relationship dt

dvCi

dt

diLv

Energy storage Ec = ½CV2 EL = ½LI

2

Continuity Voltage: vc(0-)=vc(0

+) Current: iL(0

-)=iL(0

+)

Steady-state Open circuit (I=0) Short circuit (V=0)

Series n

k keq CC1

11 n

k

keq LL

1

Parallel n

k

keq CC

1

n

k keq LL1

11

V

. FIRST-ORDER CIRCUITS

RC circuit – contains only sources, resistors, and 1 capacitor

RL circuit – contains only sources, resistors, and 1 inductor

voltages and currents are described by 1st-order ODE (ordinary differential equation)

RC Circuits RL Circuits

)()()(

tvtvdt

tdvRC ic

c Rtitvdt

tdvRC ic

c )()()(

R

tvti

dt

tdL i

R

iL

L )()(

)( )()()(

titidt

tdi

R

LiL

L

Time constant: = RC Time constant: = L/R

Tim

erest X(t), using KCL/KVL and IV

Ke-t/

as

e-domain Analysis for 1st-order Circuits

1. Write the ODE in terms of the variable of int

relationships for R, L, C.

2. Find the homogeneous solution Xh(t) by setting input to 0 and substituting Xh(t)=

the solution to find the time constant ( =RC for RC circuit and =L/R for RL circuit) .

(Note: The value of K cannot be found until the complete solution is found in Step 4.)

3. Find the particular solution Xp(t). Remember the output follows the form of the input:

input function constant exponential sinusoid

particular solution A- t - t

Acos( (wt) A e + B·te wt)+Bsin

Gues ut lve d nts. s the form of the sol ion soand the ODE to fin any arbitrary consta(Note: For sinusoidal inputs, the particular solution can be found more easily using complex imped

Combine the homogeneous and particular solutions to get the complete solution: Xance.)

4. (t) =

Xh(t)+Xp(t). Use the initial conditions to find the missing variables (i.e., the K in Xh(t)).

Example: Find vc(t>0) for RC circuit w/ vi(t)=VDD, vc(0-)=0V.

1) )()()(

tvtvtdv

RC icc 2) vc,h(t) = Ke

-t/ 0RC

dt

ttKee

K = RC

Since vi(t) is a constant, s g nto the ODE, A=VDD=v-t/

D- +

c n .

No

3) gues vc,p(t)=A. Plug ing i c,p(t).

4) vc(t) = vc,h(t) + vc,p(t) = Ke + V D. vc(0 )=vc(0 ) by capacitor voltage onti uity

-t/

vc(0)=0=K+VDD K=-VDD. So, vc(t) = VDD-VDDe .

te: Xh(t) represents the transient response of the circuit and should decay to 0 as time

sponse e to decay by 63%

passes. Xp(t) represents the steady-state response of the circuit which persists after the

transients have died away and which takes the form of the input.

Time constant – amount of time for the transient exponential re-t/

-1(e = 0.63). In 5 time constants, the response decays by 99%. Faster circuits have smaller .

General 1st-order Transient Response for Voltage/Current Step

)(

)()(o

tt

f eXtXXtX (X is any voltage or curfo rent in the circuit)

Xf = final value, to = time voltage/c n

(1) +

ty (x(0 )=x(0 )) and steady-state

rule circuit, =L/R for LR circuit). R

is the Thevenin equivalent resistance “seen” by the cap/ind.

urre t step occurred - +

Find initial value X(to ) and final value Xf. Use continui

s (open/short) for cap/ind. (2) Calculate ( =RC for RC

VI. SE

inary differential equation)

E: Error! Bookmark not

COND-ORDER CIRCUITS

RLC circuit – contains only sources, resistors, 1 capacitor, and 1 inductor

voltages and currents are described by 2nd

-order ODE (ord

General 2nd

-order OD

defined. )()(22

2tftxo

)()(2 tdxtxd

dtdt

= /

= damping coefficient, o = undamped natural freq (AKA resonant freq)

o = damping ratio, f(t) = forcing function (related to the input)

Series RLC Circuit Parallel RLC Circuit

dt

dv

Lti

LCdt

tdi

L

R

dt

tid i1)(

1)()(

2

2 t)(

dt

tdi

Ctv

LCdt

tdv

RCdt

tvd i )(1)(

1)(1)(

2

2

Time-domain Analysis for 2st-order Circuits

1. Write the ODE in terms of the va X(t), using KCL/KVL and IV

hips for R, L, C.

g the input to 0 and substituting X(t)=Kest into

n are

riable of interest

relations

2. Obtain the characteristic equation by settin

the ODE: s2+2 s+ o

2=0. Find and o. The roots of the characteristic equatio

22s ; the f2,1 o o

3. Find the homogeneous solution Xh(t) depending on :

> o, > 1

orm of the solution depends on the damping ratio = / .

overdamped: tth

oo eKeKtX)(

2)(

1

2222

)(

critically damped: = o, = 1 h eKtX 1)( tt teK2

underdamped: < o, < 1 )sin()cos()( 21 teKteKtX nt

nt

h

22on = damped natural frequency

(Note: The value of 1 d K2 cannot be f

particular solution X (t). Reme

K an ound until the complete solution is found.)

4. Find the p mber the output follows the form of the input:

input function constant exponential Sinusoid

particular solution A Ae- t

+ B·te- t

Acos(wt)+Bsin(wt)

Guess the form of the solution and solve the ODE to find any arbitrary constants. (Note: F s, the olut more ea mplex impedance.)

5. Com us an rticul ge n: X(t) =

Xh(t)).

or sinusoidal input particular s ion can be found sily using co

bine the homogeneo d pa ar solutions to t the complete solutio

Xh(t)+Xp(t). Use the initial conditions to find the missing variables (i.e., K1, K2 in

LCo

1

L

R

2

1

LC

RC

o1

2

1

V

II. SINUSOIDAL STEADY-STATE ANALYSIS

Any steady-state (SS) voltage or current in a linear time-invariant (LTI) circuit with a sinusoidal input source is

sinusoidal with the same frequency. Only the magnitude and phase (relative to the source) may be different.

Phasors – vectors (i.e., complex numbers) that represent sinusoids. Since all V,I in the circuit

are sinusoids with the same frequency, only magnitude & phase are needed to describe any V,I.

sinusoids: v(t) = Vcos( t+ ) = Re[Vej( t+ )

] = Re[Vej

et] phasor: Ve

j = V

v(t) = Vsin( t+ ) = Vcos( t+ - /2) phasor: V ( - /2)

For convenience, define phasors in terms of cosine (i.e., the real part of a complex exponential)

, jxjx

jeex

21)sin( Euler’s Identity: , )sin()cos( xjxe jx jxjx eex

21)cos(

Differentiation/integration become algebraic operations w/ phasors (i.e., complex exponentials)

jdtd

jdt 1 Ex: )()( tjtj

dtd eje

Capacitor Impedance: Cj

ZC1 ICE – Current (I) LEADS Voltage (EMF) by 90°

Inductor Impedance: LjZL ELI – Voltage (EMF) LEADS Current (I) by 90°

Complex Impedance/Generalized Ohm’s Law: I

VZ

allows for easy nodal analysis (no differential equations); series/parallel resistor laws apply

Maximum Average Power Transfer Theorem

power transferred to load impedance ZL

is maximized when ZL=Zth*

Decibel (dB) – unit of measure for ratios of power, voltage, and current levels (often used to

express gain). Power: 1dB=10log10(P1/P2); V,I: 1dB=20log10(V1/V2)=20log10(I1/I2)

Frequency Response – system’s input output transfer function vs. frequency (given

sinusoidal input). Both magnitude and phase plots are needed (output freq = input freq)

General transfer function – can be written as a product of poles and zeroes

Error! Bookmark not defined.

11jj

j

21

)(

pp

jAeH21

11zzn

jj zeroes – roots of the numerator

poles – roots of the denominator

Break point frequency BP – poles and zeros are break point freq’s

at a zero frequency, the magnitude is +3dB (= 2) and the phase is +45°

at a pole frequency, the magnitude is -3dB (=1/ 2) and the phase is -45°

Bode Plot – logarithmic plots for frequency response

Aej

j 1/j (1+j / z) 1/(1+j / p) )( jH

to draw Bode plot for general transfer function, add individual pole and zero plots

z z10

10z

dB40 decdB20

dB0

dB20

z z10

10z

2

04

p p1010p

decdB20

decdB20

A

)( jH dB0 dB0 dB0

1 1 dB20

dB40decdB20

p10p

p10

2

4

0)( jH

2

002

Filters

Lowpass Filter (LPF) – VC in RC circuit / VR in RL circuit / VC and RLC circuit

(for current output, switch from series to parallel and switch L and C)

RLjV

V

in

outH1

1)( RCjV

V

in

outH1

1)( LCjRCjV

V

in

outH2

1

1)(

Highpass Filter (HPF) – VL in RL circuit / VR in RC circuit / VL in RLC circuit

(for current output, switch from series to parallel and switch L and C)

RLj

RLj

V

V

in

outH1

)( RCj

RCj

V

V

in

outH1

)( LCjRCj

LCj

V

V

in

outH2

2

1)(

Bandpass Filter (BPF) – VR, IR in RLC circuit

LCjRCj

RCj

V

V

in

outH2

1)(

at low freq, cap. impedance CjCZ 1 dominates

inoutinZ

V

Z

VRCVjIRVCVjI

C

in

tot

in ,

at high freq, ind. impedance LjZL dominates RLj

VoutLj

V

Z

V

Z

Vinin

L

in

tot

in IRVI ,

Resonant Frequency LC

o1

At o, oCL

CjC jZjZo

1 , oCL

oL jZjLjZ inout VV

(capacitor and inductor impedances are equal in magnitude, opposite in sign)

Characteristic Impedance: CLZo

BPF Bandwidth = 2 = difference between half-power frequencies

Quality Factor Q – (1) measure of “peakiness” or filter selectivity (high Q low bandwidth)

(2) measure of energy stored vs. energy dissipated (high Q low loss)

21

2ooQ series RLC:

R

CL

R

ZoQ parallel RLC:

CL

RZR

o

Q

Tradeoffs: Bandwidth/selectivity/speed/energy loss

(e.g., high Q low (high selectivity) low slow transients e- t

)

V

III. DIODES

Passive devices that only pass current in one direction

Shockley Diode Equation: 1thDVv

SD eIi

IS = reverse-bias saturation current (~10-12 A for Silicon)

Vth = kBT/q = thermal voltage (~26mV @ room temp T=300K)

Large-Signal Diode Model (simplifies circuit analysis)

2 states: “on” – forward bias (vD = VT): iD 0

“off” – reverse bias (vD < VT): iD = 0

VT = threshold voltage ~ 0.6V

Ideal Diode Model (Perfect Rectifier) large-signal diode model with VT = 0

Zener Diode (simplified) 3 states: forward bias: vD = VT, iD 0

reverse bias: VBD < vD < VT, iD = 0

breakdown: vD = VBD, iD 0

Diode Circuit Analysis – Method of Assumed States

(1) Guess the state of each diode (on or off). For large-signal diode model, replace “on”

diodes with voltage source with voltage drop VT and “off” diodes with open circuits.

(2) Solve the circuit using KCL/KVL.

(3) Check if assumptions for diode states were correct (i.e., check that “on” diodes have iD 0

and “off” diodes have vD < VT). If not, start over, guessing new states for the diodes.

Rectifier Circuit

Peak Detector Circuit (VT=0)

AC-DC Converter (VT=0)

I

X. MOSFET

Metal Oxide Semiconductor Field Effect Transistor (transistor – a 3+ terminal device in which one terminal controls the current flow between the other two terminals)

For a MOSFET, the gate controls the current flow between source and drain.

For an n-channel MOSFET (NMOS), a positive gate voltage produces current flow

For a p-channel MOSFET (PMOS), a negative gate voltage produces current flow

NMOS PMOS

analog

digital

Circuit Symbols: NMOS Physical Structure:

NMOS IV Characteristic – Square Law Model

3 regions of operation:

cutoff VGS < VTn IDS = 0

triode/linear VGS > VTn

VDS VGS - VTn IDS = Kn(VGS-VTn-VDS/2)VDS

saturation VGS > VTn

VDS VGS -VTn IDSAT = ½Kn(VGS-VTn)

2

VGS = VG–VS , VDS = VD–VS

VTn = threshold voltage (NMOS)

VDSAT = VGS - VTn = saturation voltage

IDSAT = saturation current

Kn = constant determined by manufacturing process and transistor size (units: A/V2)

Channel-Length Modulation Parameter

In the saturation region, IDS is not perfectly constant for all VDS VDSAT; as VDS increases,

IDS also increases. An additional factor (1+ VDS) in the IV equation models this effect (the

factor is also added to the triode equation to make the IV curve continuous):

cutoff VGS < VTn IDS = 0

triode/linear VGS > VTn

VDS VDSAT IDS = Kn(VGS-VTn-VDS/2)VDS(1+ nVDS)

saturation VGS > VTn

VDS VDSAT IDS = ½Kn(VGS-VTn)

2(1+ nVDS)

PMOS IV Characteristic – Square Law Model

Same as NMOS, but switch polarity for everything (VTp is typically negative)

cutoff VSG < -VTp ISD = 0

triode/linear VSG > -VTp

VSD VSG + VTp ISD = Kp(VSG+VTp-VSD/2)VSD(1+ pVSD)

saturation VSG > -VTp

VSD VSG +VTp ISD = ½Kp(VSG+VTp)

2(1+ pVSD)

X

. MOSFET CIRCUIT ANALYSIS

Notation: uppercase w/ uppercase subscript (e.g., VIN, VOUT) – DC large signal

lowercase w/ lowercase subscript (e.g., vin, vout) – AC small signal

lowercase w/ uppercase subscript (e.g., vIN, vOUT) – total signal, DC+AC

Large-signal Analysis – find DC operating point (models nonlinearity of MOSFET IV equation)

Method 1: Load-line (graphical) Analysis. Requires MOSFET IV curves.

Method 2: Method of Assumed States.

(1) Guess region of operation for each MOSFET.

(2) Solve circuit with KCL/KVL/nodal analysis, substituting

appropriate IV equation for MOSFET IDS.

(3) Check that assumptions for MOSFET operating regions were

correct (triode: VGS VT, VDS VGS-VT; saturation: VGS

VT, VDS VGS-VT). If not, start over, guessing new operating

regions for the MOSFETs.

Large-signal

Circuit Model

Small-signal Analysis – find small-signal gain, Rin, Rout (use a linearized circuit model for the MOSFET)

small-signal circuit model is a linearized model for the MOSFET, only valid for small

signals near a given DC operating point (AKA “quiescent point”)

allows for linear circuit theory (superposition, phasor analysis)

transconductance: Q

v

im

GS

DSg output resistance:

QDS

11

v

igoDSds

r

Note: Evaluate small-signal parameters at DC operating point

small-signal parameter Gm ro

Small-signal

Circuit Model

triode/linear KVDS(1+ VDS) small VDS: 1/[K(VGS-VT)]

saturation K(VGS-VT)(1+ VDS) 1/[K(VGS-VT)2

]

MOSFET Amplifier Analysis (1) Large-signal analysis – Find DC operating point w/ load-line analysis or method of assumed states.

(2) Small-signal analysis – Zero out all DC sources, replace MOSFETs with small-signal model, and

find gm and ro for each MOSFET at the DC operating point.

To find voltage gain Av = vout/vin, solve for vout using KCL/KVL/nodal analysis.

To find Rin and Rout, zero out all independent sources and find Rth at the input and the output (this

may require VTEST/ITEST method).

Common Source Amplifier

Large Signal Small Signal

Av=vout/vin = -gm(ro || RD)

Rin =

Rout = ro || RD

XI. OP-AMPS

Operational amplifier – high-gain voltage amplifier with differential inputs and single output Circuit Symbol Circuit Model Input/Output Characteristic

Vo = A(Vp-Vn), Vo = [VSS,VDD] Note: Vo cannot exceed the power supply rails VDD and VSS

A = Gain, Rin = input resistance, Rout = output resistance

Ideal op-amp: A , Rin , Rout 0

Negative Feedback – since it’s hard to make the op-amp gain stable over all operating

conditions (the gain fluctuates with temperature, process variation, and power supply noise),

negative feedback is used to stabilize the op-amp output negative feedback usually occurs when the output is connected to the negative input terminal

Suuming Point Constraint – for ideal op-amp in negative feedback

(1) ip=in=0 (since Rin= ) (2) vp=vn (for stable Vo=A(Vp-Vn), A= )

Op-amp Analysis – (1) Check for negative feedback. (2) Apply summing point constraint.

(3) Solve the circuit using circuit-analysis techniques (remember that Vo cannot exceed the supply rails).

Op-amp Circuits Inverting Amplifier Noninverting Amplifier Unity-gain Buffer

Adder Subtractor

1in

out

V

V

1

2

R

R

V

V

in

out

2

11R

R

V

V

in

out

211

2 VVVR

Rout

212

3

1

3 VVVR

R

R

Rout

Integrators

LCjV

V

in

out

2

1RLjV

V

in

out 1

RCjV

V

in

out 1

Differentiators

RLjin

out

V

VLCj

in

out

V

V 2RCj

in

out

V

V

• Cascading Op-amp Circuits – Find gain of each stage and multiply them together to get total gain

XII. DIGITAL CIRCUITS

analog: signals (voltage and current) are continuous with time

digital: signals are discrete (e.g., “0” and “1”) advantage: less sensitive to noise, easier to transmit

Booelan Algebra – Primitive Rules

Associative A + (B + C) = (A + B) + C A · (B · C) = (A · B) · C

Commutative A + B = B + A A · B = B · A

Distributive A + (B · C) = (A + B) · (A + C) A · (B + C) = (A · B) + (A · C)

Identity A + 1 = 1 A · 0 = 0

Identity A + 0 = A A · 1 = A

Complement A + A = 1 A · A = 0

Idempotence A + A = A A · A = A

Absorption A + (A · B) = A A · (A + B) = A

Absorption A + ( A · B) = A + B A · ( A + B) = A · B

Common Gates (Note: Bubble means inversion)

DeMorgan’s Laws (AKA “bubble pushing”)

(1) BABA

(2) BABA

Truth Tables – list output value for each input combination (2n entries for n inputs)

Sum of Products Form – write output logic expression as sum (OR) of

products (ANDs), where each product corresponds to each “1” entry in the truth table

A B C Out

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 0

Ex: CBACBACBAOut

MOSFET Switch Models (NMOS) Ideal Switch Model Switch-Resistor Model

Noise Margins

Voltage Output High/Low:

VOH=F(VOL), VOL=F(VOH)

Voltage Input High/Low (VIH, Vw

IL): here voltage transfer curve slope=-1

N

L –VOL

oise Margin High/Low:

NMH = VOH–VIH

NML = VIL–VOL

ogic Swing: VOH

NMOS Inverter (Resistor Pull-up)

Loadline Analysis:

NMOS Inverter Disadvantages:

No rail-to-rail swing (low noise margins)

Large RD required to keep VOL low and power low [I=VDD/(RD+Ron)]

Large RD means large area and slow transient response for Vout=0 VDD

CMOS Inverter

Voltage-Transfer Characteristic:

Loadline

Analysis:

CMOS Inverter Advantages: Rail-to-rail swing (big noise margins)

No static power consumption (either NMOS or PMOS off)

NMOS Pass Strong “0”, Weak “1” – For Vin=VDD: Since VGS VTn for NMOS on and

VGS=VDD–VOUT, VDD–Vout VTn, Vout VDD–VTn NMOS can’t pass strong “1”

PMOS Pass Strong “1” , Weak “0” – (same analysis as above)

General CMOS Logic Gate Implementation

Pull-up network (PUN) and Pull-down n

(PDN) are complementary (only one is “on” at a

time), so Vout is either VDD or GND (“0” or “1”)

PUN

etwork

and PDN are duals of each other (parallel

Procedure

transistors in one network are series transistors

in the other network)

: (1) Express logic as XF , the NOT of some logic expression X.

ND, parallel NMOS=OR.

CMOS Inverter Propagation Delay – delay from input to output due to output load capacitance

measured between 50%

put

use switch-resistor model for

high-to-low delay (NMOS on): low-to-high delay (PMOS on):

p = (tpHL+tpLH

eral CMOS Gate Delay itch-resistor model, find Req for PUN or PDN, tp=0.69ReqCL

(2) Since F=0 when X=1, construct PDN from X. Series NMOS=A

(3) Construct the PUN as the dual of the PDN.

transition points of the in

and output signals

MOSFETs

tpHL=0.69RnCL tpLH=0.69RpCL

average propagation delay: t )/2

Gen

replace MOSFETs with sw