Hyundai L-50 A

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Multiscanning Color Monitor

TECHNICAL SERVICE MANUAL

L50A(L50C)

p://

monitor.hei.co.kr

p://

hyundaiQ.com

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L50A(L50C) Technical Service Manual

Safety PrecautionWARNINGService should not be attempted by anyone unfamiliar with the necessary precautions on thismonitor.The followings are the necessary precautions to be observed before servicing.

1. When managing this monitor , cover with shield plate to avoid to scrach on LCD surface.

2. When replacing a chassis in the cabinet, always be certain that all the protective devices areput back in place, such as nonmetallic control knobs, insulating covers, shields, isolationresistor capacitor network etc.

3. Before returning the monitor to the customer, always perform an AC leakage current checkon the exposed metallic parts of the cabinet, such as signal connectors, terminals, screwheads, metal overlays, control shafts etc, to be sure the monitor is safe to operate withoutdanger of electrical shock.

General Information1. Description

This 15" LCD color display monitor is operated in R, G, B drive mode input.

2. Operating instructions2-1. Front

Power Switch , Menu, Select, Down, Up, DPMS (Power) LED

2-2. RearInput connector (AC & Signal Cable)

2-3. OSD ControlsH/V Position, Clock Phase, Brightness, Contrast, Recall,Color Control, Language, AutoAdjust, Miscellaneous

3. Electrical Characteristic3-1. Power Supply

AC/DC - Input Voltage : 90V~264VInput Current : 1.0 A Max

Input Ferquency : 50 ~ 60Hz- Output Voltage 12V/5VOutput Vurrent 2A/2A

3-2. Video Input SignalLevel : 0.7 Vp-p analog signal(at 75 ohm termination to ground)Polarity : Positive

3-3. Horizontal Synchronization SignalLevel : TTL High : 2.4V min

Low : 0.4V maxPolarity : - or +

Frequency : 31kHz ~ 60kHz

3-4. Vertical Synchronization SignalLevel : TTL High : 2.4V min

Low : 0.4V maxPolarity : - or +

Frequency : 56Hz ~ 75Hz

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Control DescriptionFront View

Support Modes

LED Indicator Soft Power Switch

H Frequency(kHz)

31.5

31.5

37.9

37.9

46.9

48.4

56.5

60.0

V Frequency(Hz)

70.0

59.9

72.8

60.3

75.0

60.0

70.1

75.0

HPolarity

0

0

0

1

1

0

0

1

VPolarity

1

0

0

1

1

0

0

1

VPolarity

28.322

25.175

31.500

40.000

49.500

65.000

75.000

78.750

NO

1

2

3

4

5

6

7

8

Resolution

720 x 400

640 x 480

640 x 480

800 x 600

800 x 600

1024 x 768

1024 x 768

1024 x 768

Refresh rate

70.087

59.940

72.809

60.317

75.000

60.004

70.069

75.029

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Video Input SignalRecommended signal are shown below

Video SignalVideo level : 0 to 700mVPolarity : positiveVideo Input : RGB separated

Analog levelSync input : H-Sync(TTL level)

V-Sync (TTL level)

WaveformVideo input(R.G.B)


ACTIVE (T4)

Front Porch(T5)

Period (T1)

Sync Width (T2)

Back Porch (T3)

ACTIVE (T4)

Front Porch(T5)

Period (T1)

Sync Width (T2)

Back Porch (T3)

H-Sync V-Sync

0

1

2

3

4

251

252

253

254

255700mV

0mV

Signal: 256 level grayscale

Linear stepping:

(2.73mV ~ 256 Steps)

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Video Input TerminalA 15 Pin D-sub connector is used as the input signal connectorPin and input signals are shown in the table below.

Pin Description

D-Sub miniature connector

SIGNALPIN NO.

3

2

1

5

4

6

7

8

9

10

11

12

13

14

SEPARATE SYNC/DDC 1/2B

RED

GREEN

BLUE

GND

RETURN

RED GROUND

GREEN GROUND

BLUE GROUND

N.C

LOGIC GROUND

GROUND

SDA

H-SYNC(TTL)

V-SYNC(VCLK)

15 SCL

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Connecting with External EquipmentCautionsBe sure to turn off the power of your computer before connecting the monitor.


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Theory of Operation1. AC/DC Adapter

Input voltage : 90 ~ 264 Vac, 50/60 HzInput current : Max 1A (Vin : 90Vac , 50Hz)Inrush current : 15A peak (At 115Vac Max . Load)

30A peak (At 230Vac Max. Load)

2. DC/AC INVERTERInput voltage : DC 12VInput current : 2.0A(Max)Frequency(switching) : 40 - 80 KHzOn/off control voltage : 5.0V

3. DPMS MODEReference to DPMS files

Mode

Normal

Suspend

off

LED

10W

5W

LEDIndicator

40WGreen

Orange

Orange

Unplugged 0WNot illuminated

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On Screen Controls & LED IndicatorThe menu for screen setting adjustment is located in the OSD and can be viewed in one offive languages OSD feature andmain funcrions are as follows:

The OSD adjustments available to you are listed below.

BRIGHTNESS

Adjust the brightness of the screen.

CONTRAST

Adjust the contrast of the screen.

COLOR CONTROL

Color temperature affects the tint of the image. With lower colortemperatures the image turns reddish and with higher temperatures

bluish.

There are three color settings available: Mode 1(a warm white), Mode 2(a cool white)or USER. With the USER setting you can set individual values for red, green and blue.

H/V POSITION

H-POSITION

Adjusts the horizontal position of the entire screen image.

V-POSITION

Adjusts the vertical position of the entire screen image.

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CLOCK PHASE

PHA SE

Adjust the noise of the screen image.

CLOCK

Adjust the horizontal size of the entire screen image.

AUTO ADJUST

You can adjust the shape of screen automatically at the full screen pattern.

M ISCELLANEOUS

RECALL

Recall the saved color data.

OSD TIM ER

You can set the displayed time of OSD Menu window on the screen by using thisadjustment.

OSD POSITION

Adjust the OSD menu's horizontal or vertical position on the screen.

LANGUAGE

You can select the language in which adjustment menus are displayed.The following languages are available : English, French, German, Italian,Spanish, Swedish, Finnish, Danish, P

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Getting Fine Picture

Step 1. At first Display, a full screen, such as, Window's background or "H" character shouldbe achieved by using Editor (ex: Notepad. exe)

Step 2. Adjust the screen to the center of the Display(LCD), by using the top and bottom

display controls. (i.e.Using V-Position Adjust menu)

Step 3. Adjust the screen to the center of the Display(LCD), by using the right and leftdisplay controls. (i.e.Using Clock and H-Position adjust menu)

Step 4. Adjust the Clock-phase until the "H" Character displays clear.

Step 5. Using the Contrast. Brightness, and Color Control menu, set the color to yourpreference.

Step 6. When you finish the adjustment, you can save your settings by pressing on the menuuntil the OSD screen has disappeared.

Factory Setting & EEPROM Initialization Method

Factory Setting Method- Connect the signal cable and power cable to the LCD monitor.- Press Power switch with pressed MENU key.(Menu key + Power key).

- Then, a User can change the factory setting value in OSD menu.- Save changed value and Turn off the power s/w.- Turn on the power, adjust the screen.

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Specification

LCD Module

SIZE 15 Viewable diagonal

Dot Pitch 0.297mm

BrightnessResponse Time

180 cd/m2

(MIN), 250 cd/m2

(TYP)20m- sec (Typ)

InputSignal R.G.B Analog

Connector 15 pin D-SUB Connector

SYNCH-Freq 31.0kHz ~ 60.0kHz

V-Freq 56.0Hz ~ 75Hz

DisplayArea

Color

304(H)X228(V)mm

16.2M Colors

Resolution

Video Bandwidth

User Control&

OSD Control

Contrast,Brightness,H-V Position,

Clock Phase, Color Control, Language,

Auto Adjust, Miscellaneous

Power Management VESA DPMS Standard

Plug & Play VESA DDC 1/2B

Safety &Regulation

EMC

Ergonomi

Safety

FCC CLASS B , CE , VCCI

TCO

cULus, CE, TUV-GS, SEMKO

Temperature

30 to 80%(Non-condensing)

5 to 90%(Non-condensing)

packed

Humidity

Operating

Operating

Storage

Storage

5 to 35 C

- 5 to 45 C

Weightunpacked

Dimension(WXHXD mm)

* Specification is subject to change without notice for performance improvement.

4.4Kg

367X353X188.3mm

3.1Kg

1024 X 768 @ 75Hz

80MHz

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Critical Parts Specification1. LCD Module

HT-15X13(LTM150XH-L01 is a a-si TFT active matrix color liquid crystal comprisingamorphous silicon TFT attached to each signal electrode, a driving circuit and a backlight.HT-15X13(LTM150XH-L01 has a built-in backlight display area contains 1024X768 pixelsand can display full color (16.2M colors)

Display area 304(H)X228(V)mmDrive system a-si TFTDisplay color 16.2M ColorsNumber of Pixel 1024X768Pixel arrangement RGB vertical stripPixel pitch 0.297(H)X0.297(V)mmWeight 300:1Viewing angle

Horizontal: 80 degree(3 clock, 9 clock)/45(12 clock) 80 (6 clock)Vertical: 40 degree(12 clock) ,55 degree(6 clock)/65(3 clock, 9 clock)

Response time 20ms(Typr)Luminance 250cd/m2(Typ)Signal system Digital RGB signals, Sync signals(H, V-Sync),

Dot clock(DCLK) , DE(Data Enable)Supply voltage 3.3VBacklight Edge light type: Four colt cathode fluorescent lamps

With in- verterPower consumption 1.5W(TYP) without B/L

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2) INTERFACE CONNEXTION2-1) Electrical Interface

CN1 Interface connector : DF14H-20P-1.25H(HIROSE) or equivalent

User side connector : DF14-20S-1.25C(HIROSE)or equivalent

Pin No

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

Symbol

VDD1

VDD2

VSS

VSS

RIN0-

RIN0+

VSS

RIN0-

RIN0+

VSS

RIN2-

RIN2+

VSS

RCLKIN-

RCLKIN+

VSS

RIN3-

RIN3+

VSS

NC

Remark

Tx pin #48

Tx pin #47

Tx pin #46

Tx pin #45

Tx pin #42

Tx pin #41

Tx pin #40

Tx pin #39

Tx pin #38

Tx pin #37

Pin No

Power Supply : +3.3V

Power Supply : +3.3V

Ground

Ground

LVDS Negative data signal (-)

LVDS Negative data signal (+)

Ground



Ground



Ground



Ground



Ground

Reserved

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2-2) LVDS InfcrfaceLVDS Transmitter : THC63LVDM83A or equivalent.

Input

signal

R0

R1

R2

R3

R4

R5

G0

G1

G2

G3

G4

G5

B0

B1

B2B3

B4

B5

HSYNC

VSYNC

DE

MCLK

R6

R7

G6

G7

B6

B7

RSVD

Pin No

51

52

54

55

56

3

4

6

7

11

12

14

15

19

2022

23

24

27

28

30

31

50

2

8

10

16

18

25

Pin No

48

47

46

45

42

41

40

39

38

37

System (Tx)

OUT 0-

OUT +

OUT1+

OUT1+

OUT2-

OUT2+

CLKOUT-

CLKOUT+

OUT+

OUT-

TFT-LCD (Rx)

IN0-

IN0+

IN1-

IN1+

IN2-

IN2+

CLKIN-

CLKIN+

IN3-

IN3+

DF14H-20P-1.25H

Pin No

5

6

8

9

11

12

14

15

17

18

RemarkTransmitter Interface

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. FFeeaattuurreess

The gmZAN1 device utilizes Genesis patented third-generation Advanced Image Magnification technology as

well as a proven integrated ADC/PLL to provide excellentimage quality within a cost-effective SVGA / XGA LCDmonitor solution.

As a pin-compatible replacement for the gmB120, thegmZAN1 incorporates all of the gmB120 features plusmany enhanced features; including 10-bit gammacorrection, Adaptive Contrast Enhancement (ACE)filtering, and an enhanced OSD.

Features

Fully integrated 135MHz 8-bit triple-ADC, PLL,and pre-amplifier

gmZ2 scaling algorithm featuring newAdaptiveContrast Enhancement (ACE)

On-chip programmable OSD engine Integrated PLLs

10-bit programmable gamma correction Host interface with 1 or 4 data bits Pin-compatible with gmB120

Integrated Analog Front End

Integrated 8-bit triple ADC Up to 135MHz sampling rates

No additional components needed All color depths up to 24-bits/pixel are

supported

High-Quality Advanced Scaling Fully programmable zoom Independent horizontal / vertical zoom Enhanced and adaptive scaling algorithm for

optimal image quality

Recovery Mode / Native Mode

Input Format

Analog RGB up to XGA 85Hz

Output Format

Support for 8 or 6-bit panels (with high qualitydithering)

One or two pixel output format

Built In High-Speed Clock Generator

Fully programmable timing parameters

On-chip PLLs generate clocks for the on-chipADC and pixel clock from a single referenceoscillator

Auto-Configuration / Auto-Detection

Phase and image positioning

Input format detection

Operating Modes Bypass mode with no filtering

Multiple zoom modes:with filteringwith adaptive (ACE) filtering

Integrated On-Screen Display

On-chip character RAM and ROM for bettercustomization

External OSD supported for greater flexibility Many other font capabilities including: blinking,

overlay and transparency

Package

160-pin PQFP

Applications

Multi-synchronous LCD monitors

Other fixed-resolution pixelated display devices

gmZAN1

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Figure 1. gmZAN1 Pin Diagram

CVSS1

Reserved

PSCAN

Reserved

Reserved

PD47

PD46

RVSS1

PD45

PD44

SRVDD1

RVDD1

PD43

PD42

PD41

PD40

PD39

SRVSS1

PD38

PD37

SRVDD2

PD36

PD35

PD34

PD33

PD32

PD31

PD30

PD29

RVSS2

PD28

PD27

RVDD2

PD26

PD25

PD24

PD23

PD22

PD21

CVDD1

OSD

_DA

TA2

OSD

_DA

TA1

OSD

_DA

TA0

OSD

_CL

K

OSD

_VR

EF

OSD

_HR

EF

CVSS4

MFB0

MFB1

MFB2

MFB3

MFB4

CVDD4

MFB5

MFB6

MFB7

MFB8

HCLK

MFB9

IRQ

RESETn

HDATA

HFS

N/C

ADC

_RV

DDA

RED+

RED

-

ADC

_RG

NDA

ADC

_GV

DDA

GREEN+

GREEN

-

ADC

_GG

NDA

ADC

_BV

DDA

BLUE+

BLUE

-

ADC

_BG

NDA

ADC

_VD

DA

Reserved

ADC

_GN

DA

SUB

_GN

DA

OSD_DATA3

OSD_FSW

MFB11

MFB10

DVDD

DVSS

DAC_DGNDA

DAC_DVDDA

PLL_DVDDA

Reserved

PLL_DGNDA

SUB_DGNDASUB_SGNDA

PLL_SGNDA

Reserved

PLL_SVDDA

DAC_SVDDA

DAC_SGNDA

SVDD

SVSS

TCLK

XTAL (Reserved)

PLL_RVDDA

PLL_RGNDA

Reserved

SUB_RGNDA

Reserved

VSYNC

SYN_VDD

HSYNC/CSSYN_VSS

Reserved

STI_TM1

STI_TM2

SCAN_IN1

Reserved

SCAN_IN2

SRVSS2

SCAN_OUT1

SCAN_OUT2

ADC_GND1

ADC_VDD1

ADC_GND2

ADC_VDD2

PPWR

PBIAS

PHS

PVS

CVSS3

PD0

PD1

PD2PD3

PD4

PD5

RVDD3

PD6

PD7

PD8

RVSS4

Reserved

Reserved

CVDD2

PD9

PD10

PD11

PD12

PD13

PD14

PD15PD16

RVSS3

PD17

PD18

PD19

PCLKB

PCLKA

PDISPE

PD20

CVSS2

121

122

123

124

125

126

127

128

129

130

131

132133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150151

152

153

154

155

156

157

158

159

160

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

80

79

78

77

76

75

74

73

72

71

70

6968

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

5150

49

48

47

46

45

44

43

42

41

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

gmZAN1 (160-Pin PQFP)

NOTE: For all power pads:C: Core

R: Ring

S: From pad 125 to 132, S represents Sclk DDS (source clk)

D: From pad 133 to 140, D represents Dclk DDS (destination clk)

NOTE: SRVSS1, SRVSS2 are connected to core VSS and SRVDD1 andSRVDD2 are connected to core VDD.

NOTE: The following signals have the same function but different names inthe gmB120 datasheet:

OSD-HREF is h ere call ed OSD_HREF

OSD-VREF is h ere call ed OSD_VREF

OSD-CLK i s here cal led OSD_CLK

OSD-DATA0 is here called OSD_DATA0




SYVDD is here cal led SYN_VDD

SYVSS is here c alled SYN_VSS

NOTE: when connected to a pull-down resistor, the MFB5 strapping option(sampled at reset) enables the use of an external crystal. MFB5 has aninternal pull-up resistor, so an external oscillator is the default.

NOTE: MFB6 is a strapping option to select a host data bus width of fourwhen connected to a pull-down (sampled at reset). Since MFB6 has aninternal pull-up resistor, a 1-wire host bus width is the default.

Pin Out Diagram

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FEATURES

8051 core, 12MHz operating frequency with double CPU clock option0.35uM process; 5V/3.3V power supply and I/O; 3.3V core operating1024-byte RAM; 64K-byte program Flash-ROM support In System Programming (ISP)Maximum 14 channels of PWM DAC

Maximum 31 I/O pinsSYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustmentBuilt-in low power reset circuitBuilt-in self-test pattern generator with four free-running timingsCompliant with VESA DDC1/2B/2Bi/2B+standardDual slave IIC addresses; H/W auto transfer DDC1/DDC2x dataSingle master IIC interface for internal device communicationMaximum 4-channel 6-bit ADCWatchdog timer with programmable intervalFlash-ROM program code protection selection40-pin DIP, 42-pin SDIP or 44-pin PLCC package

GENERAL DESCRIPTIONS

The MTV312M micro-controller is an 8051 CPU core embedded device especially tailored for CRT/LCDMonitor applications. It includes an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDCinterface, 4-channel A/D converter, and a 64K-byte internal program Flash-ROM.

BLOCK DIAGRAM

XFR

P0.0-7

P2.0-3

RDWRALE

INT1

P0.0-7

P2.0-3

RDWRALE

INT18051CORE

P1.0-7

P3.0-2

P3.4-5

RSTX1X2

ADCAD0-3

PWM DAC

DA0-13 DDC& IICINTERFACE

ISCLISDAHSCLHSDA

AUXRAM&DDCRAM

HSYNCVSYNC

HBLANKVBLANK

H/VSYNCCONTROL

P6.0-7

P5.0-6

AUXI/O

P4.0-2

MTV312M64

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PIN CONNECTION

MTV312M40 PinPDIP

DA2/P5.2 401

39

3837

36

35

34

33

32

31

30

29

28

27

26

2524

23

22

21

2

34

5

6

7

8

9

10

11

12

13

14

15

1617

18

19

20

DA1/P5.1

DA0/P5.0VDD3

VDD

VSS

X2

X1

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P6.2/AD2/HLFHI

P1.0

P1.1

P3.2/INT0

P1.2P1.3

P1.4

P1.5

P1.6

HSYNC

DA3/P5.3

VSYNC

DA4/P5.4

DA8/HLFHO

DA9/HALFV

DA5/P5.5

HBLANK/P4.1

DA7/HCLAMP

DA6/P5.6

VBLANK/P4.0

RST

P6.5/DA11

P6.4/DA10

P6.6/DA12

HSCL/P3.0/Rxd

P6.0/AD0

P6.1/AD1

HSDA/P3.1/Txd

P1.7

MTV312M44 PinPLCC

7

8

9

10

11

12

13

14

15

16

17

39

38

37

36

35

34

33

32

31

30

29

P1.6

24

P1.7

P6.1/AD1

P1.5

P6.0/AD0

HSDA/P3.1/Txd

P1.1

P3.2/INT0

P1.2

P1.3

P1.4

23

22

21

20

28

27

26

25

NC

6 5 4 3 2 1 44

43

42

41

40

NC

VDD3

DA0/P5.0

DA1/P5.1

DA2/P5.2

VSYNC

HSYNC

DA3/P5.3

DA4/P5.4

DA5/P5.5

19

18

RST

VDD

VSS

X2

X1

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P6.2/AD2/HLFHI

P1.0

P6.3/AD3

P6.4/DA10

HSCL/P3.0/Rxd

P6.5/DA11

P6.6/DA12

DA8/HLFHO

DA9/HALFV

HBLANK/P4.1

DA7/HCLAMP

DA6/P5.6

VBLANK/P4.0

P6.7/DA13

MTV312M42 PinSDIP

DA2/P5.2

40

1

39

38

37

36

35

34

33

32

31

30

29

28

2726

25

24

23

2221

2

34

5

6

7

8

9

10

11

12

13

14

15

1617

18

19

20

DA1/P5.1

DA0/P5.0

RST

VDD

VSS

VDD3

NC

NC

HSYNC

DA3/P5.3

VSYNC

DA4/P5.4

DA8/HLFHO

DA9/HALFV

DA5/P5.5

HBLANK/P4.1

DA7/HCLAMP

DA6/P5.6

VBLANK/P4.0

42

41

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P6.2/AD2/HLFHI

P1.0P1.1

P3.2/INT0

P1.2

P1.3

P1.4

X2

X1

P6.6/DA12

P6.5/DA11

HSCL/P3.0/Rxd

HSDA/P3.1/Txd

P6.4/DA10

P6.0/AD0

P1.7

P1.6

P6.1/AD1

P1.5

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PIN CONFIGURATION

A CMOS output pin means it can sink and drive at least 4mA current. It is not recommended to use suchpin as input function.A open drain pin means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used asinput or output function and needs an external pull up resistor.

A 8051 standard pin is a pseudo open drain pin. It can sink at least 4mA current when output is at low level,and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uAto maintain the pin at high level. It can be used as input or output function. It needs an external pull upresistor when driving heavy load device.

POWER CONFIGURATION

The MTV312M can work on 5V or 3.3V power supply system.In 5V power system, the VDD pin is connected to 5V power and the VDD3 needs an external capacitor, alloutput pins can swing from 0~5V, input pins can accept 0~5V input range. And ADC conversion range is 5V.However, X1 and X2 pins must be kept below 3.3V.In 3.3V power system, the VDD and VDD3 are connected to 3.3V power, all output pins swing from 0~3.3V,HSYNC, VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V. Andthe ADC conversion range is 3.3V.

8051 Standard Pin

4mA

4mA

OutputData

Pin

CMOS Output Pin Open Drain Pin

2 OSCperioddelay

4mA 10uA

OutputData

120uA

Pin

4mA

InputData

No Current

4mAOutputData

PinInputData

VDD

VDD3

5V

10u

MTV312M in5V System

3.3V

VDD

VDD3

MTV312M in3.3V System

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BLOCK DIAGRAM

GENERAL DESCRIPTION FEATURES

The CS5828 receives four sets of 7-bit data inCMOS logic level and converts them into four low-

voltage differential signaling (LVDS) serial channels.The 7-bit input data is referenced to the CKIN signal.The RF pin selects either rising or falling edge triggerof CKIN. Parallel to serial conversion is performed bya 7X internal generated clock reference using on-chip PLL using CKIN. A copy of CKIN but phase-locked to the output serial streams, CLKOUT, is alsoconverted to the fifth LVDS channel. The CS5828offers a reliable communication media using LVDSsignaling and provides low EMI dealing with wide,high-speed TTL interfaces.

This is especially attractive for interfaces betweenGUI controller and display systems such as LCD

panels for SVGA/XGA/SXGA applications.

Four 7-bit serial and one clock LVDS channels.Compatible with ANSI TIA/EIA-644 LVDS stan-

dard.Wide CKIN ranges from 31MHz to 85MHz.Fully integrated on-chip PLL that provides 7XCKIN serial shift clock.Pin selectable for rising or falling edge trigger.Support power-down mode.5V/3.3V tolerant data input.Single 3.3V supply operation.CMOS low power consumption.Functional compatible with DS90C385.Available in 56-pin TSSOP package.

PARALLEL-IN SERIAL-OUT7-Bit SHIFT REGISTER



SHIFT/LOAD_N

DIN

CLK

PHASE LOCK LOOP

R/FCLK

7xCLK

SHIFT/LOAD_N

CONTROL LOGIC

D19,D20,D21,D22,

D27,D5,D10,D11,

RFCKIN

SHTDN

EN

CKOP

CKON

CS5828

DIN

CLK

DIN

CLK

SHIFT/LOAD_N

SHIFT/LOAD_N

EN

Y3P

Y3N

EN

Y2P

Y2N

EN

Y1P

Y1N

EN

Y0P

Y0N


DIN

CLKSHIFT/LOAD_N

D0,D1,D2,D3,D4,D6,D7

D8,D9,D12,D13,D14,D15,D18

D24,D25,D26

D16,D17,D23

CS5828

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PIN CONNECTION DIAGRAM

Figure-1 56-pin TSSOP

1

2

34

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

2425

26

27

28

VDD

D5

D6D7

VSS

D8

D9

D10

VDD

D11

D12

D13

VSS

D14

D15

D16

RF

D17

D18

D19

VSS

D20

D21

D22D23

VDD

D24

D25

CS5828

D4

D3

D2VSS

D1

D0

D27

LVDS_VSS

Y0M

Y0P

Y1M

Y1P

LVDS_VDD

LVDS_VSS

Y2M

Y2P

CKOM

CKOP

Y3M

Y3P

LVDS_VSS

PLL_VSS

PLL_VDD

PLL_VSSSHTDN

CKIN

D26

VSS

56

55

5453

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

3332

31

30

29

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A

A

B

B

C

C

01.09.04

3

1

SHEET

CONTENTS

4. LVDS & Power

Date

G

4

2. gmZAN1/2 2

ASCHEMATIC

REVISION HIST

L50C(S527B/L550B/L1510B) Schemati

3. MCU(MTV312M)

1. Contents, Revision History

01.09.20

01.10.10

W

W

55. BLOCK DIAGRAM

E01.10.23

E01.11.29

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5

5

4

4

3

3

2

2

PWM_BRIGHT

HDATAF0HDATAF1HDATAF2HDATAF3

MUTE

GND

+5V

GND

GND

+5V

GND

+5V

GND

+5V

+5V

+5V

+5V

GNDGND

GND

R301

10K

C309

1uF/50V

C302

0.1uF

R319 470

C30410uF/16V

C305

10uF/16V

R314 470

MTV312M

44Pin

PLCC

U303

MTV312M

7

8

9

10

11

12

13

1415

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

3132

33

34

35

36

37

38

39

40

41

42

43

44

123456

RST

VDD

P6.3/AD3

VSS

X2

X1

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P6.2/AD2/HLFHI

P1.0

P1.1

P3.2/INTO

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P6.1/AD1

P6.0/AD0

P3.1/Txd

P3.0/Rxd

P6.4/DA10

P6.5/DA11

P6.6/DA12

P6.7/DA13

DA6/P5.6

DA7/HCLAMP

VBLANK/P4.0

HBLANK/P4.1

DA9/HALFV

DA8/HALFH

DA5/P5.5

DA4/P5.4

DA3/P5.3

HSYNC

VSYNC

DA2/P5.2

DA1/P5.1

DA0/P5.0

VDD3

NC

NC

C3130.1UF

C3140.1uF

R302 10K

C3150.1uF

C308

18pF

R

C3160.1uF

R304 10K

C3170.1uF

D301

RLS4148

R

U301

24LC08SOIC

1234 5

678

A0A1A2VSS SDA

SCLWP

VCC

R303 10K

X300

12MHz

R300

10K

R307

1K

R306 10K

R334 10K

C303

0.1uF

C306

0.1uF

R315

10K

CN301

HEADER 8

123456

78

R

R305 10K

R309 4.7K

C307

18pF

R

R308 4.7K

R310 4.7K

RR

C301

0.1uF

C300

10uF/16V

HDATAF[0..3] S HEE T

HFS SHEET

HCLK SHEET

/IRQ SHEET

LVDS_EN SHEET

ZAN_RST SHEET

PANEL_POWERSHEET 4

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5

5

4

4

3

3

2

2

1pxl/clk

RED

GREEN

BLUE

PD10

PD0

PD8

PD3

SLVDSR/F

PD16

PD[12..17]

PD36

PD13

PD4

PD14

PD12

PD40

PD5

PDISPE

PD7PD[6..11]

PHS

SLVDSPDN

PD38

PD2

PCLKA

SPLL-VCC

PD[0..5]

PD9

PD1

PD17

PD6

PVS

PD15

PD11

PD37

PD41

PD39

SO-TD6

STTL-GND

RX0-

RX1+RX1-RX0+

RX2-RX2+RXCLK-RXCLK+RX3-RX3+

SPLL-GND

+3.3V

GND GND

LVDS_3.3V

ZAN1_3.3V / ZAN2_2.5V

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

PANEL_3.3V

GND

GND

GND

LVDS_3.3V

GND

PANEL_3.3V

GND

GND

GND

+5V

+12V

U403

CS5824

1 562 553 544 535 526 517 50

8 499 4810 4711 4612 4513 4414 4315 4216 4117 4018 3919 3820 3721 3622 3523 3424 3325 3226 3127 3028 29

VCC TA4TD1 TA3TA5 TA2TA6 GND3GND TA1

TB0 TA0TB1 TD0

TD2 LVDSGNDVCC1 TA-

TD3 TA+TB2 TB-TB3 TB+GND1 LVDSVCC

TB4 LVDSGND1TB5 TC-TD4 TC+R/F TCLK-

TD5 TCLK+TB6 TD-TC0 TD+GND2 LVDS GND2

TC1 PLLGNDTC2 PLLVCCTC3 PLLGND1TD6 /PDWNVCC2 CLKIN

TC4 TC6TC5 GND4

C408

0.1uF

C401

0.1uF

R404 33

R401

1K

C402

0.1uF

C42033pF

R402 33

C413

22uF/16V

U400RC1117.3.3

SOT2231

3 2

GND

VIN VOUT

CN400

POWER

12V

6

5V2

GND

4

5V

5

GND3

12V1

R403 33

C42133pF

C42233pF

C423

100uF/16V

C405

22uF/16V

C411

22uF/16V

C414

22uF/16V

C406

0.1uF

R400

1K

R406 4.7K

C415

0.1uF

U401ZAN1 RC1117_3.3 / ZAN2 RC 1117_2.5

SOT2231

3 2

GND

VIN VOUT

C416

0.1uF

C409

0.1uF

C407

22uF/16V

C412

0.1uF

C410

22uF/16V

U402RC1117.3.3

SOT2231

3 2

GND

VIN VOUT

C425

0.1uF

C404

0.1uF

C400

0.1uF

R405 33

C403

0.1uF

C41933pF

1234

PD[0..5]SHEET 2

PD[6..11]SHEET 2

PD[12..17]SHEET 2

PD36SHEET 2PD37SHEET 2



PHST 2

PVST 2

PDISPET 2

PCLKAT 2

RX0-

RX1-RX1+

RX0+

RX2-RX2+RXCLK-RXCLK+RX3-RX3+

PANEL_POWERSHEET 2

L VDS _E N S HE ET 3

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Hyundai L-50 A

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