HYBRID ASSEMBLY RELIABILITY BY GLASSIVATION OF THE...

Electrocomponent Science and Technology1977, Vol. 4, pp. 117-124

(C)Gordon and Breach Science Publishers Ltd., 1977Printed in Great Britain

IMPROVED HYBRID CIRCUIT ASSEMBLY YIELDS ANDRELIABILITY BY GLASSIVATION OF THE

SEMICONDUCTOR CHIP

B. C. HEAP and S. A. FRANCE

Ferranti Limited, Chadderton, England

(Received March .5, 1977)

Lead glass passivation (glassivation) of semiconductor chips has been investigated. Glassivation of BC107 typetransistor chips has resulted in improved robustness and their ability to withstand ionic contamination better thancontrol chips. Increased yields were observed when glassivated transistor chips were assembled in ceramic fiatpackages.

1. SUMMARY

The paper describes the evaluation of lead glass layersdeposited from colloidal solutions to form continuousglasses over metallised bipolar transistor chips. BC107transistors were selected as the test vehicle because oftheir severe, low current gain specification and thesusceptibility of this parameter to ionic contamination,mechanical stress and general mishandling during theassembly process.

Three fundamental properties of the glass layerwere investigated:-

1) Thickness (i.e. whether sufficiently thick layerscan be deposited before crazing occurs as with silanedeposited oxides). The effectiveness of the thick glasslayers were evaluated using epoxy encapsulants knownto polarise under elevated temperature and bias tests.Results show that compared to standard ’non-glassivated’ chips large improvements in the stabilityof low current gain are made.

2) The effectiveness of the layer as an ionicbarrier was evaluated by soaking non-encapsulatedglassivated and standard chips in sodium-chloridesolution. The devices were then subjected to elevatedtemperature and bias tests. The results indicate agreatly improved barrier effectiveness.

3) The ability of glassivated devices to withstandvarious temperature time combinations was evaluatedand compared to standard chips. These temperaturetime combinations were typical of what is experiencedin Si Au eutectic die attach sequences and Cerdip/Cerpak glass frit and sealing operations. The compari-

117

son was made by measuring initial and final lowcurrent gain on the ’glassivated’ and standard devicesand results indicate a greatly improved robustness.

2. INTRODUCTION

Standard planar diffused transistors are assembled inhybrid microcircuits by either conductive epoxy orsilicon-gold (Si-Au) eutectic die attach techniques.Of the two techniques, conductive epoxy is the mostgenerally used because the temperatures involved indie attach are low compared to Si-Au eutectictechniques. It is generally acknowledged that assilicon bipolar transistors are subjected to progress-ively higher temperatures and/or longer times, theprobability of parameter degradation is increased.

However for some applications epoxy die attachtechniques are not suitable (i.e. low thermalimpedance or low VCE(SAT requirements). Highreliability may be required where parameter degrada-tion cannot be tolerated when subjecting the circuitsto stringent environmental tests. The general silicontransistor or integrated circuit chip is protected orpassivated by a layer of SiO2 which affords a greatdeal of protection. However, there are several ionicspecies, the most significant of which is sodium (Na+)which becomes mobile in SiO2 at temperaturesapproaching 150C. Consequently if the silicon chipis subjected to temperatures in excess of 150Cduring the assembly process or in subsequentenvironmental tests, then the SiO2 affords littleprotection and parameter degradation is likely.

118 B.C. HEAP AND S. A. FRANCE

GLASSIVATION

/

ALUMINIUM EMITTER BASE

FIGURE Glassivated ZT930 chip.

EPITAXIAL

FAILURES /o70.

6O

C]

00

CONTAMINATEDGLASSIVATED

z 4 + 8 ,0 ,z ,4 ,+ ,TEST TIME HOURS)

FIGURE 2 Graph of percent failures against test time for contaminated glassed transistors, contaminated controland uncontaminated control in ion getter experiment.

CHIP GLASSIVATION 119

A solution to the problem is to deposit a glasspassivating layer after metallisation and etch contactholes through the glass to the aluminium metallisationto allow subsequent wire bonding. The glass will workeffectively as a barrier to ionic contamination andhence decrease the temperature/time susceptibilityof the device and also improve its capability ofsurviving stringent environmental tests.

3. DISCUSSION

3.1 Deposition and Formation of GlassPassivating Layers

This is done by a sedimentation technique. Glass fritis mixed with methanol and particles of greater thanmicron diameter are settled out by controlled

centrifuging. The methanol left containing grains ofmicron diameter and less, now called the slurry,

is decanted off. Settling agents are added to the slurrysuch that the dielectric constant of the medium islowered sufficiently to allow particles to come outof suspension on centrifuging onto an underlying Siwafer. Too high a dielectric constant results in thelifting of the glass frit after centrifuge and too low adielectric constant presents localised agglomerates ofparticles giving non uniform layers. The volume ofslurry used per slice is selected so as to deposit aglassy layer 2 +- .02 micron thick when fired.The firing temperature of the glass is 550 C.Standard photoresist techniques are used to openwindows in the glass layer to allow wire bonding tothe underlaying aluminium metallisation.

An example of a glass passivated transistor isshown in Figure 1.

FAILURES %

60-

,NTAMINATEO

GLASSIVATED00 4 6 8 IO IZ 14 16 18 ZO

TEST TINE (HOURS)FIGURE 3 Graph of percent failures against test time for contaminated glassed transistors, contaminated controland uncontaminated control in ion barrier experiment.


3.2 Gettering Properties of Glassivation

Three groups of BC107 transistor chips wereprocessed to evaluate the gettering properties of theglassivation process (i.e. how the firing sequence ofthe glassivation process mops up any contaminationwhich may be present in the SiO2 passivation layerprior to glass deposition).

Contamination was introduced by taking devicesand subjecting them to a 10 min. boil in a 0.02molar NaC1 solution followed by a bake at 300Cfor 30 mins. NaC1 solution was chosen becausesodium is the most significant ionic contaminant.A control sample received no NaC1 contamination.

A contaminated control sample was processed asdescribed. A contaminated glassivated sample wasprocessed as described and then glassivated. The threegroups were assembled in TO18 packages and tested

by applying 30V reverse bias to the collector-basejunction at 165C. Figure 2 shows the % failure ofthe devices against test time. A failure is defined asgreater than 50% change in any of the followingparameters, clo, IEBO, HFI (10mA Ic)’ VCE(SAT),VBE(SAT), VCE(SUS or HFE (50/aA Ic). The plotsclearly show the gettering properties of the glass.

3.3 1on Barrier Properties of Glassivation

The previous experiment was repeated except thatthe glassivated sample was contaminated after glassdeposition. A failure versus time graph is shown inFigure 3 for this experiment. Again the ion barriercharacteristics are clearly shown by the comparisonof the plots.A second experiment was performed using an

hFE AT 50

120"

I00-

80-

60-

40"

ZO-

O,0

FIGURE 4

/_C]Q O TRANSISTORS

zo 40 eo ,oo

hFE AT 50pA (INITIAL)Graph of change in hFE for glassed and unglassed transistors in epoxy resin.


epoxy encapsulant. The epoxy was known to polariseat temperatures in excess of 150C. Consequently ifthe device was stressed electrically under the sameconditions as the previous experiment the dipoleswhen cooled down would be frozen in alignmentwith the applied electric fields. This would tend tocause instabilities in the encapsulated transistor.Figure 4 shows the stability of 50/A HFE of theglassed and non-glassed chip in the epoxy resin.The glassivated devices are clearly more stable thanthe control devices. The thickness of the glass issufficient to attenuate the dipole electric field at theSiO2/Si interface caused by the epoxy resin.

As a final test some glassivated BC 107B transistorswere subjected to the following tests.

a) 230C. 160 hrs. VCB 38V. VEB 4V.

b) 25C. 160 hrs. VCE 40V. C 7mA(i.e. Tj 230C).

c) Thermocycle -40C to +100C.A plot of HFE at 2mA is shown in Figure 5 at thevarious test stages. It shows that the transistors remainstable throughout rigorous environmental testing.

3.4 Toughness Evaluation

A simple piece of equipment was designed andmanufactured as shown in Figure 6. The samplewould be placed on the block and the arm releasedby turning the cam so that the diamond point would

, AT ZrnAFINAL)

160

150

140

Z30 C LIFE TEST.

o 25 C LIFE TEST

0 THERNOCYCLE

++0000 +

0 o

00

13t 0 0o

o

I00 IZO 130 140

h.f AT ZmA (INITIAL)150 160

FIGURE 5 Graph of change in gain for glassivated ZTX 107B transistors in BS9000 test.


DIAMOND TIPPED WEIGHTTOOL

HICROSCOPE I-

h’e AT I0 mA(FINAL)

600

,,I o

WAFER LOADEDON BLOCK

CAH & PUSH RODFOR RAISING &LOWERING THE ARM

FIGURE 6 Toughness evaluation equipment.

GLASSED TRANSISTORS

UNGLASSED TRANSISTORS

400

++ +

FIGURE 7

ZOO 400 600

T O,,,A ETAL)Graph of change hfe for glassed and unglassed transistors in cerpak.


Glass Passivated

Package

TABLEChange in 10mA HFE for glassed and unglassed transistors assembled in cerpak

1G 2G 3G 4G 5G 6G 7G 8G 9G 10G 11G 12G

T1 Hfe@10mA 5V.

T2 Hfe @10mA 5V.

T3 Hfe @10mA 5V.

T4 Hfe@10mA 5V.

Non Glass Passivated

Package

Initial 510 500 490 500 500 480 480 500 500 500 500 490final 500 530 530 510 500 490 500 540 520 530 520

Initial 490 520 500 480 490 490 500 510 490 480 480 490final 500 520 530 540 550 500 530 510 510 510 520

Initial 500 490 500 510 500 500 490 490 480 490 490 480final 490 520 510 530 510 520 550 510 510 510

Initial 510 500 500 490 500 510 500 490 490 480 500 490final 500 500 520 520 510 520 510 520 540 510

13 14 15 16 17 18 19 20 21 22 23 24

T1 Hfe@10mA 5V.

T2 Hfe @10mA 5V.

T3 Hfe @10mA 5V.

T4 Hfe@10mA 5V.

Initial 550 570 520 550 570 550 570final 220 650 580 310 600

Initial 550 400 540 570 520 540 580final 250 530 250 230 430 560

Initial 540 450 560 560 570 560 570final 220 400

Initial 550 560 550 570 560 540 300final 570

590 590 550 570 570600 470 560

540 550 560 580 560280 340

560 560 550 570 600480 540

560 530 590 570 600

be dropped from a consistent height (i.e. 2 cm) ontothe sample. Additional weights would be placed onthe arm in order to increase the force applied. Thistrial would test the resistance of the glass to verticallydirected damaging forces. The sample itself consistedof a 1.5 micron Aluminium layer on a silicon substratecovered with a 2 micron thick layer of glass. Failurewas adjudged to have occured when small cracks justemanated from the point of impact.

Horizontally directed damaging forces wereinvestigated by slowly lowering the point on to theglass and moving the sample in a horizontal direction.The weight of the arm was gradually increased andthe critical weight was reached when the point brokethrough the glass layer and exposed aluminiumbeneath. Results showed that the glass consistentlyfailed in the vertical mode with a force of 4 gms andin the horizontal mode with a force of 12 gms.

3.5 Assembly Evaluation

To evaluate the ability of glassivated chips to with-stand various time temperature combinationsencountered in typical assembly operations, a sampleexperiment was performed. 48 glassivated and 48non-glassivated control chips from the same diffusedwafer were measured for 10mA gain. The devices wereSi Au eutectically attached to a 4 position flatpackframe to make up 12 flatpack arrays each for theglassivated and control batches. The frames were thenglass fritted on to a ceramic base, ultrasonic Alumi-nium wire bonded the emitter and base to the frameand then hermetically glass sealed with a ceramic cap.The highest temperature to which the devices weresubjected was 500C during the sealing operation.The times were typical for each operation whilstnoting that one transistor chip will remain at


temperature whilst the other three devices are beingalloyed and bonded.

The initial 10mA gains were measured on thetransistors in chip form and then subsequentlyremeasured after subjecting them to the previouslydescribed assembly procedure. The results are shownin Table I. Devices from packages 1 G, 2G and 13,and 14 respectively were plotted on an HFE changegraph to illustrate the results comparatively.The package yield (i.e. 4 good transistors/package)for glassivated chips was 75%. The chip yield was88%. In comparison the package yield for non-glassivated chips was zero. The chip yield was 17%.The criteria of failure was a greater than 20% shiftin HFE (i.e. standard for BS9000 or C.E.C.C. rules).The results clearly indicate the greatly increasedrobustness of glassivated chips. (See Figure 7).

4. CONCLUSIONS

It has been demonstrated that deposition and firingof the glass layer on a silicon bipolar transistoreffectively neutralises any ionic contamination whichmay have been present prior to deposition. The glasslayer has been shown to be impervious to ionicimpurities and to be of sufficient thickness toeliminate any effect due to polarising encapsulantsetc.

The toughness experiment indicated that glassivateddevices could withstand the normal tweezer handlingexperienced in assembly operations and it effectivelyprotects the underlying aluminium layer fromscuffing. Finally the assembly evaluation indicatesthe degree to which the glassivated devices willwithstand long and high, time temperature combina-tions well in excess of those at which standard non-glassivated material exhibits parameter degradation.

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