HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng...

16
1 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory HW/SW Codesign Exercise 7: SystemC Yun Cheng [email protected] 14. November 2018

Transcript of HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng...

Page 1: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

1Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

HW/SW Codesign

Exercise 7:

SystemC

Yun [email protected]

14. November 2018

Page 2: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

2Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Overview

• Understand SystemC concepts through

code

• Discuss the SystemC code

• Discuss the outputs of the different

exercises

• Some slides based on UC Berkeley Tutorial:https://embedded.eecs.berkeley.edu/research/hsc/class/ee249/lectures/l10-SystemC.pdf

Page 3: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

3Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Basic components of SystemC code

• sc_main

• module

• process (threads, methods)

• channel

• interface

Page 4: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

4Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

FIFO Communication Example

Page 5: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

5Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Top1

Top Module

Page 6: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

6Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Top Module Declaration

Page 7: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

7Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

The FIFO Example

Top1

Producer Consumer

main main

Page 8: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

8Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Producer/Consumer Declarations

Page 9: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

9Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Top1

Producer Consumer

main main

FIFO

FIFO Channel

Page 10: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

10Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

FIFO Channel

Page 11: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

11Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Top1

FIFO Interfaces

Producer Consumer

main main

FIFO

Page 12: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

12Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Interface Declaration

Page 13: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

13Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Top1

The FIFO Example

Producer Consumer

main main

write read

read_event

write_event

FIFO

Page 14: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

14Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

FIFO Implementation

Page 15: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

15Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Top1

The FIFO Example

Producer Consumer

main main

write read

read_event

write_event

FIFO

modules

processes

channels

ports +

interfaces

events

interfaces

Page 16: HW/SW Codesign Exercise 7: SystemC · 2019. 1. 7. · HW/SW Codesign Exercise 7: SystemC Yun Cheng chengyu@ethz.ch 14. November 2018. 2 Swiss Federal Institute of Technology Computer

16Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Let’s run the code!

1. Download SystemC package from course

website

2. Compile SystemC 2.3

3. Run sample file

4. Add tracing

5. Analyze trace files