ELL 201 Homework 4 IIT Delhi

1. For the circuit to move from state A to state B, not only a certain amount of time (time_up) must pass, but x = '1' must also occur. The time counting should only start after x = '1' is received, resetting it if x = '0' happens before time_up has been completed. A similar condition is defined for the circuit to return from B to A. Design the corresponding circuit, considering that time_up and time_down are three and fi ve clock periods, respectively,

2. A sequential circuit has a single input x and a single output z. The input signal x can occur

in groups of 1, 2 and 3 pulses. If x = 1 for one clock period, the output z will be 1 for three clock periods before returning to

the starting state. If x = 1 for two clock periods, the output z will be 1 for two clock periods before returning to the starting state.

If x = 1 for three clock periods, the output z will be 1 for a single clock period before returning to the starting state.

Implement the above circuit using DFFs

3. A clock signal X is to be gated on and off by a signal m. The gating signal must be

arranged so that the circuit produces complete clock pulses only. A timing diagram for the network is shown in Figure below. Develop a synchronous sequential circuit

for implementing the above specification.

4. A sequential circuit has two inputs, x and s, and a single output z. The input x is a train of high frequency pulses. It is required to output every fourth input pulse when s = 0, and every third input pulse when s = 1. Design a circuit for the specification.