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Transcript of Hulle COA Unit I
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Computer Organization
and Architecture
Computer Architecture and Arithmetic
-- Mr. Hulle N. B.
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Syllabus
Unit I: Computer Architecture and Arithmetic (7 Hours)
Computer Architecture, Von Neumann Architecture,Functional Units, Basic Operational Concepts,Performance, Processor organization, Bus Structure,
Register Organization, Instructions and InstructionSequencing, Addressing Modes.
Arithmetic: Multiplication of positive numbers, Signed
Operand Multiplication, Booths Algorithm, Fast multiplication, Integer Division, Floating point Numbersand Operations, IEEE standards, Floating point arithmetic.
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Syllabus
Unit II: The Central Processing Unit (7 Hours)
Basic Processing Unit: Single Bus Organization, RegisterTransfer, Performing an arithmetic or logic operation,Fetching and storing word from/to memory,
Execution of complete instruction, branch instruction,Multi-bus Organization.
Hardwired Control: Design methods State table and
classical method, A complete Processor, Micro-programmed Control: Microinstructions, micro- programsequencing, wide branch addressing, microinstructionswith next address field, perfecting microinstructions,emulation.
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Syllabus
Unit III: Input-Output and Memory Organization (7 Hours)
I/O Organization: Accessing I/O devices, Interrupts:Interrupt Hardware, enabling and disablinginterrupts, handling multiple requests, Controlling
devices, exceptions, Interface circuits, Standard I/OInterfaces: PCI, SCSI, USB.
The Memory System: Memory Hierarchy, Internal
organization of memory chips, Cache memory,Performance Considerations, Virtual Memories
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Syllabus
Unit IV: Introduction to 16 bit microprocessor (7 Hours)
The 8086 microprocessor, architecture of 8086, pindiagram, programming model of 8086.
Logical to physical addressing, addressing modes,Instruction set, interrupt structure, 8086 Assemblylanguage programming.
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Syllabus
Unit V: Introduction to 32 bit microprocessor (7 Hours)
The 80386 microprocessor, Features and Architecture,Pin Description, Functional Description, Register Set.
Programming model of 80386: real mode, protectedmode and virtual mode, paging and segmentation,Multitasking, Interrupts, Exceptions and I/O
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Syllabus
Unit VI: Parallel Architectures and ARM (7 Hours)
Parallel architectures, classification, Instruction levelpipelining and Superscalar Processors, The structureof general purpose multiprocessor, Multiple Processor
Organizations, Closely and loosely coupledmultiprocessors systems.
Advanced RISC Machines (ARM): Introduction to
RISC, Instruction execution, characteristics, RISCarchitecture and pipelining, RISC Vs CISC.
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ENIAC (Electronic Numerical Integrator and Computer)
Brief History:
From ENIAC (Electronic Numerical Integrator andComputer) John Mauchly and John P Eckert,University of Pennsylvania (1943 - 1946)
For war purposes, ballistic trajectory
Weighted 30 tons, consumes 140 kwatts of electricpower, 15,000 square feet of space, only 5000addition per second
Not a digital computer, it was a decimal computer(analog)
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ENIAC
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ENIAC - details
Decimal (not binary) 20 accumulators of 10 digits
Programmed manually by switches
18,000 vacuum tubes
30 tons
15,000 square feet
140 kW power consumption
5,000 additions per second
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Von Neuman Architecture / EDVAC / IAS
John von Neuman proposed : EDVAC (ElectronicDiscrete Variable Computer) - first stored programcomputer -1945
1946 Von Neuman and his gang proposed IAS
(Institute for Advanced Studies) The design included :
main memory
ALU
Control UnitI/O
First Stored Program, able to perform : +, -, x, /
The father of all modern computer/processor
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Von Neuman Architecture / EDVAC / IAS
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Von Neuman Architecture / EDVAC / IAS
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Structure of von Neumann machine (IAS)
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von Neumann
Stored Program concept Main memory storing programs and data
ALU operating on binary data
Control unit interpreting instructions frommemory and executing
Input and output equipment operated by controlunit
Princeton Institute for Advanced StudiesIAS
Completed 1952
Used the term organ to describe devices
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View of a Computer System
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Thus todays computer types and classification is based purely on
their mode of usage & portability. (From the view point of an average
end user)
o DeskTop PC
o LapTop PC
o PalmTop PC
o Workstations
Computer Types
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The computer types based on their interconnection usage, sharing
of resources, multi-user, multiprocessors, remote access like operating
environments - includes
Distributed Computers
Parallel Computers
These two categories encompass:
Enterprise Systems or Mainframes Servers
Super Computers
Interconnections
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DeskTop PCs
As its name suggest desktop PC contains CPU box, display unit,
keyboard, including speaker and a mouse which can all be housed
on an office desk or a home table in the form of 3-box structure in
two models viz Table Top model and Tower model CPU cabinets.They are stand alone computer systems & found their fullest
usage in homes, schools, colleges, banks, offices.
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PalmTop PCs
All kinds of hand held computers including Pocket PC, Tablet PCs,
Mobile electronic gadgets, PDAs, e-books, Notepads, Mobile phoneswith internet Browsing facilities fall in this category.
Limited Battery Powered, Rechargeable, tiny toy like consumerelectronic devices the palm top PC. Touch and feel are more crucial
here while operating with limited storage and computational power.
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Workstations
Workstations are industry standard desktop computers with more
computational power and high-resolution graphic display with variety
of graphic input/output capability.
Workstation PCs are usually employed in the applications of
Computer Aided Design and Drafting (CADD). Simulation &
Modeling, Interactive Graphic design, Multimedia and other
engineering applications.
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Enterprise Systems or Mainframes
Enterprise systems or mainframes are like a family of computerswith tremendous computing power beyond workstations. Theircomputational activities are distributed among one main system(usually a server) and number of child nodes or intelligent PCs withor without local computing power / processor (usually clientcomputers) called dumb terminals.
Mainframes are preferred at business data processing corporateoffices. They are quite expensive with several hard disks, RAIDs and
backup storage units.
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Servers
A server computer is a derivative of either Mainframe orWorkstation PC. It can be a powerful desktop PC interconnected in aLAN as Server.
Many corporate offices are replacing their enterprise systems withsimple and affordable Local Area Network (LAN) of Desktop PCs.Where in there is a Single Server PC and a few Client PCs, all areinterconnected !
Examples of Servers:
File Server,Database Server,Print Server,Message Server /mail server,Web Server,
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Super Computers
One of the fastest computers type currently available, They areproblem scalable.
Computational speed of a super computer is measured interms ofFloating Point Operations Per Second or FLOPS.
Examples: Cray X/MP-14 , Param 8000, Param - Padma
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FUNCTIONAL UNITS
A computer in its simplest form comprises five functional units:
1) Input Unit
2) Output Unit
3) Memory Unit
4) Arithmetic & Logic Unit
5) Control Unit
I /O
Processor or CPU
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Functional Units
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Input Unit
Computer accepts encoded information through input unit. The
standard input device is a keyboard of a video monitor or terminal.
Whenever a key is pressed, keyboard controller sends the scanned
code of that letter, digit or symbol to CPU/Memory.Examples include Mouse, Joystick, Trackerball, Lightpen, Tablet or
Digitizer, Scanner etc.
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Memory Unit
Memory unit stores the program instructions, data operands on andresults of computations etc. Memory unit is classified as:
1. Primary /Main Memory 2. Secondary /Auxiliary Memory
1. Primary memory is a semiconductor memory that provides access atelectronic speed. Run time program instructions and operands arestored in the main memory. It contains a large number ofsemiconductorstorage cells.
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Main memory is classified again as RAM and ROM.
RAM is termed as Read/Write memory or user memory that holds
run time program instruction and data.
ROM holds system programs and firmware routines such as BIOS,POST, I/O Drivers that are essential to manage the hardware of a
computer.
ROMRAM
Memory Unit
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2. Secondary /Auxiliary Memory:
While primary storage is essential, it is volatile in nature (i.e. itscontents will be lost in the absence of power) and expensive too.Additional requirement of memory would be supplied as auxiliary
memory at cheaper cost.
Secondary memory are magnetic memories viz Floppy disk, Harddisk, Magnetic tape, CD-ROM etc.
Secondary memories are non volatile in nature (contents will not be
lost in the absence of power).
Memory Unit
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Arithmetic & Logic Unit
ALU performs all arithmetic & logical operations of the processor.
Like addition, subtraction, division, multiplication, AND, OR, etc.
The operands are brought into the ALU from memory and stored in
high speed storage elements called register.
Then according to the instructions the operation is performed in the
required sequence.
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Other output devices areprinters,plotters to take a paper copy of
the results, programs, graphs calledprint outor a hardcopy
Printers types: Dot Matrix printer, Inkjet printer, Laser printer. . .
Output Unit
Computer returns the computed results, error messages, etc., via
output unit.
The standard output device is a video monitor, LCD/TFT monitor.
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Control Unit
Control unit co-ordinates activities of all units by issuing
timing control signals like MEMR, MEMW, IOR, IOW.
Timing control signals hence issued by control unit
govern the data transfers as to when the appropriate
operation must take place. Control unit interprets or decides
the operation/action to be performed.
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Main conceptual events/operations of a computer
1. A set of instructions which perform a given task, called a programmust reside in the main memory of computer during its execution.
2. The CPU fetches those instructions sequentially one-by-one fromthe main memory, decodes them and perform the specifiedoperation on associated data operands in ALU.
3. Processed data i.e. useful information will be displayed on an output
unit.4. All activities pertaining to processing and data movement inside the
computer machine are governed by control unit.
Basic Operational Concepts
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Basic Operational Concepts
An Instruction consists of two parts: An Operation code and operand/s
ADD MLOC, R0
Execution steps: To add two operands
Step 1: Fetch the instruction from main memory into the processorStep 2: Fetch the operand at location MLOC from main memory into
the processor
Step 3: Add the memory operand (i.e. fetched contents of MLOC) tothe contents of register R0
Step 4: Store the resulting sum in R0 itself.
OPCODE OPERAND/S
Instruction
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Processor and Main Memory Interaction
The figure depicts processor and memory connection w.r.t.various components of a processor.
MAIN MEMORY
CONTROL
UNIT
ALU
Control Bus
MDR
R0(Accum)
R1
Rn-1
0 1 FLAGS15
Data Bus
G
P
Rs
MAR
PC
IR
CACHE
Address Bus
CPU
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Operational Steps Associated withProcessor & Main Memory Interaction
Consider the following figure:
MAIN MEMORY
MAR
PC
MDR
Address of an
Instruction
IR
Instruction
OP
CODE
DataOperand
Control ALU
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Performance
The total time required to execute an application program is the
most important measure of performance for a computer.
Performance is also affected by features like the compiler
design, machine language instruction set of the computer, the
hardware design of that computer
For a best performance, there must be co-ordination among
Compiler Design Instruction Set Computer Hardware.
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1. To increase speed of processing, a high-speed memory called acache memory is used to contain run time programs and frequentlyaccessed data values.
3.The cache memory is employed in computer systems to overcomethe mismatch in operating speeds of processor and main memory(slower access time).
CACHE
MEMORY
MAIN
MEMORYPROCESSOR
Performance
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The performance of a processor and hence operating speed of atodays desktop PCs and workstation computers is usuallyspecified as Clock rate viz Intel Celeraton processor @850 MHz(Mega Hertz), Intel Pentium PIV processor @ 2.4GHz (Giga Hertz)and so on..
The term cycles per second used to measure clock rate is termedas Hertz (Hz).
The Clock rate R can be given as R=1/P which is similar to f=1/Twhere in P or T is length or duration of timing signal called clock
period or simply clock cycle
The duration T or length P of one clock cycle plays a key role indetermining processor performance. The inverse of P or T is theclock rate R or f which is measured in cycles per second (frequencyor clock frequency)
Processor Clock
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In general, processor circuits in a PC are controlled by clock
generator IC (say 8284) which is coupled with a crystal (Crystal
Oscillator Circuit).
This clock generator defines uniform time intervals called clock
period or T-states. In order to execute a machine languageinstruction, usually 4 to 6 T-states or clock cycles are required
Usually 1 T-state or clock period refers to 1 micro second
duration , 1 nano second, etc. depending upon the processors
clock rate.
Processor Clock
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Let
T = Time required by the processor to execute a high levellanguage program.
N = Language translator might issue the number of machinelanguage instructions to execute the given source program.
S =Average number of basic states of actions (called microoperation / micro instructions) required to execute onemachine language instruction.
R= Clock rate for a given processor in cycles per second, thentotal execution time for a given source program is:
T = ( N * S ) / R
This is referred to as Basic Performance Equation. The executiontime T has to be minimized for better performance. For whichvalues ofN and S must be minimized and value ofR must beenhanced at the same time.
Basic Performance Equation
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Clock Rate
How do you enhance the clock rate R for a processor ?
Clock frequency of a processor can be improved in a straight forward
manner i.e. if and only if processors semiconductor (IC) fabrication
technology incorporates very high speed logic circuits. This gives abetter performance ratio by reducing clock period P for completing
basic steps of actions and thus increasing the clock rate R.
The other way to improve clock rate R is to minimize the amount
of work done in each and every basic step of action (microinstructions operation). This will reduce clock period P and enhances
R the clock rate.
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Performance Measurement
It is the time a computer require to execute a given benchmarkprogram.
Benchmark refers to standard task used to measure how well adevice or computer or processor operates.
To evaluate the performance of Computers, a non-profitorganization known as SPEC-System Performance EvaluationCorporation employs agreed-upon application programs of real worldfor benchmarks. Accordingly, it gives performance measure for acomputer as
Running time on a Reference Computer
Running time on a test ComputerSPEC Rating =
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A benchmark program from a suite of benchmark program will be
selected and compiled fortest computer.
The same benchmark program will be compiled and executed onone of the typical computer which be selected as a Reference
Computer
For instance, a SPEC rating 20 indicate that a test computer is 20
times faster than the chosen reference computer for a particularbenchmark program.
Performance Measurement
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Processor Organization
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Processor Organization
IAS components are : MDR or MBR (memory data register or memory
buffer register), MAR (memory address register), IR(instruction register), IBR (instruction buffer
register), PC (program counter), AC (accumulatorand MQ (multiplier quotient), memory (1000locations)
20 bit instruction : 8 bit op-code, 12 bit address(addressing one of 1000 memory locations - 0 to
999)
39 bit data (with sign bit - 1 bit)
Operations : data transfer between registers andALU, unconditional branch, conditional branch,
arithmetic, address modify
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Processor Organization
Consider a basicinstructionofa CPU :
ADD R1, R2
(AddcontentofregisterR1 andcontentofregisterR2, place resultinR1)
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Execution steps of ADDR1,R2
The possible micro-execution steps are :
a. ALU1n [R1] {content of R1 is moved to ALU1}
b. ALU2n [R2] {content of R2 is moved to ALU2}
c. ADD {content of ALU1 + ALU2= ALU3}
d. R1n [ALU3] {Result of add is moved to R1}
If each micro-step is executed in one clock-cycle, then this ADD instruction needs 4 clock-cycles
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Processor Organization
BUS
First Clock cycle
A
LU1 [R1]
ALU1 ALU2
ALU3
ADDER
R1
R2
R3
Control
Unit
PC
MBR
MAR
To/from
memory
IR
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Processor Organization
To/from
memory
ALU1 ALU2
ALU3
ADDER
BUS
R1
R2
R3
Second Clock cycle
ALU2 [R2]
Control
Unit
PC
MBR
MAR
IR
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Processor Organization
ALU1 ALU2
ALU3
ADDER
BUS
R1
R2
R3
Third Clock cycle
ADD
Control
Unit
PC
MBR
MAR
To/from
memory
IR
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Processor Organization
ALU1 ALU2
ALU3
ADDER
BUS
R1
R2
R3
Clock cycle Four
R1 [ALU3]
Control
Unit
PC
MBR
MAR
To/from
memory
IR
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Analysis of Instruction Cycle
With single bus, it is slow, since in eachclock only one transfer could be executed
Is there any other way to improve thespeed?
Dual bus processor may be faster
Additional processor cost
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Dual processor-bus : A way to improve speed
ALU1 ALU2
ALU3
ADDER
DUAL BUS
R1
R2
R3
Only 3 clocks
cycles needed,
25% faster
1 2
1. ALU1n [R1] (bus1)
ALU2n [R2] (bus2)
2. ADD
3. R1n [ALU3] (bus1)
Other components(Control Unit, IR,PC,
MAR,MBR)
1. ALU1n [R1] (bus1)
ALU2n [R2] (bus2)
ADD
2. R1n [ALU3] (bus1)
Any other possibility
Only 2 clocks
cycles needed,
50% faster
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To provide synchronization and to compensate for different speeds
of data transfer on a bus, slow speed peripheral devices are equipped
with a buffer register.
A buffer register holds data temporarily. Buffer register
compensate the timing differences among processor, memory and
slow speed peripherals like Printer, Key-board, magnetic tape etc.,
during the transfers over a common communication path i.e., single
bus.
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Example Register Organization
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Registers
CPU must have some working space (temporarystorage) Called registers
Number and function vary between processordesigns One of the major design decisions Top
level of memory hierarchy
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UserVisible Registers
General Purpose Data
Address
Condition Codes
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General Purpose Registers (1)
May be true general purpose May be restricted
May be used for data or addressing
Data
Accumulator
Addressing
Segment
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How ManyGP Registers?
Between 8 - 32
Fewer = more memory references
More does not reduce memory references andtakes up processor real estate
See also RISC
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How big?
Large enough to hold full address
Large enough to hold full word
Often possible to combine two data registers
C programming
double int a;long int a;
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Condition Code Registers
Sets of individual bits
e.g. result of last operation was zero
Can be read (implicitly) by programs
e.g. Jump if zero
Can not (usually) be set by programs
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Control & Status Registers
Program Counter
Instruction Decoding Register
Memory Address Register
Memory Buffer Register
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Program Status Word
A set of bits Includes Condition Codes
Sign of last result
Zero
Carry
Equal
Overflow
Interrupt enable/disable
Supervisor
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Instruction and Instruction Sequencing
An instruction is a command to the processor to perform a given
task on data operands.
A program is a set of instructions that specify operations, operands
& the sequence by which processing has to occur. Thus operation of a computer is controlled by stored program
In general a computer must support 4 categories of operations:
1. Data Movement : To conduct I/O transfers
2. Data Storage : Across Memory and processor registers.
3. Data Processing : Arithmetic and logical operations
4. Program sequencing and control : Test and Branch.
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Data operands & Instructions are situated in main memory locations
& processor registers.
Like mnemonics for Op-codes, Symbolic names or label identifiers
are used to name or identify such locations.
For instances memory location names include M, LOC, A, B, C,
SUM, N1, VAR1, VAR2, NUM1, etc.,
Similarly processor register names include R0, R1, R2, R3, R4, R5,
etc., and registers of I/O subsystem may be designated as DATAIN,
DATAOUT etc.
Register Transfer Notation
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While depicting operations, the contents of a memory location or aregister are denoted by placing the corresponding name in apair of
square brackets.
For instance : R0 [M]
Suggests to copy contents of memory location
M to registerR0
The corresponding instruction is MOVE M, R0,
Similarly : MOVE R1, SUM Suggests : SUM [R1]
The instruction : MOVE B, LOC Means : LOC [B]
Memory LocationRegister
RegisterMemory Location
Register Transfer Notation
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ConsiderR1 [R1] + [R3]
Equivalent Assembly Language instruction is Add R3, R1.
Here the operation Code Mnemonic is Add
Register Locations
R1,R3
represent operand fields
Similarly, in the instruction ADD R1, SUM
i.e. SUM [SUM] + [R1]
Opcode
Register OperandMemory Operand
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Three Address Instruction Two Address Instruction
One Address Instruction
Zero Address Instruction
Three Address InstructionSuppose we would like to use a single machine instruction to
perform the following addition operation:
S [P] + [Q]
We will have to use a three address instruction to carry
out addition and to store the sum in a third variable S.
Then three address instruction to perform addition is:
Add P, Q, S
Basic Instruction Types
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General form of three address instruction
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Two Address Instruction
Two address instruction general format:
Example of two address instruction Add P, Q
To perform operation of addition as : Q [P] + [Q]
Destination Operand Source Operand/s
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Here one of the operand i.e. destination operand Q acts as sourceas well as destination.
To perform S [P] + [Q]
Use two address instructions sequence: MOVE Q, S
ADD P, S
Two Address Instruction
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Stack organized computer make use of a special memory
structure called push down stack to store operands. In such
computer machines it is possible to use instructions that containonly operation codes and no explicit operands.
The name Zero address specifies the absence of an address field
of operands in machine instructions.
Example of Zero address instruction: NOP in 8085
Zero Address Instruction
Instruction Execution & Straight line
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To perform operation of addition as S (P + Q)
We shall rewrite instructions to perform S [P] + [Q] as:
Move P, R0 ; R0 [P]
Add Q, R0 ; R0 [R0] + [Q]
Move R0, S ; S [R0]
Instructions of a given program are fetched one at a time in the
increasing order of their memory addresses.
This kind of instruction fetching in sequence (one at a time for
execution ) is known as straight line sequencing
Instruction execution can be carried out as two step process viz.
# Instruction Fetch cycle.
# Instruction Execute cycle.
Instruction Execution & Straight line
sequencing
Instruction Execution & Straight line
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g
sequencing
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The data conditions or status, after an arithmetic or logical
operation are indicated by setting or clearing the flip flops called
flags orcondition codes.
Each flip-flop holding a data condition code is a one bit storage
cell (logic circuit) that can be set to a 1 or reset to 0 value.
These condition codes are set/reset as a result of arithmetic and
logical operations in the ALU.
Condition code bits or flag bits are accommodated in a groups of
4 bit, 8 bit or 16 bit flag register or a status register in CPU.
Condition Codes
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Many of the processors include the following four flags:Z - Zero flag bit is set to 1 if the result is 0;
N - Negative flag bit is set to 1 if the result is negative;
C - Carry flag bit is set to 1 if result generates a carry bit
V - Overflow flag bit is set to 1 if arithmetic overflow occurs
Pentium processormakes use of following condition codes:
C (carry flag)
P (parity flag)
A(
Auxiliary carry flag)Z (zero flag)
S (sign flag)
O (over flow flag)
Condition Codes
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The addressing mode specifies a rule or method for interpreting or
modifying the address field of the instruction before the operand is
actually accessed for manipulation.
Itis concerned with the different ways in which the location of an
operand can be specified in a given instruction.
Various schemes for specifying addresses of operands in an
instruction have been introduced. Such schemes are collectively
known as Addressing Modes.
What are Addressing Modes . . . ?
OPCODE OPERAND/S
Instruction Format Address field
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Addressing Modes:
Immediate mode
Register mode
Absolute (Direct) mode
Indirect mode
Indexed mode
Relative mode
Auto increment mode
Auto decrement mode
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Here the operand is specified in the instruction itself. An
instruction that follows immediate mode has an operand field
rather than an address field.
Immediate Addressing mode
For example:
Move 50immediate, R0
A common convention say, a pound symbol # has to precede the
value of an immediate operand
Move #50, R0
50
R2
R1
R0
R i t Add i M d
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RegisterAddressing Mode
In this scheme, name of the register (address code of a specificgeneral purpose register) appears in the address field of an
instruction Example: Move R1, R2
Register Addressing Mode
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Advantages of this scheme :
No memory reference
A few bit address to indicate register location
Speedy execution since register is inside the processor& has low access time.
Disadvantages of this scheme :
Limited address space as number of registers are lessin many of the processors.
RegisterAddressing Mode
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Here operand resides in Memory and its address is given explicitlyin the address field of an instruction. This scheme need only one
memory reference in addition to instruction fetch cycle and no further
calculation is required to compute operand address.
Direct Addressing Mode /Absolute Mode
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Direct addressing scheme is simple to use and easy to implementwithout the requirement for additional hardware.
Examples
Move P, R0
Move R0, S
Add Q, R0
Add P, Q
Load P
Store S
Direct Addressing Mode /Absolute Mode
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Indirect Addressing Mode
Here, the address field of an instruction gives the address of
a memory word in which effective address or actual address
of the operand is found.
By referring to this address (EA), the required operand
can be fetched from memory.
Example: Add (A), R0 i.e. EA = (A) i.e. contents ofA is B
HereB
is effective address of desired operand in memoryAddress of (A) address of (B) memory location is the desired
operand (say 50).
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Indirect Addressing Mode
Register Indirect Addressing Mode
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Here, instruction specifies a register in the CPU whose contentsgive the effective address of the operand in Memory.
For example Add (R1), R0 i.e. EA = (R1) i.e. contents ofR1
is B
Register Indirect Addressing Mode
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The advantage of Register Indirect Addressing:
It uses one less memory reference (memory read operation)
Address field of the instruction uses a fewer bits to
specify a register
Register indirect addressing can be specified withEffective Address EA = (R) i.e. B
Advantages of Indirect addressing:
a wider address range to refer to a large number of
memory locations.
Disadvantage of Indirect addressing:
3 or more memory references (memory read operations)
required to fetch the desired operand in memory.
Indexed Addressing Mode
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Indexed Addressing Mode
Here, effective address of the operand is generated
by adding a constant value to the contents of a register.
This constant value may be either an offset value called
displacementorbeginning address of data/operand array
in main memory (Base). Indexed addressing mode is symbolically represented as
X(R)
&Here X denote a constant and R is name of the registerinvolved in Indexing.
Effective address EA of the operand is given asEA = X + [R]
&Contents of index register are not changed during theprocess of address generation.
Indexed Addressing Mode
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Indexed Addressing Mode
A = 1040 = X; constant X corresponds to a memory location(R) = 20 i.e. Index oroffset value
EA = A + (R) = 1040 + 20
EA = 1060 at which you will find desired operand 50
Indexed Addressing Mode
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You can use indexed addressing mode in two waysI) A constant value X defines here beginning address of
operand in memory and index register Ri contains offset value
(Displacement)
& For example 1040 in the following instruction:Add 1040 (R1), R2 X=1040 R1=20 offset
II) A constant value X defines an offset and index register Ri
contains beginning address of operand in memory.
& For example 20 in the following instruction:
Add 20(R1), R2 X=20 R1=1040
Indexed Addressing Mode
I d d Add i M d
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Advantages of Index mode
is the flexibility it offers to access relative memory locations
Disadvantages of Index mode
* Is the complexity of computing effective address.
* The instruction requires to have two address fields
at least one of which is an explicit number.
Indexed Addressing Mode
Relative Addressing Mode
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Relative Addressing Mode
This scheme supplies the relative position of the memory
operand to be located.
Its like index mode only but program counter register PC
substitutes for base address contents
Relative Mode specify Effective Address by a notation:
X(PC)
Effective address is EA = [ PC ] + X
Branch > 0 loop Here jump value / displacement X
Auto Increment Mode
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Here contents of a register specified in the instruction are
incremented to denote effective address of next operand in
successive memory location.
After accessing the operand, the contents of this register are
incremented again automatically to point to the next operand
in contiguous memory locations.
Notation forAuto Increment Mode: (Ri) +
For example: Add (R2) +, R0 Use ofAuto Increment mode instruction eliminates the use of
explicit increment instruction
Auto Increment Mode
Auto Decrement Mode
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Auto Decrement Mode
Here, content of a register specified in the instruction is
decremented to denote effective address of next operand in
successive memory location.
Notation forAuto Decrement Mode: - (Ri)
For instance
Add (R2), R0
It allows accessing of operands in decreasing order of
memory address..
Add i M d
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Advantages of Addressing modes :
To be able to reference large number of memory location in main
memory or for some system in virtual memory.
To reduce number of bits in the address field of an instruction
To extend programming convenience to the user / programmer by
providing such facilities as indexing of set of data values, counters
for loop control, pointers to memory locations
Addressing Modes
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End of first half part ofUnit No. 1