Hp Decoder(24,38)
7
EXPERIMENT 7 AIM - design synthesize and stimulate 2*4 and 3*8 decoder ACTIVITY 1 - 2*4 DECODER :- VHDL CODE :- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity hp_deco_24 is Port ( X,Y : in STD_LOGIC; O : out STD_LOGIC_vector(3 downto 0)); end hp_deco_24; architecture Behavioral of hp_deco_24 is begin O(3) <= (not X) and (not Y); O(2) <= (not X) and Y; O(1) <= X and (not Y); O(0) <= X and Y; end Behavioral; TEST BENCH CODE :- -- Create Date: 00:44:14 04/14/2015 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY hp_deco24_tb IS END hp_deco24_tb; ARCHITECTURE behavior OF hp_deco24_tb IS
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Transcript of Hp Decoder(24,38)
EXPERIMENT 7AIM - design synthesize and stimulate 2*4 and 3*8 decoderACTIVITY 1 -2*4 DECODER :-VHDL CODE :-library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity hp_deco_24 is Port ( X,Y : in STD_LOGIC; O : out STD_LOGIC_vector(3 downto 0));end hp_deco_24;architecture Behavioral of hp_deco_24 isbegin O(3)
