How to implement a DALI-2 Transceiver using Core Independent...

TB3201How to Implement a DALI-2 Transceiver Using

Core Independent Peripherals

Introduction

Authors: Alin Stoicescu, Victor Berzan, Microchip Technology Inc.

This technical brief gives a solution for a Manchester code transceiver. It is implemented in DigitalAddressable Lighting Interface (DALI-2) systems, in which it serves as an encoder and decoder for datatransmission on the physical layer. The transceiver is implemented using PIC16F1779, a MicrocontrollerUnit (MCU) with several Core Independent Peripherals (CIPs). These peripherals can be used to performan important part of the tasks in hardware, thus reducing the Central Processing Unit (CPU) load andobtaining a faster response.

The solution presented here is applicable to any other 8-bit PIC® microcontroller that offers the sameminimal set of CIPs. DALI-2 is an IEC standard (known as IEC62386).

This document describes the modulation implementation in hardware and the data transmission bysoftware encapsulation. For a proper understanding of the process, the technical brief also covers thefollowing:

• Manchester Coding Convention• DALI-2 Forward and Backward Frames• Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART), Configurable

Logic Cell (CLC) and Timer (TMR) Functionality• EUSART, TMR and CLC Merged Solution for Manchester Encoder• EUSART and TMR with Hardware Limit Timer (HLT) Merged Solution for Manchester Decoder

© 2018 Microchip Technology Inc. DS90003201A-page 1

Table of Contents

Introduction......................................................................................................................1

1. Manchester Coding Convention................................................................................ 3

2. DALI-2 Frames.......................................................................................................... 4

3. Hardware Description................................................................................................ 53.1. Encoder Hardware Description.................................................................................................... 53.2. Decoder Hardware Description.................................................................................................... 5

4. MCC Configuration.................................................................................................... 8

5. Demo Implementation............................................................................................. 165.1. DALI-2 Transmitter Demo Implementation.................................................................................165.2. DALI-2 Receiver Demo Implementation.....................................................................................17

6. Conclusion...............................................................................................................20

The Microchip Web Site................................................................................................ 21

Customer Change Notification Service..........................................................................21

Customer Support......................................................................................................... 21

Microchip Devices Code Protection Feature................................................................. 21

Legal Notice...................................................................................................................22

Trademarks................................................................................................................... 22

Quality Management System Certified by DNV.............................................................23

Worldwide Sales and Service........................................................................................24

TB3201


1. Manchester Coding ConventionManchester coding uses logic transitions from ‘0’ to ‘1’ or from ‘1’ to ‘0’ for representing the ‘0’ and ‘1’bits. There are two coding conventions, presented in the figure below:

Figure 1-1. Manchester Coding Convention

Clock

Data

Manchester(IEEE 802.3)

0 1 0 0 1 1 0 1

DALI-2 standard uses IEEE 802.3 Manchester convention. This document presents the systemcomposed of PIC16F1779 and DALI-2 click board. This DALI-2 click board uses inverting thermocouples;therefore, the microcontroller implements the inverted Manchester convention.

Figure 1-2. PIC16F1779 and DALI-2 Click Board DALI-2 System

PIC16F1779DALI-2Click

DALI-2Click PIC16F1779

IEEE 802.3

DALI-2 Bus

TB3201Manchester Coding Convention


2. DALI-2 FramesDALI-2 is a protocol used for digital lighting control. The DALI-2 communication system is usuallydeployed as a network composed of master or control devices and several slaves or control gears. Thecommunication between devices is wired and is based on a Manchester coding.

All DALI-2 devices in the network are connected using a 2-wire connection line, carrying power and data.The devices exchange data with a baud rate of 1200.

• The data is Manchester encoded using a hardware EUSART and CLC configuration, while theinformation is packed as a DALI-2 frame using few software adjustments.

• The data is decoded using the same EUSART, with a sampling rate twice the DALI-2 baud rate inorder to sample both bit halves for each Manchester encoded bit.

The DALI-2 wire consists of digital data coded using the IEEE 802.3 approach, and the information ispacked as a frame. When there is no data exchange over the wire, meaning it is in an Idle state, the lineis kept High. The start of the frame is represented by a Start bit, is followed by the payload, and the frameends with two Stop bits represented by the line left in Idle or High (Figure 2-1).

Figure 2-1. DALI-2 Frame

MSB LSB

First ByteStart

MSB LSB

Last Byte Stop

The payload can be:

• One byte, if the frame is a backward frame: data sent as a reply to a previous received frame• Two bytes, if the frame is a forward frame: the first byte represents the address of the recipient, and

is followed by the opcode byte

Figure 2-2 and Figure 2-3 describe a DALI-2 frame created or received by a microcontroller. As shownhere, the DALI-2 frame starts with a ‘1’ followed by a ‘0’ during the first clock period, being the equivalentof a logic ‘1’, which represents the Start bit. It is followed by two bytes of data for the forward frame (0x26and 0x24 in Figure 2-2) or it is followed by a byte of data for the backward frame (0x26 in Figure 2-3).After the end of the clock generation, the line is left in an Idle state.

Figure 2-2. Forward Frame

Figure 2-3. Backward Frame

TB3201DALI-2 Frames


3. Hardware Description

3.1 Encoder Hardware DescriptionThe hardware requirements and configurations were made for a PIC16F1779, attached on a CuriosityHigh Pin Count (HPC) development board and using a DALI-2 click board from MikroElektronika, whichinverts the logical levels of the signal between the microcontroller and the DALI-2 wire.

3.1.1 EUSART Description

Since the Manchester code is mainly based on transitions of the logic level of the communication line, theeasiest way to encode data for this type of modulation is using a clock. The information will berepresented by a clock pulse or by an inverted clock pulse. Sending a logic ‘1’ can be implemented bytransmitting the clock period to the DALI-2 bus, while sending a logic ‘0’ can be implemented bytransmitting the inverted clock period to the DALI-2 bus.

For synchronization reasons, a peripheral that can generate its own clock is recommended: EUSART,SPI, etc. Since the DALI-2 frame might involve more than one byte of information, a peripheral that cancontinuously exchange data will be required, and so an Enhanced Universal Synchronous AsynchronousReceiver Transmitter (EUSART) was used.

The EUSART is configured in Synchronous mode so it can generate its own clock with a baud rate of1200. The clock is configured as non-inverted, meaning that the line is low in Idle state and the clockstarts in logic ‘1’. The DALI-2 frame begins with a Start bit and is followed by one or more bytes, resultingin at least nine bits per frame. Thus, the EUSART must be initially configured in a 9-bit mode andreconfigured in 8-bit mode after the first byte, if the frame is not a backward frame and there is moreinformation to transmit.

3.1.2 CLC Description

The Configurable Logic Cell (CLC) is utilized to control the type of clock (non-inverted or inverted) that willbe used in constructing the encoder. The decision is taken by implementing a logic XOR gate which getsinputs from the CLK and from the inverted DATA of the EUSART and outputs the DALI-2 frame.

In the case of a non-inverted clock, which starts in logic ‘1’, by writing a logic ‘0’ the XOR gate will outputan ‘1’ followed by a ‘0’ during the period of the clock, with the new data having a period two times smallerthan the one of the clock.

3.2 Decoder Hardware DescriptionA forward frame (Start bit + 0xFE02 + Stop bits) received by the MCU is presented in the figure below:

Figure 3-1. DALI-2 Frame, Received by MCU

TB3201Hardware Description


The DALI-2 bus has a data rate of 1200 bits/s. The EUSART is used to sample both halves for each bit,so its sample (baud) rate is set to 2400. The sample period, TE = 1s/2400 = 416 μs. The EUSARTreading must be synchronized with the DALI-2 frame Data bits.

TMR8 is used for detecting the Start and Stop bits of the DALI frame. The timer has the Hardware LimitTimer (HLT) capability – a feature that allows the timer to be started or reset by an external event usingthe External Reset (TMRx_ers) pin. The mode is configured by setting the corresponding value in theT8HLTbits.MODE field. (See PIC16(L)F1777/8/9 Data Sheet for details).

Initially, the HLT mode is configured to start the timer on the falling edge of the External Reset(TMRx_ers) pin, and the timer is configured to overflow in TE/2 = 208 μs. The first falling edge occurs atthe middle of the Start bit, triggering the timer, which generates the interrupt after 208 μs.

Figure 3-2. DALI-2 Frame Start Detection

Start bitTimer Start (using HLT)

208 μs

EUSART Start Reading

Interrupt

Samples

208 μs 208 μs

In the ISR, the EUSART continuous receive is started. The EUSART is configured as a synchronousmaster, with a baud rate of 2400, which is twice the data rate of the Manchester signal. In thisconfiguration, the EUSART will sample both halves of each Manchester encoded Data bit. On theEUSART Receive ISR, the received data is stored in a buffer.

Also during the timer ISR, the timer is configured to detect the Stop condition. The HLT is configured toreset the timer for each signal edge. The timer is configured to overflow in 2.4 ms and then it is started. Ifthere is no edge for 2.4 ms, it means that the Stop condition occurred and the end of frame was reached.The timer will generate the interrupt.

Figure 3-3. DALI-2 Frame End Detection

Last edge

EUSART Stop Reading

TMR8 Interrupt2.4 ms

No EUSART ISR(EUSART was stopped)Last byte (discarded)

In the timer ISR, the EUSART is stopped, the timer is reconfigured for start detection, and the receiveddata is processed. Signal error checking is performed, then the data is decoded to obtain the actual bytesand the callback function is called.



http://ww1.microchip.com/downloads/en/DeviceDoc/40001819B.pdf

Figure 3-4. Automatic Baud Control

Samples

T

416 μs

HPTHLP

In order to correctly receive the frames, the EUSART baud rate must be equal to the baud rate of thereceived signal. When using the internal oscillator, the clock frequency of the PIC may drift, thus affectingthe generated baud rate. An automatic baud control mechanism is implemented to compensate for thatfrequency drift.

It uses two timers: TMR5 for measuring the width of the first high pulse, and TMR1 for measuring the totalwidth of the first high + low pulses. The two measurements are needed to get an accurate result. Themeasured width of the high pulse is smaller than TE, due to the sluggish rising edge, but that differenceadds up to the end of the low pulse, so the total width will be exactly a multiple of TE. The low pulseconsists of one or two half bits, depending if the first bit (after the Start bit) is a ‘1’, or a ‘0’.The width of the low pulse is compared against 1.5 times the width of the high pulse, to decide whetherthe total (high + low) width must be divided by 2 or by 3, in order to get the actual TE. The computation ismade after the frame end detection, and then the EUSART baud rate is adjusted to 1/TE for the nextframe.

The TMR5 is set to count only during the first high pulse, by enabling the Gate Single-Pulse mode, withGate Polarity high, and Gate Signal Source to the RX pin. The TMR1 is configured similarly, but also withGate Toggle enabled, so it counts during the first high + low pulses. This automatic baud control wassuccessfully tested for a transmitter data rate variation of -50% to +100%, with a fixed receiver clockfrequency, and for a receiver clock frequency variation of -50% to +100%, with a fixed transmitter datarate (1200 bits/s).



4. MCC ConfigurationThe MCC configuration was made for PIC16F1779 and Curiosity HPC development board, but thetransceiver solution can be implemented on any 8-bit MCU that has a CLC, an EUSART, a TMR with HLTand two TMRs with gate control. The configuration is based on a system clock of 4 MHz. All the requiredperipherals are available for configuration in MCC.

The tools versions used are:• MPLAB X IDE v4.15• XC8 v1.45• MCC Plugin v3.55.1• MCC Core v4.45• MCC 8-bit Library v1.65.2

These are the configuration steps:

1. Start MPLAB X and create a new project for PIC16F1779.2. Open MCC.3. In System Module, change internal clock to 4MHz_HF and disable PLL by unchecking PLL

Enabled checkbox.Figure 4-1. System Module

4. From Device Resources → Peripherals shown in Figure 4-2, select a CLC, an EUSART and threeTimer modules.

TB3201MCC Configuration


Figure 4-2. Peripherals Selection

5. The CLC must act like an XOR gate, with its input signals coming from EUSART, as shown in Figure 4-3; the demo is using CLC4:

– Enable CLC → uncheck box– Mode → OR-XOR– Configure the first signal to be the Clock (CK) channel from the EUSART module, and enable

the connection to the first or the second gate– Configure another signal to be the Data (DT) channel from the EUSART module, and enable

the connection to the third or the fourth gate– Negate the Data signal by pressing on the top of the gate to which it was assigned



Figure 4-3. CLC4 Configurations

6. The EUSART must be configured as synchronous and with a baud rate of 1200, as indicated in Figure 4-4, to satisfy the DALI-2 requirements, and also the EUSART interrupts must be enabled:

– Mode → Synchronous– Sync Mode → master– Baud Rate → 1200– Enable EUSART Interrupts → Check



Figure 4-4. EUSART Configuration

7. A Timer was used to generate an interrupt after the end of the transmission, leaving thecommunication channel into an Idle state. The demo is using TMR8 and the configuration isillustrated in Figure 4-5:

– Enable Timer → uncheck box– Clock Source → FOSC/4– Postscaler → 1:1– Prescaler → 1:32– Timer Period → 416 μs– Enable Timer Interrupt → check box– Callback Function Rate → 416 μs



Figure 4-5. TMR8 Configuration

Note: TMR8 is also used by the decoder, which will modify the prescaler and Period values.There is no problem, since the decoder and the encoder will never be both active at the same time.When disabled, the decoder will revert the Period to the value set in MCC. The encoder will set theprescaler back to 1:32 when needed.

8. Additionally, the decoder uses two timers with gate control for measuring the actual baud rate ofthe received signal and adjust the EUSART baud rate accordingly. The demo is using TMR1 andTMR5 for this, and the configurations are illustrated in Figure 4-6, respectively Figure 4-7:

– Enable Synchronization → uncheck box– Enable Gate → check box– Enable Gate Toggle → check box (just for TMR1)– Enable Gate Single-Pulse mode → check box– Gate Polarity → high



9. In Pin Manager from Figure 4-8, the user must select the CLC module output pin, buttons inputpins, EUSART DT pin, LEDs output pins, TMR1 and TMR5 gate pins and TMR8 input pin:

– CLC4OUT → output on Port RD0; disable Analog– EUSART DT → connect to Port RB5– Pin Module → input Port RB4; rename the pin to S1; enable Weak Pull-Up– Pin Module → input Port RC5; rename the pin to S2; enable Weak Pull-Up– Pin Module → output Port RA4; rename the pin to LED_D2; disable Analog– Pin Module → output Port RA5; rename the pin to LED_D3; disable Analog– Pin Module → output Port RA6; rename the pin to LED_D4– Pin Module → output Port RA7; rename the pin to LED_D5– TMR1 T1G → input from Port RB5– TMR5 T5G → input from Port RB5– TMR8 T8IN → input from Port RB5



Figure 4-8. Pin Manager Configurations

10. The configurations for Manchester transceiver were made, so the Generate button can be pressed.



5. Demo ImplementationThe current applications present the capability to send and receive DALI-2 frames and were created forPIC16F1779.

In the encoder demo application, the user can send DALI-2 frames by pushing the on-board buttons. TheS1 button will send a forward frame, while the S2 button will send a backward frame.

In the decoder demo application, the three Least Significant bits of the first byte of the received frame aredisplayed on three LEDs, and the Error flag is displayed on the fourth LED.

5.1 DALI-2 Transmitter Demo ImplementationThe functionality of the code is briefly described in Figure 5-1. After the hardware configurationsmentioned in the previous chapter through the MCC selection steps, the demo application counts everypush of the button, stores the value in a byte and will further send DALI-2 frames. In case of the frameswith more than one byte of data, the first one will contain the counted value and the others will be filledwith zeros.

Figure 5-1. Demo Workflow

Start

initialize

while (1)

End

while (1)

Is button 1 pressed?

Is button 2 pressed?

Wait for button release

Increment counter 1

Wait for button release

Increment counter 2

No

No

Yes

Yes

Send forward frame

Reset counter values

Send backwardframe

Hardware

Interruptenable

1. For a DALI frame implementation, the user must add the manchester_encoder.c andmanchester_encoder.h files to the project. These files implement the DALI-2 frametransmissions providing ‘DALI_Send_Frame(block_of_bytes, number_of_bytes)’ function,which takes as a first argument a block of bytes representing the data of the frame, and as asecond argument, the number of bytes. In conclusion, both forward and backward frames can besent by calling the same function but with a different number for the second argument (1 forbackward and 2 for forward).

TB3201Demo Implementation


Note: The function will activate the 9-bit transmission option of the EUSART for the first byte ofthe frame, will deactivate it once it is done, and will change the endianness of every byte to MSB-LSB to comply with DALI-2 requirements. More details can be found in the following figure.

Figure 5-2. API’s Workflow

DALI_Send_Frame

Number of bytes > 3

For each byte

Is the first byte?

Enable 9-bit

transmit

Write on EUSART

Start Timer

Timer Interrupt

CLC Disable

End

No

Yes

No

Done

Yes

YesStop Timer EUSART

Transmit EnableEUSART

Set Line HIGH CLC Enable

Set 9th bit Shift data and include Start bit

EUSART Transmit wait

Disable 9-bit

transmit

EUSART Transmit wait

Disable 9-bit

transmit

Configure Timer

EUSARTTransmit Disable

Stop Timer

Change the

endiannessdata

Change thedata

endianness

2. In ‘main()’, after the initializing procedures, the user must enable the global and peripheralinterrupts required by TMR8.

3. In ‘while (1)’, the state of the buttons is checked and, if a button is clicked, the respectivecounter is incremented and a DALI-2 frame is sent.

5.2 DALI-2 Receiver Demo ImplementationThe functionality of the code is briefly described in demo workflow. The demo application detects the startof the frame using TMR8, then reads one or more bytes of data using the EUSART, then detects theframe stop, using the same TMR8, but with different configuration. After detecting the frame stop, thereceived data is processed, signal error checking is performed, then the data is decoded and the callbackfunction is called.



Figure 5-3. Demo Workflow

Configure one shot timer (SFD)T = Te/2 (208 µs)

With HLT mode to start on falling edge

Start EUSART continuous receive(synchronous, master, CLK not used,

baud 2400)

Read data &append to buffer

Start Frame Detection

Buffer data contains errors?

Call error handler

Yes

Call receive handler

No

SFD Timer Interrupt

EUSART Receive Interrupt

EFD Timer Interrupt

Stop timer

Stop EUSARTcontinuous receive

Start Frame Detection

Start Baud Rate

Clear the Timers T_HP and T_HLP,Start Single Pulse Acquisition (T_HP will measure the first high pulse, T_HLP will

measure the first high + low pulses)

Read the Timers T_HP and T_HLP,Compute Baud Rate,

Update EUSART Baud Rate

Start Baud Rate

DetectionMechanism

DetectionMechanism

Configure & start timer (EFD)T = 2.4 ms

With HLT mode to reset timer on any edge

For a DALI-2 Receiver implementation, the user must add the manchester_decoder.c and themanchester_decoder.h files to the project. These files give the possibility of DALI-2 frame reception.



Figure 5-4. API's Workflow

Start

Hardware Initialize

Interrupt Enable

while (1)

End

Set receive handler, set error handler

Receive handler

Display three

Error handler

Light D5 LED

S1 Pressed

Clear D5 LEDleast significantbits on LEDs

Start frame detection,start baud rate

detection mechanism

The API allows the user to set the callback functions for error handling:‘manchester_decoderSetErrHandler(onSignalError);’ and for received data handling:‘manchester_decoderSetReceiveHandler(onReceived);’. After those two being set, the decodercan be started using ’manchester_decoderEnable();’, and stoppedusing ’manchester_decoderDisable();’.



6. ConclusionThis technical brief describes one possible implementation of a DALI-2 frame handling based onManchester encoding/decoding and offers network connectivity in DALI-2 systems. The Tx demo sendsframes, containing a counter value for each button press, and the Rx demo displays three bits of thereceived counter value on three LEDs, and the Error flag on the fourth LED. The clock speed required forthe transceiver to work goes down to 4 MHz, which is much less than the maximum 32 MHz supported bythe PIC16F1779, thus reducing the power consumption.

TB3201Conclusion


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TB3201


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TB3201


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IntroductionTable of Contents1. Manchester Coding Convention2. DALI-2 Frames3. Hardware Description3.1. Encoder Hardware Description3.1.1. EUSART Description3.1.2. CLC Description

3.2. Decoder Hardware Description

4. MCC Configuration5. Demo Implementation5.1. DALI-2 Transmitter Demo Implementation5.2. DALI-2 Receiver Demo Implementation

6. ConclusionThe Microchip Web SiteCustomer Change Notification ServiceCustomer SupportMicrochip Devices Code Protection FeatureLegal NoticeTrademarksQuality Management System Certified by DNVWorldwide Sales and Service

How to implement a DALI-2 Transceiver using Core Independent...

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