Xilinx Template (light) rev

How to Create Area Constraints with PlanAheadXilinx TrainingObjectivesAfter completing this module, you will be able to:Add Pblocks to your design with the Hierarchy viewer, Schematic viewer, and the Timing Report generator

PblocksPblocks are used to group logicAssignment of a Pblock to a range of locations on the die makes it an area constraintWhen starting to floorplan, the intent is to minimize the routing between PblocksA single Pblock should not occupy over 20 percent of the design resourcesIf so, try to make two Pblocks from logic at a lower level

UCF SyntaxPblocks are used to group logicPblocks form a groupINST "usbEngine1" AREA_GROUP = "pblock_usbEngine1";Area constraints form a range constraintAREA_GROUP "pblock_usbEngine1 RANGE=SLICE_X0Y60:SLICE_X43Y119;

AREA_GROUP (Area Group) is a design implementation constraint that enables partitioning of the design into physical regions for mapping, packing, placement, and routing.1. AREA_GROUP is attached to logical blocks in the design, and the string value of the constraint identifies a named group of logical blocks that are to be packed together by mapper and placed in the ranges if specified by PAR. If AREA_GROUP is attached to a hierarchical block, all sub-blocks in the block are assigned to the group. Once defined, an AREA_GROUP can have a variety of additional constraints associated with it to control its implementation.

2. RANGE defines the range of device resources that are available to place logic contained in the AREA_GROUP, in the same manner ranges are defined for the LOC constraint.

Making a PblockTo create a Pblock Select a level of hierarchy or a component from the Netlist window and use the popup menu > New Pblock Select a block from the Hierarchy viewer and use the popup menu > New Pblock commandFrom a timing report, use the popup menu > New Pblock command

1. The first thing you need is to select a level of hierarchy or a component from the Netlist window. Right Click and select the New Pblock command in the pop up menu as shown in the screen shot here.2. To create a new Pblock, select a block from the Hierarchy viewer and use the popup menu > New Pblock command.3. or from a timing report, use the popup menu > New Pblock command.The New Pblock command creates a new Pblock in the Physical Constraints view, but does not create a rectangle in the Device view. You must pre-select logic for assignment to the new Pblock. If no logic is pre-selected, the command creates an empty Pblock. To create new Pblocks with or without pre-selected logic, select New Pblock from the popup menu.Auto-create PblockFrom the horizontal toolbar use the Tools > Auto-create Pblocks commandIf more modules exist than the total number of Pblocks specified, it will create Pblocks for the largest modules

PlanAhead enables automatic Pblock placement using the Auto-create Pblocks command. This method is used primarily to create top-level Pblocks to view the data flow of the design and to understand the relative size and relationship between the various logic modules in the design. Normally, the designer has some concept of the critical modules and circuitry in the design and begins floorplanning with those modules.1. To run Auto-create Pblocks command, from the horizontal toolbar use the Tools>Auto-create Pblocks command. In the dialog box, review the options with which you can define the maximum number of Pblocks to create and specify the minimum Pblock size.2. If more modules exist than the total number of Pblocks specified, it will create Pblocks for the largest modules.

Device ViewerCreate or view Pblocks easily using the Device viewer.The vertical toolbar has the following controlsShow/Hide I/O Nets Show/Hide Bundle NetsShow/Hide Loc ConstraintsShow connections for selected instancesDraw Pblock

The Device viewer gives a graphical diplay of your designs floorplan with the resources used on the FPGA. You can easily create Pblocks by selecting a portion on the FPGA. The vertical toolbar provides you with different options with which you can draw aPlblock and control the net connectivity views and LOC constraints.

Pblock PropertiesAfter selecting a Pblock use the popup menu > Pblock Properties command Shows device utilization of PblockCLBBlock RAMDSP sliceNumber of clocksBest way to determine

You can display various types of information with the Pblock Properties view.1. To display or edit Pblock properties, select the Pblock and view the Pblock Properties view. 2. The Statistics tab of the Pblock Properties view displays content information about the Pblock.The Statistics tab shows the following Pblock information: Physical Resources EstimatesA chart of each resource type in the device. Carry StatisticsThe number of vertical carry chain logic objects assigned to the Pblock. It also displays the tallest carry chain assigned to the Pblock and the percentage of its height in relation to the Pblock height. Clock ReportClock signals (Local, Global, and Resource) contained in the Pblock as well as the number of clocked instances on each clock. RPM StatisticsThe number of Relatively Placed Macros (RPM) objects assigned to the Pblock. It also displays the tallest and widest RPM assigned to the Pblock and the percentage of its size in relation to the Pblock size. Clock Region StatisticsThe utilization percentage of each clock region that the Pblock overlaps. Primitive StatisticsThe number of each type of logical resource assigned to the Pblock.

Analyzing ConnectivityUse the Show Connectivity popup menu command to identifyWidely dispersed routingTightly clumped logic modulesUse Shift-click to select source and destination logicUse the popup menu > Show Connectivity commandYou can use this command sequentially to expand a cone of logic

The PlanAhead software has extensive logic expansion, selection and highlighting capabilities. These capabilities can be used to validate that modules are suitable to floorplan. For example, logic modules that connect to logic throughout the device may not be suitable for floorplanning, while tightly grouped and self-contained modules are suitable.Routing congestion and timing inconsistency can be alleviated by floorplanning logic outside ofthe critical logic areas, preventing logic from migrating into the critical areas.1.Use the Show Connectivity popup menu command to identify, widely dispersed routing and tightly clumped logic modules.2. Use Shift-click to select source and destination logic. Right-click and select the Show Connectivity popup menu command.3. You can use the Show Connectivity command to highlight or select a cone of logic from any source net or logic object.

Analyzing Timing ResultsExamine your timing resultsGenerated timing reports make it easy to display all or some paths that are failing to meet a timing constraintHelps you see patternsSimply select the paths to be displayed from the report or use Shift + click to select a group of pathsTo remove, reselect the group and click the Hide All Timing Paths button from the vertical toolbarAfter selecting a path use the popup menu > View Path Report command to see a more detailed timing report

When a timing path is selected, all the gates in the path are selected. The path properties window will show the timing information for each level of hierarchy. If post-place and route placement has been loaded, the tool will show how the path was placed in the device. Analyzing Timing Results with the SchematicView critical paths with the Schematic viewerSelect the path(s) and use the popup menu > Schematic commandHelps you visualize the levels of hierarchyAnalyze logic modules for floorplanning Create Pblocks from selected modulesUse the popup menu > Select Primitive Parents command to select the smallest modules containing all of the selected primitives

You can view the critical paths with the schematic viewer by selecting the paths and use the popup menu > schematic command. 1. This helps your to visualize the levels of hierarchy in your design.2. Then analyze the logic modules that needs to be floorplan.3. Create Pblock for that logic modules.4. Use the popup menu > Select Primitive Parents command to select the smallest modules containing all of the selected primitives.

Visualizing HierarchyHierarchy view displays logic hierarchy Visualize relative size and location of selected logic in Hierarchy viewEasily select parent modules of selected logic to floorplanUse the popup menu > Show Hierarchy command to view a selected module with this viewNote that this only shows size; it does not show how many signals are connected between the modulesLikewise, after selecting a component, use the popup menu > New Pblock command to assign the logic

The Hierarchy view displays the hierarchical relationship of the modules and the relative sizes. The selected logic module displays in the Hierarchy view, which is useful to visualize the module location and relative size prior to floorplanning. You can select modules directly from this view for floorplanning. Logic selected in other views is highlighted in the Hierarchy view.

1. You can easily select parent modules of selected logic to floorplan.2. Use the popup menu > Show Hierarchy command to view a selected module with this view.3. This will show only the size and does not show the signals that are connected between the modules.4. Likewise, after selecting a component, use the popup menu > New Pblock command to assign the logic.

Case StudyDesign has been implemented with no area constraintsImport the design into the PlanAhead software and perform a timing analysisDisplay all of the paths that are failing to meet timing to get ideasNote the hierarchical blocks that are part of the failing pathsIn this example, note that there are long routing delays between some of the block RAMs

This is an example using floorplanning for Timing Closure. The design has been implemented with no area constraints.Only post implementation timing numbers identify what logic is failing timing. After the design has been run through implementation, and the design fails timing, load the results into the PlanAhead tool.Display all of the paths that are failing to meet timing to get ideas.Note the hierarchical blocks that are part of the failing paths. In this example, the block RAMs with the critical paths are spread out over more of the chip then they need to be. Floorplanning can be used to generate a tighter placement. The timing problem occurs in the paths between block RAM. These paths are good candidates for floorplanning.

Case StudyFailing paths displayed with the Schematic viewerConfirmed from the timing reports that most of these paths can be constrained within a few area constraintsIn this case, usbEngine1 is a good candidate, but there may be others

Start off by loading the critical paths into the schematic. The schematic will show which gates are involved in the critical path and in which hierarchy the gates are located. You can trace the logic around the critical gates in the schematic to see how the non-critical logic is structured. The floorplan should constraint at least the timing critical paths between block RAMs inside usbEngine1. So far, usbEngine1 appears to be a good candidate for floorplanning. If usbEngine1 is a large portion of the chip, instead we would try to floorplan the four levels of sub hierarchy that contain the critical path.

Case StudyPlacement reviewed in the Device viewTiming critical nets and logic in green (20% of design)Note the use of block RAMIs there anything wrong?Note the pin layout Is there anything wrong?

Answer 1: Block RAMS are fixed into separate columns. So any time you have a hierarchical component that uses more block RAM or DSP slices than are placed into one column, you may have timing problems due to the routing to and from separate columns.Answer 2: Long routes to pins. This brings to mind the question: Was a good pinout made? If it is too late to re-assign pins, then the logic will need to be placed near the pins.If this slide does not show up well, you can refer to page 25 of the Floorplanning Methodology Guide or ask the instructor to project this slide on the board.Case StudyTop-level floorplan examined (this is just Pblocks with no area constraints) These will have to be made by the user and are based on the design hierarchyThe white box is usbEngine1Note the green linesThese are the connections from logic to I/O pinsIs there anything wrong?Note the red lines They represent the greatest concentration of routes between hierarchical blocks Where should each Pblock go?

213465Answer 1: Long routes to pins. Answer 2: Pblock 1 is okay (it is near its I/O pins). Pblock 2 is also okay. Pblock 3 needs to be centrally located because it is the most popular (communicates with the other Pblocks the most). Pblock 4 needs to be lower (closer to its I/O pins). Pblock 5 needs to be in the upper-left corner of the die. This will put it near its I/O pins and next to Pblock 3. Pblock 6 could be placed anywhere (no I/O pins), but it needs to be next to Pblock 3. Note: If you are going to make all of these area constraints, remember to make sure that Pblock 3 touches with all of the other Pblocks (remember it needs to communicate with all of the others). If other Pblocks communicate with each other, it is also recommended they touch. In the end, if you did not want to make all of these Pblocks and area constraints, you could possibly get by with just an area constraint around usbEngine1 (assuming that was the only block that had timing errors).If this slide does not show up well, you can refer to page 25 of the Floorplanning Methodology Guide or ask the instructor to project this slide on the board.Case StudyIf all the timing errors were only in usbEngine1, then an area constraint for Pblock 5 might be able to be madeSaves some workThe block RAMs and DSP slices within usbEngine1 could also be placed in the upper left corner of the dieThis would in effect force the tools to place the logic closer to its I/O pins

213465The implementation shows the timing errors were only in usbEngine1, then an area constraint for Pblock-5 will be done. The usbEngine1 could also be placed in the upper left corner of the die, which would place the logic closer to the I/O pins.

Case StudyThere were also timing errors in the usbEngine0 componentIn the end, this also required similar floorplanning

So the final solution is shown here

This design has two copies of the same component: usbEngine1 and usbEngine0. Implementation has shown that there is a timing problem with usbEngine1, which will likely appear in usbEngine0 as well. You will need to solve the timing problems of each block separately. Consider both USB blocks as two separate timing critical hierarchies, and floorplan each hierarchy separately.

UCF SyntaxThe following constraints are the output of this exerciseINST "usbEngine1" AREA_GROUP = "pblock_usbEngine1";AREA_GROUP "pblock_usbEngine1" RANGE=SLICE_X0Y60:SLICE_X43Y119;AREA_GROUP "pblock_usbEngine1" RANGE=DSP48_X0Y24:DSP48_X2Y47;AREA_GROUP "pblock_usbEngine1" RANGE=RAMB18_X0Y24:RAMB18_X2Y47;AREA_GROUP "pblock_usbEngine1" RANGE=RAMB36_X0Y12:RAMB36_X2Y23;PlanAhead creates a construct that enables you to constrain any subset of netlist hierarchy to a region on the chip. They are created using the New Pblock and Assign to Pblock commands. The Pblocks are turned into AREA_GROUP constraints in the UCF to guide implementation and they keep the level(s) of hierarchy to various regions on the chip.

List of Questions (Revisited)In hindsight, maybe there could have been a few more questionsWere proper pin planning decisions made?Is there any central logic that needs to be placed in the middle of the die?Are all my area constraints touching appropriately?Should any of my area constraints be used to place logic near dedicated hardware (such as GTs, the PCI core, or memory controllers, for example)?In hindsight, maybe there could have been a few more questions.Were proper pin planning decisions made? Is there any central logic that needs to be placed in the middle of the die? Are all my area constraints touching appropriately? Should any of my area constraints be used to place logic near dedicated hardware (such as GTs, the PCI core, or memory controllers, for example)?PblocksAre used to group logicSupport a user-programmable utilization90%+ for low speed7087% for high speed

There are a number of utilities in the PlanAhead software that can help you make good area constraintsHierarchy viewer, Schematic viewer, and Timing Report generatorAutomatic Pblock assignment and placement

SummaryMore Information To learn more, visit the PlanAhead tool web site www.xilinx.com/planaheadArticles, documentation, white papers, and training enrollment

User GuidePlanAhead Software Tutorial, Design Analysis and Floorplanning for Performace, UG676Floorplanning Methodology Guide, UG633

View the PlanAhead tool video demonstrations Quick Tour of the PlanAhead Design and Analysis Tool I/O pin planning with PinAhead Technology Improve Design Performance with the PlanAhead Design and Analysis tool PlanAhead User GuideFrom the Project Manager: Help > User Guide > PlanAhead User GuideChapter 10, Analyzing Implementation ResultsChapter 11, Floorplanning the DesignFloorplanning Methodology Guide From the Project Manager: Help > Methodology Guides > FloorplanningPlanAhead TutorialsFrom the Project Manager: Help > PlanAhead > Tutorials > Design Analysis and Floorplanning for Performance

Where Can I Learn More?Xilinx Education Services courseswww.xilinx.com/trainingXilinx tools and architecture coursesHardware description language coursesBasic FPGA architecture, Basic HDL Coding Techniques, and other free Videos!

Xilinx is disclosing this Document and Intellectual Property (hereinafter the Design) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (High-Risk Applications). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

2012 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.Trademark Information