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EE141

Timing and Clocks

EE141- Fall 2002Lecture 23

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Announcements

l No homework this weekl Hardware lab next weekl Projects due today

» Please turn in the electronic version by e-mail and a paper copy in the drop box

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Today’s Lecture

l Timing

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Timing

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Latch Parameters

D

Clk

Q

D

Q

Clk

TClk-Q

TH

PWmTSU

TD-Q

Delays can be different for rising and falling data transitions

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Flip-Flop Parameters

D

Clk

Q

D

Q

Clk

TClk-Q

TH

PWm

TSU

Delays can be different for rising and falling data transitions

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Example Clock System

Courtesy of IEEE Press, New York. 2000

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Clock Nonidealities

l Clock skew» Spatial variation in temporally equivalent clock

edges; deterministic + random, tSK

l Clock jitter» Temporal variations in consecutive edges of the

clock signal; modulation + random noise» Cycle-to-cycle (short-term) tJS

» Long term tJL

l Variation of the pulse width » for level sensitive clocking

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Clock Skew and Jitter

l Both skew and jitter affect the effective cycle timel Only skew affects the race margin

Clk

Clk

tSK

tJS

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Clock Skew

# of registers

Clk delayInsertion delayMax Clk skew

Earliest occurrenceof Clk edgeNominal – Tsk/2

Latest occurrenceof Clk edge

Nominal + Tsk/2

Tsk

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Sources of skew and jitter

Clock Generation

Devices

Power Supply

InterconnectCapacitive Load

TemperatureCoupling to Adjacent Lines7

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4

5

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Positive and Negative Skew

R CL R CL RData

φ

CL

R CL R CL RData

CL

φ

(a) Positive skew

(b) Negative skew

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Constraints on Skew

R1 R2

φ’ φ’’δ

tr,min + tl,min

(a) Race between clock and data.

R1 R2

φ’ φ’’+ Pδ

tr,max + tl,max i

(b) Data should be stable before clock pulse is applied.

tφ’ tφ’’ = tφ’ + δ

tφ’ tφ’’ + T =

data

data

φ’’

tφ’ + T + δ

Late

Early

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Clock Constraints in Edge-Triggered Logic

δ tr min, ti tl min,+ +≤

T tr max, ti tl max, δ–+ +≥

Maximum Clock Skew Determined by Minimum Delay between Latches

Minimum Clock Period Determined by Maximum Delay between Latches

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Impact of Jitter

CLK

-tji t ter

TC LK

t j itter

CLK

InCombinational

Logic

tc-q , tc-q, cdt log ict log ic, cdtsu, thold

REGS

tjitter

1

2

3 4

5

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Longest Logic Path in Edge-Triggered Systems

Clk

T

TSU

TClk-QTLM

Latest point of launching

Earliest arrivalof next cycle

Unger and TanTrans. on Comp.10/86

TJI - δ

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Clock Constraints in Edge-Triggered Systems

If launching edge is late and receiving edge is early, the data will not be too late if:

Minimum cycle time is determined by the maximum delays through the logic

Tc-q + TLM + TSU < T – TJI,1 – TJI,2 + δ

Tc-q + TLM + TSU - δ + 2 TJI < T

Jitter always works negatively

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Shortest Path

ClkTClk-Q TLm

Earliest point of launching

Data must not arrivebefore this time

ClkTH

Nominalclock edge

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Clock Constraints in Edge-Triggered Systems

Minimum logic delay

If launching edge is early and receiving edge is late:

Tc-q + TLM – TJI,1 < TH + TJI,2 + δ

Tc-q + TLM < TH + 2TJI+ δ

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How to counter Clock Skew?

RE

G

φ

RE

G

φ

RE

G

φ

.

RE

G

φ

log Out

In

Clock Distribution

Positive Skew

Negative Skew

Data and Clock Routing

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Flip-Flop – Based Timing

Flip-flop

Logic

φ

φ = 1φ = 0

Flip-flopdelay

Skew

Logic delay

TSUTClk-Q

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Flip-Flops and Dynamic Logic

φ = 1φ = 0

Logic delay

TSUTClk-Q

φ = 1φ = 0

Logic delay

TSUTClk-Q

PrechargeEvaluateEvaluatePrecharge

Flip-flops are used only with static logic

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Latch timing

D

Clk

Q

tD-Q

tClk-Q

When data arrives to transparent latch

When data arrives to closed latch

Data has to be ‘re-launched’

Latch is a ‘soft’ barrier

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Single-Phase Clock with Latches

Latch

Logic

φ

Clk

P

PW

Tskl Tskl TsktTskt

Unger and TanTrans. on Comp.10/86

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Latch-Based Design

L1Latch Logic

Logic

L2Latch

φ

L1 latch is transparentwhen φ = 0

L2 latch is transparent when φ = 1

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Slack-borrowing

QDIn CLB_A QD QD

CLK1

L1 L2 L1

CLK2 CLK1

CLB_Btpd,A tpd,B

CLK1

CLK2

TCLK

321 4

a b c d e

tpd,A

a valid b val id

tDQtpd,B

c valid d valid

tDQ

e valid

slack passed to next stage

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Latch-Based Timing

L1Latch Logic

Logic

L2Latch

φ

φ = 1

φ = 0

L1 latch

L2 latch

Skew

Can tolerate skew!

Longpath

Shortpath

Static logic