HOW TECHNOLOGY R&D LEADERSHIP BRINGS A COMPETITIVE ADVANTAGE IN
Transcript of HOW TECHNOLOGY R&D LEADERSHIP BRINGS A COMPETITIVE ADVANTAGE IN
� HOW TECHNOLOGY R&D LEADERSHIP BRINGS � A COMPETITIVE ADVANTAGE
� IN THE FIELDS OF MULTIMEDIA CONVERGENCE
� AND POWER APPLICATIONS
DATE - March 2011
� AND POWER APPLICATIONS
Philippe MAGARSHACKSTMicroelectronics
Technology R&D Group VPCrolles, France
Outline
� Identifying the fundamental post-recovery market changes:
uncovering the new driving applications �Understanding the crucial benefits of
DATE - March 2011
�Understanding the crucial benefits of technology leadership�An ST case study: ST Leadership in Technology & ST Competitive Advantage
2
TAM Market trend line Monthly B Unit and B $ value
Unit PeakJuly 2004
Unit
Unit PeakSept. 2006
Unit PeakOct. 2007
New Unit Record Aug
2010
New $ recordSep. 2010
DATE - March 2011Source : WSTS
$ peak Nov. 2006
$
Unit
PeakOct. 2007
PeakOct. 2000
3
10
100
1000
SC Market $ Billions
25%
50%
75%
SC Market % Growth
Maturing Market
Market growthYoY
SC Current Market
Trend Line
New Trend Line
� Long term CAGR moved from 15% to 7%� But pervasion is not ending
DATE - March 2011
0
1
10
1959
1961
1963
1965
1967
1969
1971
1973
1975
1977
1979
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
2011
e
2013
e
-25%
0%
25%
4
Source : WSTS, ST (5YP forecast)
Key Driving - Loosing Applications2010-2014* Estimates – TAM Variation in M$
Driving
Loosing
DATE - March 20115
(1)Total Industrial sector includes medical, automation and other sub-segments.
* Source: iSuppli, available only until 2014
Market trend by Applications
DATE - March 20116
* Source: iSuppli, available only until 2014
Samsung
NEC
Toshiba
Intel
4
3
2
1
2000
4
3
2
1
1980
4
3
2
1
2010
Hitachi
Motorola
Toshiba
NEC
NEC
Philips
Motorola
TI
4
3
2
1
1990
Toshiba
TI
Samsung
Intel
Semi Industry’s Changing Geography
DATE - March 20117
Sources : Future Horizons, Gartner, iSuppli
MicronInfineon
Hitachi
Motorola
TI
109
8
7
6
5
109
8
7
6
5
109
8
7
6
5
MatsushitaPhilips
Mitsubishi
TI
Fujitsu
Intel
SiemensFairchild
Intel
Hitachi
Toshiba
National
109
8
7
6
5
Micron
Renesas
Elpida
HynixST
Qualcomm
ST
Market Mega-Trends 2009-20141. Industry is maturing
2. Industry is consolidating / specializing3. Semiconductor market keeps moving East
4. Leading-edge processes within few actors
5. Convergence is accelerating
DATE - March 20118
5. Convergence is accelerating6. New software trends reshape the market forces
7. Home and mobile appliances become nodes of
the Web
8. R&D is shifting across the value chain9. Semiconductors are key enablers of environmental policies
Outline
� Identifying the fundamental post-recovery market changes:
uncovering the new driving applications� Understanding the crucial benefits of technology leadership
DATE - March 2011
leadership� An ST case study: ST Leadership in Technology & ST
Competitive Advantage
9
High-Speed >2GHzLow Operation VddLow Stdby Leakage
SOCMULTI-FUNCTIONAL
Mobile Internet DeviceHigh-Speed >>2GHzHigh Operation VddHigh Stdby Leakage
MPUMONO-FUNCTIONAL
Computers, Servers
DIFFERENT PARADIGM => DIFFERENT NEEDS
DATE - March 2011
Video
Gaming, GPS
Set Top Box
AudioPhoto
Computers, Servers
⇒ differenttechnologies needed
MULTITUDE OF FUNCTIONS => MULTITUDE of TECHNOLOGICAL REQUIREMENTS TO RECONCILE
SIP
DATE - March 201111
PROCESS-DESIGN ENABLEMENT-ARCHITECTURECIRCUIT-PACKAGE
MULTITUDE OF FUNCTIONS => MULTITUDE of TECHNOLOGICAL REQUIREMENTS TO RECONCILE
DATE - March 201112
Courtesy BOSCH AE
Technology Platform SegmentationComputers
Computer Peripherals
Communication Infrastructure
Consumers
High Performance
“HP”
General Purpose
“G”
DATE - March 2011
Wireless
Automotive
Industrial
Multi segment
Low power
“LP”
AnalogMS/RF/BCD
/Derivatives
13
Performance
Power leakage
Design simplicity
High Performance
General Purpose
Technology Platform KPI
DATE - March 2011
Area scalingCost of ownership
14
Low power
AnalogMS/RF/BCD
/Derivatives
Technology R&D/MFG Leadership Brings
Time-to-Market • First device tape out in most advanced partner Fab.
• Device volume and yield ramp up thru fast learning technics.
Innovation• Device performance, power, area scaling.
• Device Add on.
• Cost-of-ownership, design simplicity
DATE - March 2011
• Cost-of-ownership, design simplicity
Supply-Chain Multi Sourcing• Time-to-Market first source
• Second /Alternative source thru Manufacturing Synchronization.
Sustainable Effort• cooperative model allows leveraged capture of technology innovation with risk mitigation .
• Shared capital/operating expenses thru cooperative/distributedmodel.
Outline
� Identifying the fundamental post-recovery market changes:
uncovering the new driving applications� Understanding the crucial benefits of technology leadership
DATE - March 2011
leadership
�A case study: ST Leadership in Technology & ST Competitive Advantage
16
50/50 JV with Ericsson
Automotive, Consumer, Computer &
Communication Infrastructure (“ACCI”)
Industrial and Multisegment Sector
(“IMS”)Wireless
Home Entertainment
& Displays
Computer & Communication Infrastructure
Automotive Products
Group
Analog, Power and
MEMS
Microcontrollers, Memories and
SmartcardsMajor Product Lines
ST Business Segment Overview
DATE - March 2011
Products
Major Customers
& Displays Infrastructure Group MEMS Smartcards
17
Wireless: multi-purpose Products
Modem
Camera
MP3 player
Phone Web browser
Radio
DATE - March 201128-Mar-
11
18
Camcorder
GPS / Mapping
Gaming
TV
“Phones”: High Performance @ Low Power
Smartphone
Tablets
� Battery life� Packaging (heat dissipation)
� Energy efficiency (environment)
Nova A9600 (28 nm)dual –core Eagle A15 at 2.5 GHz+ 20X graphics improvement *
DATE - March 201119
2000 20102005
Feature phone
90’s
Basic phone
2011 2012 2014...
� Multimedia convergence
� User experience� Interfaces options� Connectivity
Nova A9540 (32 nm)dual-core A9 @ 1.85 GHz
+ 4X graphics improvement*Sampling 2011.
* vsU8500
Nova A9500 (45 nm)dual-core A9 @ 1.2 GHz
+ 20% graphics improvement*Available
+ 20X graphics improvement * sampling 2011.
ST/ Networking ASICsA growing SOC integration / Power Challenge
32nm LPH
28nm LPG• 400-900MHz• 10-90W
20nm
50+
50
+ M
gate
Mga
te40
040
0--50
0 m
m²
500
mm
²2020
--40 40
Mga
teM
gate
200
200--
400
mm
²40
0 m
m²
>1GHz>1GHz>40W >40W avg.avg.
>1GHz>1GHz>40W >40W avg.avg.
DATE - March 201120
90nm• 100-250MHz• 5-10W
65nm LP & LPGP• 200-500MHz• 15-70W
• 300-600MHz• 10-80W
• 10-90W
5-20
Mga
te10
0-20
0 m
m²
5 M
gate
50-1
00 m
m²
SerDes RoadmapSerDes Roadmap
20072007--080833--6GBps6GBps
20092009--101066--10Gbps10Gbps
201120111010--14Gbps14Gbps
201220121414--25Gbps25Gbps
2013+2013+25+ 25+ GbpsGbps
Courtesy R Ferrari, G Cesana, ST
ST/Consumer relentless integration
Mtr
500
1000
2000
5 CPU’s, 500MHz ~3-4W, WB, FE integration
8 CPU/GPU’s, 1-2GHz,~3-7W, FC, system on single package
10 CPU/GPU’s, >2GHz, ~3-7W, Flip Chip/3DstackHeterogeneous
PMIC
FEnd
Apps
Network
MPE6 CPU/GPU’s, 700MHz,~3-6W, WB&FC,system Co-design
25-40k DMIPS« ARM based »
DATE - March 201121
90/80GP
2004-2007
65/55LP
2005-2011
40LP
2008-2011
32/28LP
2009-2015
20nm
2012-2017
50
100
3CPU’s, 250MHz,~3W, Hier. Design,Wire bonding
STB, IPTV: HD format,Single decode, DDR1,
Security, Analog
STB, IPTV & TV:Dual HD decode, DDR2, Analog
DDR3 Systems:Digital platform
with appsSTB,TV, Gateways: Decode+encode,
DDR2/3, Graphic and 3DTV
2k DMIPS« SH4 + »
8-20k DMIPS« A9 based »
1k DMIPS« SH4 »
« ARM based »
Courtesy D Henoff, ST/HED
The ST Technology R&D Model
A Distributed & Cooperative R&D:
• Leveraging best innovation versus :
• Targeted product• Critical decision factor
DATE - March 2011
• Critical decision factor• Technology
• Mitigating risks of choice
• Sharing expenses effort
22
Value-Chain Management : Technology Innovation 1 /3
� Technology Innovation leveraging bi/ multi third parties competence centers:
� Fundamental/ advanced R&D thru joint Academia/Research Institutes Cooperation. (CEA LETI being the corner stone.)
DATE - March 2011
being the corner stone.)
� Advanced CMOS both Low Power and General Purpose R&D thru ISDA (Advanced R&D pre T0).
23
Value-Chain Management :Technology Operations 2/3
� Technology Operations balanced between internal/third parties competence centers:
� Advanced CMOS thru International Semiconductor Development Alliance (ISDA) with strong concurrent development activities .
DATE - March 2011
development activities .
� CMOS Analog and Derivatives thru internal Cluster of Crolles (France)
� Smart Power/Analog thru internal Cluster of Agrate (Italy)
� Distributed Design Enablement thru internal clusters of Agrate/Crolles/Greater Noida (India).
24
� Scope: Electrical Synchronization of partner fabs to IBM� Parametrical equivalence, GDS2-level
� Contract: JDA between IBM and partners on 32LP Bulk and 28LP.� Timing: Program started 2H09 (28LP), end DEC2011.
IP circuits EquivalenceDirect validation between ST & foundry, not in Fabs ync
ISDA MANUFACTURING SYNC 3/3
DATE - March 201125
Test vehicleCommon modeling macros
Common electrical monitoring
In line Cp/Cpk Equivalence Metrology (SEMCD, Overlay, thin films, material com position) matching
ProcessFEOL & BEOL critical process steps,
Construction Analysis
Parametrical EquivalenceEquivalence to model
Model to silicon correlation
1.5
2
2.5
D0
Poi
sson
(D
ef/c
m²)
D0 90nm
D0 65nm
D0 45nm
Yield Learning – D 0 Trend – ST/Crolles
C065
C045
DATE - March 2011
0
0.5
1
Q3 05
Q4 05
Q1 06
Q2 06
Q3 06
Q4 06
Q1 07
Q2 07
Q3 07
Q4 07
Q1 08
Q2 08
Q3 08
Q4 08
Q1 09
Q2 09
Q3 09
Q4 09
Q1 10
Q2 10
Q3 10
Q4 10
Q1 11
Q2 11
D0
Poi
sson
(D
ef/c
m²)
26
C090C065
� Technology Development:
• CMOS Core logic
Analog MS/RF, eDRAM, eNVM
• CMOS Imaging
� Central CAD & Design Solutions
� Technology Development:
• CMOS Core logic
Analog MS/RF, eDRAM, eNVM
• CMOS Imaging
� Central CAD & Design Solutions
� Technology Development:
• Analog (BCD, HVCMOS)
• MEMS
� Central CAD & Design Solutions
� Technology Development:
• Analog (BCD, HVCMOS)
• MEMS
� Central CAD & Design Solutions
ST Clusters of Competence
DATE - March 2011
� Technology Development:
• Advanced Power Discretes
• Micro fuel cell, solar, thin films batt.
• Biotechnologies & healthcare
• Integrated active & passive devices
� Specific CAD & Design Solutions
� Technology Development:
• Advanced Power Discretes
• Micro fuel cell, solar, thin films batt.
• Biotechnologies & healthcare
• Integrated active & passive devices
� Specific CAD & Design Solutions
� Central CAD & Design Solutions
� Information & Communication Technology
� Central CAD & Design Solutions
� Information & Communication Technology
27
L1 Cache designed to reach 1.8Ghz
High Density L2 cache designed for 0.6 V
Retention
High Performance Clock Generator
HPCG
Enabling performance race on products :STE 32nm 1.5GHz Low Power A9 Core
A9 Power
Management
DATE - March 201128
Power Switches:Peripheral Switches and Distributed Switches for
best Vdrop.
Fast FF library designed for improving R2R
performance in critical pathsFaster pipelined Memory
BIST Architecture
Retention
Dedicated algorithms for Memory Test in 32/28nm
Several IP/Lib
Patents Pending
Management Solution
5V
4V
3V
2V
Power Supply
High Voltage Solutions•Mission Mode •Thermal Management•Supply Noise Management
Application / System Solutions
•SW control •multiple OPP•Closed loop AVS
Vdd Scaling and energy efficiencyScaling driven by process technology (T ox)
DATE - March 2011
19951990 2000 2005 20101985
2V
1V
2015
Low Voltage / Power Solutions•Technology: Multi Vt / Large-L / BB•SRAM: 6T -> 8T/ 0.5V SRAM•Logic: Low VDD Logic / Async Logic •IC Design: Design for Variability, GALS, AVS, ABB
Energy Efficient Design for +/- nominal V DD
5V
4V
3V
2V
Power Supply
Power Management
LP/GP Process
Multi Vt CMOS
Process compensation
System Level Power Management
Product Leakage (a.u) (no management)
Vdd Scaling and energy efficiencyKeeping leakage under control
HKMG
DATE - March 2011
19951990 2000 2005 20101985
2V
1V
2015
Product Leakage (a.u) (no management)
CMOS 32/28nm : ST Differentiating Factors
ST offering process/IP addST offering process/IP add--ons vs. standard ISDA offerons vs. standard ISDA offer
Cu PillarCu Pillar SP Bitcell for ARM CacheSP Bitcell for ARM Cache
• 0.244µm² bitcell• High current, low leakage, low Vdd• 1.5GHz+ cache operation
@ SS/1.0V/0C/Rcmax
• 0.6V Vmin RAM operation enabled
ST specific bitcell
• < 50um Bump Pitch •Enabling 3D integration
DATE - March 2011
• 0.6V Vmin RAM operation enabled
MIM Decoupling CapMIM Decoupling Cap
• Enhanced power supply control • For GHz+ operation
LPG & LPG & Poly BiasingPoly Biasing
• Specific High Speed Transistor (G) for critical paths inside Core
• High efficiency in overdrive mode
ST specific process option ST specific process option
28nm Speed Projection
+15%
+15%
+15%
28nm FDSOI: the next speed booster�
DATE - March 2011
BOX
RaisedS/D
VLSI Platform Worldwide clusters
Agrate
DATE - March 20113333
Technology Leadership : Leading Edge
TSMC
Samsung
Glob.F.
UMC
SMIC ?
TSMC
Samsung
Glob.F.Foundries
DATE - March 201134
IDMs
ST Technology Leadership
� ST R&D cooperative model allows leveraged capture of technology innovation and risk mitigation
� ST leadership in technology enables differentiated / competitive product positioning through:
� Device Integration
DATE - March 2011
� Device Integration� Device add-on for Derivatives / Analog� Design Enablement� Specific process modules for best device performanc e� Fast yield learning cycle time techniques
and a full multi sourcing supply-chain efficiency.
35
What’s next after 20nm?� High Performance (µPs) will move to 15nm with ` relaxed
design rules
� SOC/ ASICs (LP/GP) will move to 14nm for dense rulesbecause 2x shrink factor, +30% Perf vs 20nm
� 2 main disruptions are expected:� Lithography: moving from 193nm immersion to EUV
DATE - March 201136
� Lithography: moving from 193nm immersion to EUV� Device: moving from bulk CMOS to Thin Silicon devices
� For devices, 2 options:� FinFET� FDSOI
� 3D integration could appear faster
Main candidates after bulk are FinFET and FDSOI:
FDSOI = 2D FinFET = 3D
gate
Thin Silicon film
gate
drain
source
height
DATE - March 201137
Thin Silicon film
FDSOI FinFET
Strengths - 2D (planar) process- Electrostatic control
-Double gate : Electrostatic control
Risk - Compatibility withconventional « performanceboosters »
-Process complexity (3D)-Compatibility with conventional« performance boosters »
Transistor Architecture Trends
Record Performance Nanodot FET (ST VLSI 2009)
32/28nm
22/20nm
16nm/14nm
11nm/10nm8nm/7nm
�Self Aligned PlanarDouble Gates structures
25nm FDSOI ( ST/IBM VLSI 2010)
HQS GAA Devices(ST IEDM 2010)
FinFET ( ST/IMEC VLSI 2006)
15nm FDSOI ( ST/LETI VLSI 2010)
DATE - March 201138
28nm Low Power (ST/IBM IEDM 2009)
Hybrid UTB² /Bulk(ST/LETI IEDM 2009)
32/28nm
�Gate First MetalGateHigh-K
� Bulk w/ enhancedstressors�2nd GenerationMGHK (GateLast)� Improvedjunctions
�Fully Depleted SOI with Hybrid Bulk
�Fully DepletedSOI with Ultra Thin BOX and Stressors
�FinFETsstructures
� FullyDepletedSOI withHybrid Bulk
� 3D/Heterogeneous Integration of Wide-IO DRAM� Benefits: Low-Power DRAM/SOC data connexion
Challenges: cost, thermal management, Test, Supply Chain
-
Next to come: 3D, Photonics
DATE - March 201139
Communication bandwidthrapidly increasing from few Gb/s to 100Gb/s.
� Copper wire technology not able to sustain such data rates
� Photonics on silicon technologyallows die to die and within die optical communication CMOS
wafertransistors metal interconnects
FC
Modulator
AWG
Ge
PD
InP source
PAD
Optical connexions already presentin servers/routersrack to rack communications
Photonics on Silicon
SOC CMOS Application Trends : Summary� SOC Applications require high-performance energy-efficient
Processing Units (CPUs, GPUs, …) :� Wireless� Consumer� Automotive� Computer Peripherals
DATE - March 2011
� ST’s 32/28nm LP / Design Platform at state-of-the-art� Process optimizations, above industry leading ISDA HKMG 32nm� Library/IP design� CAD Flow/ Sign-off optimization� Application-driven
� Partnerships are key to optimize R&D investment� Process, IP, Design, EDA, Universities, Labs
40
Mastering the Technology Platform
DATE - March 201141
� ST has proven the competitive advantage of its R&D model
at 40nm then at 28 nm node
� Moving to 20 nm and beyond , with increasing complexity,
facing major architecture, process, equipment disruption s
Conclusion
DATE - March 2011
Yet investing deep knowledge in Process, Design Enablement,
Manufacturing and their interactions ,
ST will strengthen its position of
‘UNDISPUTED LEADER IN MULTI MEDIA CONVERGENCE
AND SENSE&POWER APPLICATIONS’
42