Host/Memory/User Interface

Interfacing with the host computer, external memory, and user

ESU: Extended Parallel Port, Smart Media Card, and User Interfaces

ESU Memory Mapped Registers

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDR NAME

Tds Twh Tdh Trc No wait X 0x2000 Timing

EPP Data Unused 0x2001 EPP Data

SMC Data Unused 0x2002 SMC Data

SMC Command(0 – F Hex)

SMC

ready/not-busy

SMC

Data(fromcard)

EPP

Datainreg

EPP

Spare

Front Panel soft touch buttons 0x2003 Commandand status

ESU: Memory Mapped Register Descriptions

• TimingProgrammed by software (probably the boot routine) this register sets parameters for all of the critical timing between the DSP and the Smart Media Card. Each of the timing blocks is a 3 bit number which will be used as a index to a counter. Therefore the smallest number we can count for is our cycle time (10ns). This 3 bit limitation means that the longest we can hold a signal for is 70ns. The longest requirement for our SMC is 50ns.

• DataThe data register is a bi-directional register which can be written and read by the SMC, the EPP, and the Data Bus. The first byte of the data register is designated for the SMC (which has an 8 bit I/O bus), and the second for the EPP.

• Command/StatusThe command/status register takes care of all other functions. It is polled and written regularly by both software and the host. Additionally the last byte of this register can be written by eight external buttons (user controls). The first four bits specify the SMC operation that software wants to perform and are read by the SMC_SIG_GEN unit to carry out that operation. Bit four is the SMC R/nB, which indicates if a SMC operation is running. Bit 5 is the SMC data read bit, which goes hi when there is valid data from the SMC in the data register. Bit six is the EPP status bit, it indicates if there is data in the data register. This bit can be written by both the host and the software, and therefore must be polled before the data register is written by either.

SMC CommandsNOP 0000 Do Nothing

CMD 0001 Send Command to SMC*

Addr1 0010 Load First Address of a two or three byte address word*

WRITE 0011 Load a byte of data*

READ1 0100 Store the first byte from SMC into Data register

READ 0101 Store a successive byte from SMC to Data register

Wait 0110 Wait (only used in erase between address write and erase command)

Reset 0111 Stops any current operation (e.g. READ) and SMC returns control of the data bus.

WAKE 1000 Wake the SMC up after reset. SMC takes over the data bus.NOTE: NO OTHER OFF CHIP OPERATIONS ARE ALLOWED UNTIL NEXT RESET.

OPEN 1001 Unused

OPEN 1010 Unused

OPEN 1011 Unused

OPEN 1100 Unused

OPEN 1101 Unused

OPEN 1110 Unused

OPEN 1111 Unused

* Data must be valid in the Data register before the command is programmed in the cmd/status register

Example operations

• READ:Commands: CMD Addr1 Addr2 Addr3 Read1 Read … Reset

Data: <00h> <a1> <a2> <a3> <Din> <Din> …<XX>

• Write:Commands: CMD Addr1 Addr2 Addr3 Write Write … Write CMD CMD Read1

Data: <80h> <a1> <a2> <a3> <Dout> <Dout> … <Dout> <10h> <70h> <stat>

• Erase:Commands: CMD Addr1 Addr2 Wait CMD CMD Read1

Data: <00h> <a1> <a2> <XX> <D0h> <70h> <stat>

Boot Memory Interface(BMI)

BMI Pin DescriptionSignal Function Attr.

DATA[0:3] &ADDR[0:12]

Address to Boot Memory Out

BMS_B Chip Enable signal to Boot Memory OutBM 1= Boot Mode, 0= Normal Out To I-UNITDATA_RDY 1= Data from Boot Memory is valid Out To I-UNITDATA[8:15] Data from Boot Memory InPMDAK 1= enable BMI to drive PMD bus In From I-UNITBMA0_SEL 1= Data from DMD bus to BMADDR0 register In From I-UNITBMA1_SEL 1= Data from DMD bus to BMADDR1 register In From I-UNITBMS_SEL 1= Data from DMD bus to BMSTS register In From I-UNITBMS_EN 1= enable Data in BMSTS register dump to DMD

busIn From I-UNIT

BMD_EN 1= enable Data in BMDATA register dump to DMDbus

In From I-UNIT

CLK System Clock InRESET Reset signal InDMD[0;15] Data Memory Data bus In/OutPMD[0;23] Program Memory Data bus In/Out

Boot Mode Process Flow

Boot Memory Contents

Memory Mapped Register(1)

Memory Mapped Register(2)

Off-chip SRAM Interface(OSI)

OSI Pin DescriptionSignal Function Attr.

ADDR[0:12] Address to Off-Chip SRAMs OutDMS_B Chip Enable signal to Off-chip DM OutPMS_B Chip Enable signal to Off-chip PM OutEWE_B Write Enable signal to Off-chip SRAMs OutERE_B Read Enable signal to Off-chip SRAMs OutEDMD_RDY 1= Data in EDMD Register is valid Out To I-UNITEPMD_RDY 1= Data in EPMD Register is valid Out To I-UNITDMA[0:13] Data Memory Address bus InPMA[0:13] Program Memory Address bus InWE_B 0= write Data to Memory

1= read Data from MemoryIn From I-UNIT

DCE_B 0= Chip Enable to Data Memory In From I-UNITPCE_B 0= Chip Enable to Program Memory In From I-UNITCLK System Clock InRESET Reset signal InDATA[0:23] Data from/to Off-chip SRAMs In/OutDMD[0:15] Data Memory Data bus In/OutPMD[0:23] Program Memory Data bus In/Out

Off-chip SRAM Access Flow

Off-chip SRAM Write Timing

Off-chip SRAM Read Timing