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Transcript of Host Port Interface Expansion Bus Chapter 16 C6000 Integration Workshop Copyright © 2005 Texas...
![Page 1: Host Port Interface Expansion Bus Chapter 16 C6000 Integration Workshop Copyright © 2005 Texas Instruments. All rights reserved. T TO Technical Training.](https://reader035.fdocuments.in/reader035/viewer/2022062323/5697bfea1a28abf838cb71bc/html5/thumbnails/1.jpg)
Host Port InterfaceExpansion Bus
Chapter 16
C6000 Integration Workshop
Copyright © 2005 Texas Instruments. All rights reserved. T TO
Technical Training Organization
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Objectives HPI Overview HPI on the DSK Host Software Example HPI Hardware Description Optional Discussions
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Why HPI?
CC ‘C6x‘C6x
Ser. Port
32
|| Bus
Ded. Bus
Dedicated to memory access
Dedicated to Codecs and A/D’s
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Why HPI for Communication? Give host control of the transfer Allow host to access the entire
C6000 memory map Additional parallel bus for data
exchange between a host and the C6000
Provide glueless interface to many different types of hosts
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What are the requirements of the dedicated bus?What are the requirements of the dedicated bus?
Why HPI?
CC ‘C6x‘C6x
Ser. Port
32
|| Bus
Ded. Bus
Dedicated to memory access
Dedicated to Codecs and A/D’s
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What are the requirements for the dedicated bus?1. Address2. Data3. Control
What are the requirements for the dedicated bus?1. Address2. Data3. Control
HPI Bus
HPI Overview
C C ‘C6x‘C6xHPI
HPIC
HPIA
HPID
DMA Aux. Ch.
Addr.
Data
Memory
..
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HPI Bus
HPI Overview
Since the HPI bus (HD) is only 16 bits wide, each read/write requires two operations.
Since the HPI bus (HD) is only 16 bits wide, each read/write requires two operations.
C C ‘C6x‘C6xHPI
HPIC
HPIA
HPID
DMA Aux. Ch.
Addr.
Data
Memory
..
16
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Objectives HPI Overview HPI on the DSK Host Software Example HPI Hardware Description Optional Discussions
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Host DSK Communications The C6713 DSK has a HPI connector which brings out the pins of the
Host Port Interface On the C6416 DSK, this connector contains the muxed HPI/PCI pins Also shown, the JTAG emulation connections
DSP
JTAGEmulation
Port
HPI connector
USB
..............
JTAG
....... .............. .......
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Objectives HPI Overview HPI on the DSK Host Software Example HPI Hardware Description Optional Discussions
T TOTechnical Training
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Some Ideas for Host Interface APIC6X_open( ) Open a connection to the C6000
C6X_close( ) Close a connection to the C6000
C6X_resetBoard( ) Reset the entire board
C6X_resetDsp( ) Reset only the DSP on the board
C6X_dspImageLoad( ) Load a DSP image (COFF) to DSP memory
C6X_memRead( ) Read DSP memory via the HPI
C6X_memWrite( ) Write to DSP memory via the HPI
C6X_ctrlRead( ) Read HPI control register
C6X_ctrlWrite( ) Write to HPI control register
C6X_generateInt( ) Generate a DSP interrupt
C6X_isr( ) Respond to host interrupt (HINT) from DSP
Here are some ideas for the host software (and hardware) functionality you might want to build into your system
These routines could be combined to create more advanced host functions (like routines for setting up the EDMA and such)
Unfortunately, we cannot provide these functions for you, as they must be written specific to the hardware of your hostT TO
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Objectives HPI Overview HPI on the DSK Host Software Example HPI Hardware Description
Setup Control and Address Writing 32-bits Reading 32-bits Sequential Accesses
Optional Discussions
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Setup HPI Control Register
HWOB0 - Big Endian
1 - Little Endian
HWOB0 - Big Endian
1 - Little Endian
HWOBreserved
015 5
HWOBreserved
1631 21
Setup the HPI Control register (HWOB-bit) to specify which 16-bits (upper or lower) are transferred first.
Similar to little/big endian. Order doesn’t matter when
writing to HPIC as the fieldsare aliased to both halves.
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Setup HPIC
1. Use HCNTL[1:0] = 00b to enable access to HPIC1. Use HCNTL[1:0] = 00b to enable access to HPIC
CC ‘C6x‘C6xHPI
DMA Aux. Ch.
Addr.
Data
2
HCNTL
HPID
HPIA
Memory
..
HD16
HPIC
HCNTL ValuesHCNTL Values
HCNTL1 HCNTL0 Description
0 0 HPIC
0 1 HPIA
1 0 HPID (HPIA++)
1 1 HPID
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Setup HPIC
CC ‘C6x‘C6xHPI
DMA Aux. Ch.
Addr.
Data
2
HCNTL
HPID
HPIA
Memory
..
HD16
HPIC
HR/W
1. Use HCNTL[1:0] = 00b to enable access to HPICHR/W to write (0). HD = ctrl bits (HWOB= xxx1)
1. Use HCNTL[1:0] = 00b to enable access to HPICHR/W to write (0). HD = ctrl bits (HWOB= xxx1)
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Setup HPIC - 1
CC ‘C6x‘C6xHPI
DMA Aux. Ch.
Addr.
Data
HPID
HPIA
Memory
..
HD16
HPIC
HR/W
HHWIL
1. Use HCNTL[1:0] = 00b to enable access to HPICHR/W to write (0), HD = ctrl bits (HWOB = xxx1)HHWIL = 0 indicates first halfword transfer
1. Use HCNTL[1:0] = 00b to enable access to HPICHR/W to write (0), HD = ctrl bits (HWOB = xxx1)HHWIL = 0 indicates first halfword transfer
2
HCNTL
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HSTRB - 2
CC ‘C6x‘C6xHPI
DMA Aux. Ch.
Addr.
Data
HPID
HPIA
Memory
..
HPIC
HSTRB
1. Use HCNTL[1:0] = 00b to enable access to HPICHR/W to write (0). HD = ctrl bits (HWOB = xxx1)HHWIL = 0 indicates first halfword transfer
2. HSTRB to indicate active
1. Use HCNTL[1:0] = 00b to enable access to HPICHR/W to write (0). HD = ctrl bits (HWOB = xxx1)HHWIL = 0 indicates first halfword transfer
2. HSTRB to indicate active
HD16
HR/W
HHWIL
2
HCNTL
xxx1
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Setup HPIC - 3
CC ‘C6x‘C6xHPI
DMA Aux. Ch.
Addr.
Data
HPID
HPIA
Memory
..
HPIC
3. Use HCNTL[1:0] = 00b to enable access to HPICHR/W to write (0). HD = ctrl bits (HWOB = xxx1)HHWIL = 1 indicates second halfword transfer
3. Use HCNTL[1:0] = 00b to enable access to HPICHR/W to write (0). HD = ctrl bits (HWOB = xxx1)HHWIL = 1 indicates second halfword transfer
HD16
HR/W
HHWIL
2
HCNTL
xxx1
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Setup HPIC - 4
CC ‘C6x‘C6xHPI
DMA Aux. Ch.
Addr.
Data
HPID
HPIA
Memory
..
HPIC
HSTRB
3. Use HCNTL[1:0] = 00b to enable access to HPICHR/W to write (0). HD = ctrl bits (HWOB = xxx1)HHWIL = 1 indicates second halfword transfer
4. HSTRB to indicate active
3. Use HCNTL[1:0] = 00b to enable access to HPICHR/W to write (0). HD = ctrl bits (HWOB = xxx1)HHWIL = 1 indicates second halfword transfer
4. HSTRB to indicate active
HD16
HR/W
HHWIL
2
HCNTL
xxx1xxx1
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Setup HPIA - 1
C
Write
8000_0000
to
HPIA
C
Write
8000_0000
to
HPIA
‘C6x‘C6xHPI
DMA Aux. Ch.
Addr.
Data
HPID
HPIA
Memory
..
HPIC
1. Use HCNTL[1:0] = 01b to enable access to HPIAHR/W to write (0), HD = 0000HHWIL = 0 indicates first halfword transfer
1. Use HCNTL[1:0] = 01b to enable access to HPIAHR/W to write (0), HD = 0000HHWIL = 0 indicates first halfword transfer
HR/W
HHWIL
HD16
2
HCNTL
xxx1xxx1
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Setup HPIA - 2
C
Write
8000_0000
to
HPIA
C
Write
8000_0000
to
HPIA
‘C6x‘C6xHPI
DMA Aux. Ch.
Addr.
Data
HPID
HPIA
Memory
..
HPIC
HSTRB
1. Use HCNTL[1:0] = 01b to enable access to HPIAHR/W to write (0). HD = 0000HHWIL = 0 indicates first halfword transfer
2. HSTRB to indicate active
1. Use HCNTL[1:0] = 01b to enable access to HPIAHR/W to write (0). HD = 0000HHWIL = 0 indicates first halfword transfer
2. HSTRB to indicate active
HD16
HR/W
HHWIL
2
HCNTL
xxx1xxx1
0000
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Setup HPIA - 3
C
Write
8000_0000
to
HPIA
C
Write
8000_0000
to
HPIA
‘C6x‘C6xHPI
DMA Aux. Ch.
Addr.
Data
HPID
HPIA
Memory
..
HPIC
3. Use HCNTL[1:0] = 01b to enable access to HPIAHR/W to write (0). HD = 8000HHWIL = 1 indicates second halfword transfer
3. Use HCNTL[1:0] = 01b to enable access to HPIAHR/W to write (0). HD = 8000HHWIL = 1 indicates second halfword transfer
HD16
HR/W
HHWIL
2
HCNTL
xxx1xxx1
0000
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Setup HPIA - 4
C
Write
8000_0000
to
HPIA
C
Write
8000_0000
to
HPIA
‘C6x‘C6xHPI
DMA Aux. Ch.
Addr.
Data
HPID
HPIA
Memory
..
HPIC
HSTRB
3. Use HCNTL[1:0] = 01b to enable access to HPIAHR/W to write (0). HD = 8000HHWIL = 1 indicates second halfword transfer
4. HSTRB to indicate active
3. Use HCNTL[1:0] = 01b to enable access to HPIAHR/W to write (0). HD = 8000HHWIL = 1 indicates second halfword transfer
4. HSTRB to indicate active
HD16
HR/W
HHWIL
2
HCNTL
xxx1xxx1
00008000
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Objectives
HPI Overview HPI on the DSK Host Software Example HPI Hardware Description
Setup Control and Address Writing 32-bits Reading 32-bits Sequential Accesses
Optional Discussions
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Example 1: Writing a 32-bit Value - 1
1. HCNTL[1:0] = 11b (HPID)HR/W = 0 , HD = 5678HHWIL = 0
1. HCNTL[1:0] = 11b (HPID)HR/W = 0 , HD = 5678HHWIL = 0
C
Write
1234_5678
to
8000_0000
C
Write
1234_5678
to
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HD16
HR/W
HPIC
xxx1xxx1
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Example 1: Writing a 32-bit Value - 2
C
Write
1234_5678
to
8000_0000
C
Write
1234_5678
to
8000_0000
‘C6x‘C6xHPI
HPID
5678
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HD16
HSTRB
HR/W
HPIC
xxx1xxx1
1. HCNTL[1:0] = 11b (HPID)HR/W = 0 , HD = 5678HHWIL = 0
2. HSTRB
1. HCNTL[1:0] = 11b (HPID)HR/W = 0 , HD = 5678HHWIL = 0
2. HSTRBT TO
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Example 1: Writing a 32-bit Value - 3
3. HCNTL[1:0] = 11b (HPID)HR/W = 0Write value: HHWIL = 1, HD = 1234
3. HCNTL[1:0] = 11b (HPID)HR/W = 0Write value: HHWIL = 1, HD = 1234
C
Write
1234_5678
to
8000_0000
C
Write
1234_5678
to
8000_0000
‘C6x‘C6xHPI
HPID
5678
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HD16
HR/W
HPIC
xxx1xxx1
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Example 1: Writing a 32-bit Value - 4
3. HCNTL[1:0] = 11b (HPID)HR/W = 0Write value: HHWIL = 1, HD = 1234
4. HSTRB
3. HCNTL[1:0] = 11b (HPID)HR/W = 0Write value: HHWIL = 1, HD = 1234
4. HSTRB
C
Write
1234_5678
to
8000_0000
C
Write
1234_5678
to
8000_0000
‘C6x‘C6xHPI
HPID
1234 5678
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HD16
HR/W
HPIC
xxx1xxx1
HSTRB
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Example 1: Writing a 32-bit Value - 5
3. HCNTL[1:0] = 11b (HPID)HR/W = 0Write value: HHWIL = 1, HD = 1234
4. HSTRB5. HRDY high (not-ready) until DMA is finished
3. HCNTL[1:0] = 11b (HPID)HR/W = 0Write value: HHWIL = 1, HD = 1234
4. HSTRB5. HRDY high (not-ready) until DMA is finished
C
Write
1234_5678
to
8000_0000
C
Write
1234_5678
to
8000_0000
‘C6x‘C6xHPI
HPID
1234 5678
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HD16
HSTRB
HRDY
HPIC
8000 0000
1234 5678
1234 5678
xxx1xxx1HR/W
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Example 1: Writing a 32-bit Value - 5
3. HCNTL[1:0] = 11b (HPID)HR/W = 0Write value: HHWIL = 1, HD = 1234
4. HSTRB5. HRDY high (not-ready) until DMA is finished
3. HCNTL[1:0] = 11b (HPID)HR/W = 0Write value: HHWIL = 1, HD = 1234
4. HSTRB5. HRDY high (not-ready) until DMA is finished
C
Write
1234_5678
to
8000_0000
C
Write
1234_5678
to
8000_0000
‘C6x‘C6xHPI
HPID
1234 5678
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HD16
HSTRB
HPIC
8000 0000
1234 5678
1234 5678
xxx1xxx1HR/W
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Objectives
HPI Overview HPI on the DSK Host Software Example HPI Hardware Description
Setup Control and Address Writing 32-bits Reading 32-bits Sequential Accesses
Optional Discussions
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Example 2: Reading a 32-bit Value - 1
1. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 0
1. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 0
C
Read
8000_0000
C
Read
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HR/W
HPIC
1234 5678
xxx1xxx1
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Example 2: Reading a 32-bit Value - 2
1. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 0
2. HSTRB, HPIA is copied to DMA address
1. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 0
2. HSTRB, HPIA is copied to DMA address
C
Read
8000_0000
C
Read
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HSTRB
HPIC
1234 5678
xxx1xxx1HR/W
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Example 2: Reading a 32-bit Value - 3
1. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 0
2. HSTRB, HPIA is copied to DMA address3. HRDY is asserted until HD = 5678
1. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 0
2. HSTRB, HPIA is copied to DMA address3. HRDY is asserted until HD = 5678
C
Read
8000_0000
C
Read
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HPIC
1234 5678
xxx1xxx1
HD16
1234 5678
HR/W
HSTRB
HRDY
1234 56785678Host Data
8000 0000
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Example 2: Reading a 32-bit Value - 3
1. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 0
2. HSTRB, HPIA is copied to DMA address3. HRDY is asserted until HD = 5678
1. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 0
2. HSTRB, HPIA is copied to DMA address3. HRDY is asserted until HD = 5678
C
Read
8000_0000
C
Read
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HPIC
1234 5678
xxx1xxx1
HD16
1234 5678
HR/W
HSTRB1234 56785678
Host Data
8000 0000
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Example 2: Reading a 32-bit Value - 4
4. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 1
4. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 1
C
Read
8000_0000
C
Read
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HPIC
8000 0000 1234 5678
xxx1xxx1
HD16
1234 56781234 5678
HR/W
5678Host Data
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Example 2: Reading a 32-bit Value - 5
4. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 1
5. HSTRB
4. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 1
5. HSTRB
C
Read
8000_0000
C
Read
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HPIC
1234 5678
xxx1xxx1
1234 56781234 5678
8000 0000
HD16
HR/W
HSTRB5678
Host Data
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Example 2: Reading a 32-bit Value - 6
4. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 0
5. HSTRB6. HD = 1234
4. HCNTL[1:0] = 11b (HPID)HR/W = 1Read value: HHWIL = 0
5. HSTRB6. HD = 1234
C
Read
8000_0000
C
Read
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
Memory
..
HPIC
8000 0000 1234 5678
xxx1xxx1
HD16
1234 56781234 5678
HR/W
HSTRB1234_5678Host Data
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Objectives
HPI Overview HPI on the DSK Host Software Example HPI Hardware Description
Setup Control and Address Writing 32-bits Reading 32-bits Sequential Accesses
Optional Discussions
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Example 3: Sequential Accesses - 1
1. HCNTL[1:0] = 10b (HPID w/HPIA++)HR/W = 1Read value: HHWIL = 0
1. HCNTL[1:0] = 10b (HPID w/HPIA++)HR/W = 1Read value: HHWIL = 0
C
Read 16
values
starting at
8000_0000
C
Read 16
values
starting at
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
MemoryHPIC
1234 5678
..
1111 0000
xxx1xxx1HR/W
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Example 3: Sequential Accesses - 2
1. HCNTL[1:0] = 10b (HPID w/HPIA++)HR/W = 1Read value: HHWIL = 0
2. HSTRB
1. HCNTL[1:0] = 10b (HPID w/HPIA++)HR/W = 1Read value: HHWIL = 0
2. HSTRB
C
Read 16
values
starting at
8000_0000
C
Read 16
values
starting at
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTL
HPIA
8000 0000
MemoryHPIC
1234 5678
..
1111 0000
xxx1xxx1HR/W
HSTRB
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Example 3: Sequential Accesses - 3
1. HCNTL[1:0] = 10b (HPID w/HPIA++)HR/W = 1Read value: HHWIL = 0
2. HSTRB3. HRDY is high until HD = 5678, HPIA is incremented
1. HCNTL[1:0] = 10b (HPID w/HPIA++)HR/W = 1Read value: HHWIL = 0
2. HSTRB3. HRDY is high until HD = 5678, HPIA is incremented
C
Read 16
values
starting at
8000_0000
C
Read 16
values
starting at
8000_0000
‘C6x‘C6xHPI
HPID
DMA Aux. Ch.
8000 0000Addr.
Data
HHWIL
2
HCNTL
HPIA
8000
Memory
HD16
HPIC
1234 5678
..
1111 0000
xxx1xxx1HR/W
HSTRB
HRDY5678
Host Data 1234 56781234 5678
00000004
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Example 3: Sequential Accesses - 4
4. HCNTL[1:0] = 10b (HPID w/HPIA++)HR/W = 1Read value: HHWIL = 0
5. HSTRB6. HD = 1234
4. HCNTL[1:0] = 10b (HPID w/HPIA++)HR/W = 1Read value: HHWIL = 0
5. HSTRB6. HD = 1234
C
Read 16
values
starting at
8000_0000
C
Read 16
values
starting at
8000_0000
‘C6x‘C6x
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTLMemory
HD16
8000 0000
1234 5678
1234 5678
..
1111 0000
HPI
HPID
1234 5678
HPIA
8000 0000
HPIC
0004
xxx1xxx1HR/W
HSTRB
1234_5678Host Data
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Example 3: Sequential Accesses - 5
7. The new address in HPIA is copied to the DMA.The DMA begins to pre-fetch this address.HRDY is high until the DMA finishes.
7. The new address in HPIA is copied to the DMA.The DMA begins to pre-fetch this address.HRDY is high until the DMA finishes.
C
Read 16
values
starting at
8000_0000
C
Read 16
values
starting at
8000_0000
‘C6x‘C6x
DMA Aux. Ch.
Addr.
Data
HHWIL
2
HCNTLMemory
HD16
8000 0000
1234 5678
1234 5678
..
1111 0000
HPI
HPID
1234 5678
HPIA
8000 0000
HPIC
0004
xxx1xxx1HR/W
HSTRB
1234_5678Host Data
8000 0004
1111 0000
HRDY
0008
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HPI Pin Summary
‘C6x‘C6xHostHostHCNTRL[1:0]HHWILAddress
HR/WR/W
HDS1HDS2HCS
DATASTROBES
HASALE
HBE[1:0]BE
HRDYReady
HINTINTERRUPT
HDData[15:0]
HSTRB
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Interface Example
‘C6x‘C6xMC68360MC68360
HCNTRL[1:0]
HHWIL
HR/WR/W
HDS1HDS2
HCS
DSACK1
HAS
HBE[1:0]
HRDY
HINTIRQx
HD[15:0]Data[31:16]
A[3:2]
A[1]
DSACK0 Vcc GND
CSx
GNDVcc
Vcc
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HPI Hardware Overview Setup Control and Address Writing 32-bits Reading 32-bits Sequential Accesses
Optional Discussions
Objectives
Control Register (and CSL for HPI)
Expansion Bus (XBUS)
Next Chapter
17. Wrap Up
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HPI Hardware Overview Setup Control and Address Writing 32-bits Reading 32-bits Sequential Accesses
Optional Discussions
Objectives
Control Register (and CSL for HPI)
Expansion Bus (XBUS)
Next Chapter
17. Wrap Up
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