•Homework 4 Questions •Combinational Logic Components ...

CMSC 313 Lecture 19

• Homework 4 Questions

• Combinational Logic Components• Programmable Logic Arrays

• Introduction to Circuit Simplification

UMBC, CMSC313, Richard Chang <[email protected]>

CMSC 313, Computer Organization & Assembly Language Programming, section 0101Fall 2003 Homework 4

Due: Thursday, November 6, 2003

1. (10 points) Question 3.8, page 96, Murdocca & Heuring

2. (10 points) Question 3.9, page 96, Murdocca & Heuring

3. (20 points) Read the instructions on how to run the DigSim digital simulator on the course web page:

http://www.csee.umbc.edu/~chang/cs313.f03/digsim-info.shtml

Using DigSim, wire up the following circuit diagram, play with the switches, create a text box withyour name, and save the circuit diagram. (This is the same as the circuit we used in the in-class lab.)

The file which has your circuit diagram should be a plain text file that starts with something like:

# Digsim file

version 1 0

describe component TwoNandPort

pos 23 13

Use a text editor to look at the file and make sure that the file is not empty and has some data similarto the above. Next, use DigSim to load the file and make sure that this still works. If all is well, submitthe circuit file using the Unix submit command as in previous assignments. The submission name forthis assignment is: digsim0.The UNIX command to do this should look something like:

submit cs313_0101 digsim0 xor.sim

Last Time & Before

• In-class lab: next time Tuesday 11/18

• Half adders & full adders• Ripple carry adders vs carry lookahead adders

• Propagation delay


Appendix A: Digital LogicA-26

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring

Digital Components• High level digital circuit designs are normally created using col-

lections of logic gates referred to as components , rather than us-ing individual logic gates.

• Levels of integration (numbers of gates) in an integrated circuit(IC) can roughly be considered as:

• Small scale integration (SSI): 10-100 gates.• Medium scale integration (MSI): 100 to 1000 gates.• Large scale integration (LSI): 1000-10,000 logic gates.• Very large scale integration (VLSI): 10,000-upward logic

gates.• These levels are approximate, but the distinctions are useful

in comparing the relative complexity of circuits.



Multiplexer

0011

0101

A B

D0

D1

D2

D3

FD0

A

D1

D2

D3

B

F

0001

1011

F = A B D0

+ A B D1

+ A B D2

+ A B D3

Dat

a In

puts

Control Inputs



AND-OR Implementation of MUX

F

A B

D0

D1

D2

D3



MUX Implementation of Majority• Principle: Use the 3 MUX control inputs to select (one at a time)

the 8 data inputs.

A C

F

000001

010011

B

100101

110111

00

01

01

11

00110011

01010101

B C

00001111

A

00010111

M



4-to-1 MUX Implements 3-Var Function• Principle: Use the A and B inputs to select a pair of minterms.

The value applied to the MUX data input is selected from {0, 1,C, C} to achieve the desired behavior of the minterm pair.

A B

F

00

0110

11

0

1C

C

00110011

01010101

B C

00110110

F

00001111

A

0

1

C

C



Demultiplexer

F0

A

F1

F2

F3

B

00

0110

11

D

F 0 = D A B

F 1 = D A B

F 2 = D A B

F 3 = D A B

00110011

01010101

A B

00001000

F0

00000100

F1

00000010

F2

00000001

F3

00001111

D



Gate-Level Implementation of DEMUX

A B

F0

F1

F2

F3

D



Decoder

D0

A D1

D2

D3

B

0001

1011

0011

0101

A B

1000

D0

0100

D1

0010

D2

0001

D3

D3 = A BD1 = A B D2 = A BD0 = A B

Enable

Enable = 1

0011

0101

A B

0000

D0

0000

D1

0000

D2

0000

D3

Enable = 0



Gate-Level Implementation of Decoder

A

B

D0

D1

D2

D3

Enable



Decoder Implementation of MajorityFunction

A

CM

000001

010011

B100101

110111

• Note that the en-able input is notalways present.We use it whendiscussing de-coders formemory.



Priority Encoder• An encoder translates a set of inputs into a binary encoding.• Can be thought of as the converse of a decoder.• A priority encoder imposes an order on the inputs.• Ai has a higher priority than A i+1

0111000000000000

0100111100000000

F0 F1

0000000011111111

A0

0000111100001111

A1

0011001100110011

A2

0101010101010101

A3

F0

F1

0001

1011

A0

A1

A2

A3

F0 = A0 A1 A3 + A0 A1 A2

F1 = A0 A2 A3 + A0 A1



AND-OR Implementation of PriorityEncoder

F0A1

A2

A3

F1

A0



ProgrammableLogic Array

F0

A B C

Fuses

F1

AND matrix

OR matrix

• A PLA is acustomizable ANDmatrix followed bya customizableOR matrix.

• Black box view ofPLA:

ABC

PLAF0

F1



SimplifiedRepresentation

of PLAImplementation

of MajorityFunction

F0

A B C

F1

(Majority)

A B C

A B C

A B C

A B C

(Unused)



Full Adder

00110011

01010101

Bi Ci

00001111

Ai

01101001

Si

00010111

Ci+1

Fulladder

Bi Ai

Ci

Ci+1

Si



PLA Realizationof Full Adder

Sum

A B Cin

Cout

Appendix B: Reduction of Digital LogicB-3


Reduction (Simplification) of BooleanExpressions

• It is usually possible to simplify the canonical SOP (or POS)forms.

• A smaller Boolean equation generally translates to a lower gatecount in the target circuit.

• We cover three methods: algebraic reduction, Karnaugh map re-duction, and tabular (Quine-McCluskey) reduction.



Karnaugh Maps: Venn Diagram Rep-resentation of Majority Function

• Each distinct region in the “Universe” represents a minterm.

• This diagram can be transformed into a Karnaugh Map .

ABC

ABC’ AB’CAB’C’

A’BC

A’BC’ A’B’C

A’B’C’B

A

C



K-Map for Majority Function• Place a “1” in each cell that corresponds to that minterm.

• Cells on the outer edge of the map “wrap around”

A B C FMinterm

Index

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

0

1

2

3

4

5

6

7

1

0

0-side 1-side

0

A balance tips to the left or right depending on whether

there are more 0’s or 1’s.

00 01 11 10

0

1

ABC

1

11 1



Adjacency Groupings for MajorityFunction

• F = BC + AC + AB

00 01 11 10

0

1

ABC

1

11 1



Minimized AND-OR Majority Circuit

• F = BC + AC + AB

• The K-map approach yields the same minimal two-level form asthe algebraic approach.

F

A B C



K-Map Groupings• Minimal grouping is on the left, non-minimal (but logically equiva-

lent) grouping is on the right.

• To obtain minimal grouping, create smallest groups first.

00 01 11

1

01

11

11

10AB

1

CD

10

00

01 11

01

11

10CD

10

00

00AB

1

1

1

1

1

2

3

4

1

11

1

1

1

1

1

2

4

51

F = A B C + A C D + A B C + A C D

F = B D + A B C + A C D + A B C + A C D

3

Richard Chang

Example Requiring More Rules

0000

1100

01

00

10

11

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10




K-Map Corners are Logically Adjacent

00 01 11

1

1

1

01

11

1

1

1

1

1

10AB

1

CD

00

10

F = B C D + B D + A B



K-Maps and Don’t Cares• There can be more than one minimal grouping, as a result of

don’t cares.

00 01 11

1

01

11

11

10AB

1

CD

10 d

00 d

F = B C D + B D

01 11

1

01

11

11

10

1

CD

10 d

00 d

00AB

F = A B D + B D

1 1

Gray Code

• Two bits: 00, 01, 11, 10

• Three bits: 000, 001, 011, 010, 110, 111, 101, 100• Successive bit patterns only differ at 1 position

• For Karnaugh maps, adjacent 1’s represent minterms that can be simplified using the rule: ABC’ + A’BC’ = (A + A’)BC’ = 1 BC’ = BC’

00 01 11 10

0

1

ABC 11

A

B

1 1


Karnaugh Maps

Implicant: rectangle with 1, 2, 4, 8, 16 ... 1’s

Prime Implicant: an implicant that cannot be extended into a larger implicant

Essential Prime Implicant: the only prime implicant that covers some 1

K-map Algorithm (not from M&H):

1. Find ALL the prime implicants. Be sure to check every 1 and to use don’t cares.

2. Include all essential prime implicants.

3. Try all possibilities to find the minimum cover for the remaining 1’s.


K-map Example

1010

0dd0

11

10

10

1d

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C

1010

0dd0

11

10

10

1d

00 01 11 10

00

01

11

10

ABCD 11

A

B

D

C

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

A’B + AC’D + AB’D’


Notes on K-maps

• Also works for POS

• Takes 2n time for formulas with n variables

• Only optimizes two-level logicReduces number of terms, then number of literals in each term

• Assumes inverters are free

• Does not consider minimizations across functions• Circuit minimization is generally a hard problem

• Quine-McCluskey can be used with more variables

• CAD tools are available if you are serious


Next Time

• Continue Circuit Simplification

• Homework 4 due• Homework 5 assigned


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