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SILICON WAFER PROCESSING

Objective

To provide general description about silicon wafer processing steps and to share the knowledge about semiconductor industry mainly focused on wafer fabrication process.

Overview

As a second year student of Singapore Polytechnic, I , Kyaw Soe Hein, is attached to "SINGAPORE INSTITUE OF MANUFACTURING TECHNOLOGY" Research Institute during my Industrial Training Programme (ITP) , and was inspired by working environment to conduct research on silicon wafer processing . Thus, this work is done during this six weeks period, mainly sourced by Internet. The report will describe in sequential steps start from raw material ,silicon, to the end "Integrated Circuit". Many illustrations are also provided for clear understanding.

Acknowledgement

Truly thankful to my special Supervisor and Liaison Officer, Mr. Kong Chun Jeng & Mr. Yep Chin Hooi , for their continuous support and guidance during this ITP. I was inspired by them to learn more and ITP become beneficial. And thanks goes to the attached department for warm hospitality as well.

Kyaw Soe Hein

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Tables of Contents Page No.

INTRODUCTION

History of electronics...................................................................................3

PREPARATION OF WAFER

Wafer growth and slicing process................................................................5

Thickness sorting.........................................................................................8

Flatness testing.............................................................................................9

Final electrical properties testing................................................................10

SILICON WAFER FABRICATION PROCESS

Photolithography.........................................................................................14

Etching Process............................................................................................15

Implanting mask...........................................................................................17

Annealing.....................................................................................................19

INTEGRATED CIRCUIT PACKAGING

Die Attach....................................................................................................20

Encapsulation................................................................................................20

Lead Finishing..............................................................................................21

Final testing..................................................................................................21

CONCLUSION

Aspects of electronics....................................................................................22

Kyaw Soe Hein

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Introduction

History of electronics

No one had ever imagined that the glory of electronics will be brighten like in this modern day until as recently as 1980. Computers and data system become to play a role in our daily lives and have great impact on us as far as one wouldn't dare to imagine how they need to work without computers and data system. Mankind has been using the fusion of computer system and electronics technology in very demanding rate and yet, it is increasing in exponential rate and Moore's Law can be applied in computer usage. The daily use of electronic components such as phone, MP4, camera, and automobile has increased dramatically along with the drop in price and density. The Electronics technology has shaped the world by itself into modernized and technology hub.

The semiconductor industry reflects the extraordinary revolution in both Material Science and data storage and processing technology. Along with it, the silicon wafer which is the major components of all Integrated circuit has evolved as a vital organ for semiconductor industry. Every electronic device you touch surprised of it. It is true that most of the leading research institutions run into rat race and conduct experiments on Silicon wafer has pushed its compatibility and application beyond the imagination - so called nanotechnology. Therefore, it is undeniable fact that Silicon Processing is becoming something that fairly important topic of our modern age.

The processing of silicon wafer to Integrated circuit involved a lot of complicated procedures including micromachining and loads of chemistry and physics protocol. Silicon as we all know - mainly found in dust, and sand is un-reactive element. Therefore, it is not easy job to make it electrically reactive which deemed to be out of questions for few decades ago. In order to alter its properties, both inert and toxic chemicals are used to bring about different and unusual conditions. These conditions are manipulated by plasma-state(ionized) elements and RF ( Radio Frequency ) Energy. From 150mm,200mm,300mm diameter of thin, round wafers of silicon crystal, the process will lead to the creation of layers of wafers to produce thousands of electronics devices at minute size which are confused together as Integrated Circuits(ICs) . The IC which is size only half-inch today would have occupied the 100 inches in the old time to function the same because the electronics components like (Transistor, resistors, capacitors and alike..) were only available in discrete units.

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The conditions under which these processes, transforming silicon to be used as Integrated circuits, need absolute absence of contamination and very delicate caring. Thus, the processes need to be done in vacuum environment where foreign particles and specific contaminants are precisely controlled. Therefore, the silicon wafer processing is fundamental on clean room technology and procedures, applying knowledge on vacuum system, theory of gas, and handling tools for highly contaminants-free objects.

Today, only thirty years later, the semiconductor technology has gradually developed by mankind in term of its capability of data processing and storage system that are now in mainstream. Inventiveness and creativity, comes with the great strides in process control, workforce management, leading research, are factors contributing daily on reducing the size of electronics component smaller and further smaller. We are foreseeing that biochemically based devices will be smaller, the heat generated will be much lower, and of course, they executes and performs function in incredible speed. If our world would go on with this rate of technology development, our world would be wonderland which replete ,not with colorful flowers and funny creatures, but with advanced and amazing semiconductor-devices which will create the golden history of today's future.

Kyaw Soe Hein

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Preparation of Silicon Wafer MediaThe following is the steps required to transform raw material, silicon, to wafer media to be ready to make IC. Wafers are checked at every sequential processes to identify the manufacturing defects in order to prevent unsatisfactory conditions for making new ICs. Thus, the defected materials can be removed from the process and sort the wafer into batches of uniform thickness at the point of final inspection.

Table 1. Thermal properties of Silicon

Crystal Growth and Wafer slicing Process

The very first step in developing the wafer is crystal Growth by chemical means. It is to obtain the formation of large, perfect granular silicon crystal mainly done by seed crystallization method. Basically, in this method, the crystal is grown from a 'seed crystal' which is perfect crystal. The silicon is supplied in granular powder form, then melted in crucible. Subsequently, the seed crystal that described above is immersed into the molten silicon, then withdrawn.

Kyaw Soe Hein

Fig.1 Molten Silicon

Thermal Properties of Si

Thermal Conductivity(Solid) / (liquid)

1.412 W/cm-K4.3 W/cm-K

Thermal Diffusivity 9 cm^2/s

Molar Heat Capacity

20.00 J/mol-K

Melting Point 1683K

Boiling Point 2628K

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Step 1: Obtaining the sand

The sand used for the wafer process is mostly shipped from the beaches of Australia where good form of silicon is present. The sand need to be super facially clean and the normal sand found in general won't be good for wafer fabricating. Also, it need to be fine and meet standard ISO 14588 grades.

Step 2: Preparing the Molten Silicon Bath

The source of silicon is from sand(SiO2) , sand, which was put into crucible and it's heated to around 1600 Degree C - just above the melting point.

Step 3: Making the Ingot

This dominant technique for this process is known as Czochralski Method. It is named after the Polish Scientist Jan Czochralski discovered the method in 1916 while he was studying of the rate of crystallization of metal. In this method, a pure silicon seed is placed into the molten sand bath. It is pulled out slowly and gently as it is rotated, resulting in a pure silicon cylinder called an ingot.

Kyaw Soe Hein

Fig.2 Seed Crystallization

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The purpose of this process is to provide good clean surface for later processes. In epitaxial cylinder, the layers of silicon are grown on top of wafer, which produce much better quality than the apparent damaged or unclean layer. This epitaxial layer is where the actual processing will be done.

The temperature variables and the rate at which the cylinder is pulled out determine the size of diameter of epitaxial silicon. When the desired length of ingot obtained, then it is grounded to a uniform surface and diameter using mechanical lathe.

Kyaw Soe Hein

Fig.3 Completed Ingot in the shape of epitaxial silicon

Fig 4. Wafer Notch

Each of the wafer is given a notch to set orientation to be used in later process.

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Step 4: Preparing the wafer

After it is grounded to a uniform diameter, they proceed to be cured with epoxy resin before slicing. Then, ingots are mounted to carbon block machine for cutting. Wafers are sliced from the ingot using both ID(Diamond) and Wire type saws. The Diamond saw can produce only single wafer at a time. However, the wire saws are more efficient as they are able to slice off the entire ingot at once, producing multiple wafers. Immediately after the slicing, the "as -cut" wafers are cleaned in a series of chemical baths to remove any residual slurry. Then, a series of refining steps are carried out to make them stronger and flatter.

Thickness Sorting

Followed by slicing, the wafers are sorted according to their thickness so that it would be more efficient in next process, lapping . In the mean while, the manufactures can also observe the defects trends due to slicing process. Thus, the possible measurement can be taken to increase productivity in wafer slicing.

Lapping & Etching Process

Lapping removes the abrasive surface silicon which has been cracked or damaged by the slicing process, and it ensures the flat surface. Then, wafers are etched by chemical means to remove any remaining cracked or damaged silicon from Lapping process for further smoothness.

Kyaw Soe Hein

Fig 5. Wafer thickness sorting machine

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Flatness checking

Following Lapping & etching process, the wafers are measured for flatness to investigate the defects trend produced by previous process, lapping & etching. Still, wafers are sorted by thickness on automated basis so that the productivity for next process, polishing, can be leveraged.

Polishing Process

Polishing is the process in which the wafer is smoothen its uneven surface left by lapping and etching process and makes the wafer mirrored, super-flat surface required for the fabrication of today's advanced semiconductor devices. Basically, it is an automated, multi-step process using ultra-fine slurry and pressure against two rotating surfaces ,which is quite similar to lapping.

This is accomplished by chemical-mechanical polishing process to support optical photolithography.

Kyaw Soe Hein

Fig 6. Wafer Polishing Fig 7. Wafer Stack

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Final Dimension & Electrical Properties Qualification

After all the above processes has been carried out, the wafers undergo a final test so that manufactures can check if the wafers obtained are met the customer specifications and needs. They are tested for flatness, thickness, resistivity and type. The electrical properties of wafers can be tested with examina probe which is easily found in industry. By carrying out the final test, defect trend information can be evolved. Thus, the wafer manufactures can taken necessary improvement on yield and process improvement regarding surface defects, scratches and particles defect.

Kyaw Soe Hein

Fig 8. Wafer Fabrication Facility

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Silicon Wafer Fabrication Steps

Silicon wafers are then ready to manufacture into semiconductor devices. Turning silicon into memory chips is like implementing something from dream as this exciting and meticulous procedure involve much effort of engineers, chemists, physicist and metallurgist. The very first step from silicon to circuit is the creation of a pure single-crystal cylinder or ingot of six or eight inches diameter. These are then sliced into very thin, highly polished wafers less than 1/40 of an inch thick. It is undeniable that the procedure is so amazing. The circuit elements( transistors, capacitors and resistors) are built in layers on the silicon wafer. Hundreds of memory chips are etched onto the wafer though the processor chips will only fit 10 to 50 places on a wafer.

There comes the part of ( CAD ) computer aided design systems as they develop most chips design today. These programs provide the features like testing and simulation. Therefore, one advantage is that the circuit can be designed in software before they are actually developed on real one. After that, the glass photo-masks are made - one mask for each layer of the circuit. The process involving glass photo-masks are know us photolithography.

Fabrication

The manufacturing of semiconductor memory chip is done in special environment- free from contaminants as the circuitry is relatively very small even the tiny dust can damage the circuit. In typical, clean room class 1 and class 10 are mostly used. Clean room has typically low level of pollutants such as dust, airborne microbes, aerosol particles and chemical vapor. Clean room are classified according to the particles present per cubic feet and the standard is set by ISO.

Following is the table of classification of cleanroom class.

Kyaw Soe Hein

Fig 8. Designing Circuit with the help of software

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Table 1. US FED STD 209E Clean room Standards

BS 5295 cleanroom standards

  maximum particles/m³

Class ≥0.5 µm ≥1 µm ≥5 µm ≥10 µm ≥25 µm

Class 1 3,000

Class 2 300,000 2,000 30

Class 3 1,000,000 20,000 4,000 300

Class 4 200,000 40,000 4,000

The cleanroom has filtering system of air which is continuously filtered and circulated in and out of clean room and furthermore, the employees working inside cleanroom has to wear dust free clothing, gloves, and masks to keep the air at optimum cleanness.

The machine shown on the right is the outline of modern semiconductor etch machine. It consists of the wafer handling system which accepts wafers from the factory materials handling systems and aligns them for processing in the etch machine and moves them into the main part of the machine. When wafers move into the process part of the machine, they are normally operated in vacuum, with extremely low level of particles ( Class 1).

Kyaw Soe Hein

Fig.9 Outline of etching machine

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Extra care is given to this system as the extremely tiny particle can affect the wafer and damage numbers of Integrated Circuit on it, losing hundreds of thousands of dollars.

The large circular area is the transferring part of the machine, moving wafers to process chambers for different processes. The chambers are configured individually to treat wafer with desired etching process. It is notable that a signal wafer undergoes a lot of processes to have complex layers of semiconductor and furthermore, insulation material is needed to produce the desired circuitry.

Wafer fabrication process steps can be grouped into these basic procedures described below.

DiffusionA layer of materials such as oxide is grown or deposited onto the wafer.

Coke/Bake It is the coating of resistive, protective light layer and curing it in the place.

Align A reticule is placed on the wafer while the Ultraviolent goes through its opening, hence creating

the pattern onto the wafer.

DevelopIt is when the developing of the resist occur and the unnecessary resist are washed away.

Dry EtchIt removes the oxide which is not protected by resist.

Wet etch & clean

Kyaw Soe Hein

Fig. 10 Align of pattern on wafer

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The remaining resist is washed away to reveal the patterned oxide layer. Then the wafer is clean. This process is repeated up to 18 times to create the various layers necessary for each part's circuitry.

Process steps in details ( Photolithography)

The wafers are undergone the numbers of photolithography processes in sterile environment. This process is repeat once for each mask for every single layers. Each layer means the different parts of the transistors, capacitors, connectors comprising the complete integrated circuit and defines the circuitry pattern for each layer on which device is fabricated.

At the beginning, the silicon wafer is protected by a thin glass layer followed by nitride layer. In fact, glass is silicon compound(Silicon dioxide) ,hence it is obtained by exposing wafer to oxygen. However, it is needed to be exposed to oxygen at 1600 Degree C or higher and 1 hours or more depending on thickness of glass layer required. Higher the heat energy i.e. higher degree, the faster the rate of reaction (oxidation).

Next step is to undergo photolithography process . Firstly, the wafer is coated uniformly coated with a thick light-sensitive liquid called photoresist. It is applied while the wafer is spinning. The spin coating runs at 1200 to 4800 rpm for 30-60 seconds and produce 0.5 to 2.5 micrometer thick.

The photo resist-coated wafer is then prebaked to clear off excess photoresist solvent, typically at 90 - 100 Degree C for 30 - 60 seconds.

After that, the photoresist wafer is exposed to a pattern of intense light, ultraviolet light. However, they are two kinds of photoresist, positive type and negative type with different properties. Positive type , the most common type , becomes soluble in the developer while negative type becomes insoluble in the developer. This property allows to wash away unnecessary resist.

Before developing, PEB (Post Exposure Baked) is performed to reduce "standing wave" phenomena caused by the constructive and destructive pattern of the incident light. This phenomena happens as a result of interference between two waves travelling in different direction.

Kyaw Soe Hein

Fig. 11 Concept of Photolithography

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Then, portions of the wafer to be exposed are carefully selected by aligning the a mask between the ultraviolet light source and the wafer. The light passes through the clear portion of the mask and exposes the remaining photoresist

.Direct Wafer Stepping (DWS) is the number one method used in industry. In this method , the mask can be placed a bit far away from wafer and through a series of optics, the image is placed onto the wafer. The mask can be larger than the final pattern and along with the manipulation of optical and mechanical process, the better resolution of imprint can be obtained on wafer. Nowadays, the imprint image on wafer can go up to nano-scale.

When photoresist are exposed to ultraviolent light, they become hardens and impervious to etchants This chemical change allows to remove the unexposed portion of photoresist while leaving exposed ones in subsequent developer solution.

Etching the wafer surface

Immediately after the photolithography, the etching process is carried to remove unwanted material from wafer. Etching is critically important and every wafer has to undergo many etching process before it is complete. For many etching steps, part of the wafer is protected from the etchant by a "masking" material which resist etching. These "masking" material is photoresist which had been patterned from the photolithography process. There are several ways to do etching, out of which, dry etching, wet etching and plasma etching are common.

Kyaw Soe Hein

Fig. 12 Nano imprinting on wafer

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Etching will leave behind the exact design of the mask on the wafer. The hardened photo resist like silicon nitride ,then, will be removed by another chemical.

The two fundamental type of etchants are liquid phase(Wet) and plasma phase(Dry). Each of these in turns exists in varieties.

Wet Etching

Basically, wet etching is done by the use of chemicals. The bench of wafers is dipped into the acid, normally buffered hydrofluoric acid which is used to etch silicon dioxide over silicon substrate and the exposed area will be cleared off away. In terms of low price and abilities of processing many wafers quickly, wet etching is good. However, for some smaller critical geometries that we use today's semiconductor industry, wet etching is lack of capability.

Dry Etching

Except from the etching methods using chemical solvents, any other methods using gases are considered as dry etching. It is different from wet etching is that it enhance the production of tiny size critical geometries that we need in today's industry.

In industry, VLSI ( Very-large-Scale-Integration) avoid wet etching, applying plasma etching. In plasma etching, the gas that is subjected to the intense electric field to generate the plasma state of matter is used. The source gas contains molecules rich in chlorine or fluorine. For instance, carbon tetrachloride etches silicon and aluminium, and trifluoromethane etches

Kyaw Soe Hein

Fig. 13 Dry Etching

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silicon dioxide and silicon nitride. The electric field is produced with coils that are wrapped around the chamber and exposed to a high level of RF source. There are two different types of operation depends on the shape of the chamber used. One consists of barrel type chamber where wafers are sitting up while the gas is flowed over the wafers and out through an exhaust pipe. The second consists of parallel plates, giving out electric field instead of coils around the chamber. The plasma etching is very reactive and provide effective etching of exposed surface even in critical geometry. However, it is a point that this process needs extra-care as RF radiation can damage the wafers.

Another etching method is Reactive Ion Etching, works at lower pressure and uses both physical and chemical means to etch the wafer. A parallel plate (RIE) system consists of a cylindrical vacuum chamber, with a wafer platter situated in the bottom portion of the chamber. The wafer platter is electrically grounded. Gas enters through small inlets at the top of the chamber and exist through the bottom, suction created by vacuum pump. Gas Pressure is usually maintained in a range between few millitorr and few hundred millitorr.

Anisotropic & Isotropic Etching

Isotropic etching is the problem that results from chemical etching and some forms of dry etching. The result is that the etch material etch to the side laterally as well as straight down. This can cause some of the material under the patterned resist to be etched away, resulting in undercutting and poor image accuracy. Anisotropic etching occurs in most form of dry etching. In this process there is no lateral etching so an exact representation of the pattern is etched onto the wafer. Anisotropic etching is more desirable because there can be problems in maintaining the desired electrical characteristic if there is lateral etching as well as vertical etching.

Implant/ Masking steps : Diffusion & Ion implant

Kyaw Soe Hein

Fig. 14 Anisotropic & Isotropic Etching

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Electrical characteristics of selected area on the developing integrated circuit are changed by implanting energized ions( dopants ) into the areas not protected by resist or other layer. Dopant is an impurity element added to a crystal lattice in low concentrations in order to alter optical/electrical properties of the crystal.

Doping, the addition of a dopant to a semiconductor, has the effect of shifting the "Fermi level" within the material. This results in a material with predominantly negative(N-type) or positive(P-type) charge carries depending on the dopant species. Pure semiconductors altered by the presence of dopants are known as "extrinsic semiconductors" . Dopants are introduced into semiconductors in a variety of techniques: solid sources, gases, spin on liquid and ion Implanting and surface diffusion.

Fermi level is an energy that pertains to electrons in a semiconductor.

Boron, Arsenic, phosphorous, antimony, among other substances, are commonly used dopants in the semiconductor industry.

The implanting dopants can damage to the wafer , so heating process known as annealing is used to reduce any damage to wafers.

Diffusion

Diffusion is done in a furnace with a flow of gas running over the wafers. It is not selective so the photolithography process and patterning need to be done before this step. In fact, diffusion is very similar to oxidation except it uses different gas other than oxygen.

Ion Implantation

Ion implantation is a process by which ions of a material can be implanted into another solid, thereby changing the properties of the solid. The implantation typically consists of an ion source, an accelerator where the ions are electrostatically accelerated to a high energy and hit the target . It is different from the diffusion in a way that diffusion uses the natural tendency of gas flowing from high to low pressure while ion implantation shoots the desired dopant ions into the wafer. However, diffusion has one advantage that it can process several wafers at the same time while Ion implantation can only process a single wafer at a time.

Kyaw Soe Hein

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Then, the next step in "Drive In" process after the ions have been implanted into the wafer. In this step the wafer is heated to make the ions go deeper into the wafer.

Annealing

The heating process is required again as the above processes( especially ion implantation ) is highly possible to damage the wafers. During this final stage, the wafer is heated so that crustal lattice structure of the wafer will repair itself. Furnace anneals are used for this process and are performed by equipment especially built to heat semiconductor wafers. Furnaces are capable of processing lots of wafers at a time but each process can last between several hours and a day.

The finished wafer is an intricate sandwich of n-type and p-type silicon and insulating layers of glass and silicon nitride. The first few mask operation means to construct the circuit elements (transistors, resistors, and capacitors), the following operations to connect them together.

Then, the insulating layer of glass (called BPSG) is deposited and a contact mask is used to define the contact points or windows of each of the circuit elements. BPSG stands for Boronphosphosilicate Glass that includes additives of both Boron and Phosphorous. After the contact windows are etched, the entire wafer is covered with a thin layer of aluminium in a

Kyaw Soe Hein

Fig .15 Principle of Ion Implantation

Fig.16 Furnace for semiconductors

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sputtering chamber. The metal mask is used to define the aluminium layer leaving a fine network of thin metal connections or wires.

An insulating layer of glass and silicon nitride act as a protective layer for wafer and protects it from contamination during assembly. This kind of protective coating is called the passivation layer, the spontaneous formation of a hard non-reactive surface film that inhibits further corrosion. The final mask and passivation etch removes the passivation material from the terminals, called bounding pads. The bonding pads are used to electrically connect the die to the metal pins of the plastic or ceramic package.

Before cutting the wafer into individually chips, every IC is tested and functional and non-functional chips are identified and mapped into a computer data file. Then, the wafer is cut into individual chips by a diamond saw. Nonfunctional chips are discarded and the rest are sent on to be assembled into plastic packages.

Integrated Circuit PackagingIntegrated circuit packaging is the final stage of semiconductor device fabrication, followed by testing. It is also known as encapsulation or seal , as it is the last step of this packaging process.

Die attach/ Wire bond

Before encapsulation, the die are mounted on lead frames, and thin gold wires connect the bonding pads on the chip to the frames to create the electrical path between the die and lead fingers. The quality assurance test is then carried out to push produced chips to their extreme limits of performance to ensure high quality, reliable die and to assist engineering with product and process improvements.

Kyaw Soe Hein

Fig. 16 Thin gold wires creating electrical path

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Encapsulation

It is often the last stage of IC packaging ( semiconductor package assembly ) in semiconductor device fabrication. The integrate circuit die is being encapsulated with ceramic, plastic, or epoxy to prevent physical damage or corrosion. During the process, lead frames are placed onto mold plates and heated. Molten plastic material is pressed around each die to form its individual package. The mold is opened, and the lead frames are pressed out and cleaned.

Lead Finishing

There is, however, more processes to increase the conductivity and provide a clean consistent surface for surface mount applications. The process is called electroplating in which the encapsulated frames are "charged" while submerged in a tin/lead ion solution. The ion are attracted to electrically charged lead frame, hence creating a uniform plated conductive surface, increasing the conductivity of the chips.

Trim & Form

Another process is called Trim & Form, where lead frames are loaded into trim-and-form machines where the leads are formed step by step until finally the chips are separated from the frames. Then, each of the chips is put into anti-static tubes for handling and transportation to the test area for final testing. The form and shape are served according to the customer's needs.

Kyaw Soe Hein

Fig. 17 IC Circuits

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Final testing

For the very last time, testing is carried out to attain the very best quality. Each memory chip is tested to see how fast it can store or retrieve information, including the high temperature burn-in Micron's proprietary AMBYX ovens which test the circuitry of each chip, ensuring the quality and reliability. This monitored burn-in feedback throughout the process, allowing identification and correction of manufacturing problems. The completed package are inspected, sealed and marked with a special ink to indicate product type, data, package code and the speed. Finally, the finished goods are shipped to computer, peripheral telecommunication, and transportation Customers throughout the world.

Conclusion

Aspects of Electronics

Today's one of the biggest market is the electronics entertainment area which includes PSP, MP4, mobile phone, CD player and of course, computer. They are booming in incredible speed along with the dramatic increase in users around the world. They become just not like normal devices. It is life-style that these electronics devices offer.

Creativity and design are the key points of promoting gadgets today. Moreover, people become more furious about data system. No one would like to use slow speed processor. Therefore,

Kyaw Soe Hein

Fig. 18 iPod gold

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manufactures try to upgrade their technology, conducting research and compete each other for a place in market. This has made electronics technology more advanced and it is too likely that this trend will continue over next many years.

One can't live without electronics devices. As long as they are people out there, there will be used of electronics. In other words, electronics will not disappear from our world. And I do strongly believe that we should thank today's electronics technology and think how it make you at ease, just by looking around you.

Kyaw Soe Hein