Hiromi Suda Canon Inc. [email protected] October 14 th, 2015.

Hiromi SudaCanon [email protected] 14th, 2015

Suda – Canon

IWLPC 2015

1. Introduction of 3D/2.5D technology

2. Lithography tool for 3D/2.5D integration

3. Challenges related to FOWLP 4. Summary

Suda – Canon

IWLPC 2015

3D (by TSV) 2.5D (by Si Interposer)

3D/2.5D integration technology is an innovative approach to high-density integration

Si Interposer

MemoryProcessor

Memory

Under the present conditions◦ 3D/2.5D integration cost is still very high◦ 3D/2.5D adoption is limited to high performance

products

Suda – Canon

IWLPC 2015

In FOWLP, semiconductor chips are connected using RDL, but without the use of a Si interposer

FOWLP overcomes pin count limitations by expanding RDL patterns to larger than the size of the chip

MoldProcesser Memory

Suda – Canon

IWLPC 2015




Suda – Canon

IWLPC 2015

Equipped with functions for Advanced Packaging

Chuck for warped wafer

Bonded wafer handling

Wafer

Special ItemsWafer Edge Shielding

Chemical Filter

Outgas Exhaust Unit

Pellicle Particle Checker

Wafer Edge Exposure

Through Si Alignment

Alignment

Unique Pattern TVPA

Dual Side Metrology

Exposure

Optimal NA lens

Wide Band i-Line Filter

Suda – Canon

IWLPC 2015


Chuck for warped wafer Bonded wafer handling

Wafer


Chemical Filter

Outgas Exhaust Unit


Wafer Edge Exposure


Alignment

Unique Pattern TVPA

Dual Side Metrology

Exposure

Optimal NA lens


Suda – Canon

IWLPC 2015

Focus

FPA-5510iV (NA0.18), 1.5 µm Hole

FPA-5510iZ (NA0.57), 2.5 µm Hole

-6 µm -4 µm -2 µm 0 µm 2 µm 4 µm 6 µm

Resist: P-W1000T-PMTokyo Ohka Kogyo (TOK), t = 5.5 µm

Suda – Canon

IWLPC 2015

FPA-5510iV achieves large common DOF◦ Reduction optics◦ New chuck system◦ Die-by-die tilt & focus

-20

-10

0

10

20

30

40

50

-15 -10 -5 0 5 10 15

12.2μm

Focus (μm)

ΔC

D (

%)

FPA-5510iV Target 1.0 μm L/SImage Field 52 ×34 mmMeasurement points: 9 points

Measurement points

52 mm34

mm

Suda – Canon

IWLPC 2015



Wafer


Chemical Filter

Outgas Exhaust Unit


Wafer Edge Exposure

Exposure

Optimal NA lens



Alignment

Unique Pattern TVPA

Dual Side Metrology

Suda – Canon

IWLPC 2015

Through Si Alignment Scope “TSA-Scope” with IR

◦ Both front and back-side alignment is possible◦ Suitable for via-last processes

Tra

nsm

itta

nce o

f S

i w

afe

r (%

)

Wavelength (nm)

FEOL

Through Si detectionwith IR-light

ObservedAlignment

markThrough Si

Front surface

detection with

visible-light

Si-wafer

Suda – Canon

IWLPC 2015

112nm 95nm

Overlay accuracy with FEOL machine

Si Wafer thickness: 775 µmBack side (1st) patterning: FPA-5510iZFront side (2nd) patterning: FPA-5510iV

TSA-Scope overlay accuracy is <120 nm TSA-Scope is suitable for TSV processes

Suda – Canon

IWLPC 2015



Wafer

Exposure

Optimal NA lens



Alignment

Unique Pattern TVPA

Dual Side Metrology


Chemical Filter

Outgas Exhaust Unit


Wafer Edge Exposure

Suda – Canon

IWLPC 2015

Edge Blade

Wafer Edge Shield

Rθ

Wafer Edge Exposure

No throughput loss Variable exposure

width & position

Flexible ring-shaped shield No contamination

Exposure Area

Suda – Canon

IWLPC 2015

Wafer Edge Shield & Exposure unit can make a smooth ring area around the wafer edge regardless of the shot layout

Wafer Edge Shield

Wafer Edge Exposure

(µm)

(mm)

Bump pattern

Resist type : positive

Suda – Canon

IWLPC 2015




Suda – Canon

IWLPC 2015

Large topography◦ Issue related to fine pitch RDL patterning

Die grid error◦ Issue related to high-density interconnections

Shot area

Bonded chip

A B

A B

A B

A BA B

Rotation

ShiftMagnification

Bonding accuracychip to chip

A

BA

BA B Non-flatness

Suda – Canon

IWLPC 2015

-10

-5

0

5

10

15

20

-150 -100 -50 0 50 100 150H

eig

ht [μ

m]

Pos. [mm]

Focus gap between chips and mold region is ~20 μm Focus gap reduces focus margin for fine RDL patterning

A A’

A-A’ Cross SectionChip

Mold

20 μ

m

Sample wafer provided by Hitachi Chemical Chip Size: 10 mm x10 mm; Step size: 30 mm x 30 mm

Suda – Canon

IWLPC 2015

Original topography Focus compensation residual

Multi-channel optical Auto-Focus system is available to support RDL patterning processes◦ Performs tilt & focus measurement on every shot◦ Reduces yield loss caused by the focus gap

between die and mold

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-5

0

5

10

15

20

-150 -100 -50 0 50 100 150

Heig

ht [μ

m]

Pos. [mm]20

μm

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-5

0

5

10

15

20

-150 -100 -50 0 50 100 150

Heig

ht [μ

m]

Pos. [mm]

10 μ

m

Shot size : 30 mm×30 mm

Suda – Canon

IWLPC 2015

2μm pattern can be formed with Die-by-die tilt & focus Wafer flatness needs to be lower < 5μm for 1μm patterning

0

10

20

30

1 2 5

DO

F (μ

m)

Line Width (μm)

DOF ConditionCD Error:±5%Dose Error: 7%

Global focus

Die-by-die tilt & focus

Focus compensation residual

Suda – Canon

IWLPC 2015

Sample wafer consists of multi-chips package which two dies; die A and die B

A B

Shot size 17mm x17mm

Suda – Canon

IWLPC 2015

Die grid error will be more crucial for fine pitch RDL

Die A Placement Error

Wafer

3σ X (μm)

3σ Y (μm)

ID1 5.7 13.2ID2 14.0 10.2ID3 9.6 11.3

Wafer

3σ X (μm)

3σ Y (μm)

ID1 6.4 16.0ID2 14.6 12.1ID3 11.3 12.2

ID1 ID2 ID3

Die B

Die A

Die B Placement Error

Die grid measurement result on 3 sample wafers which manufactured in the same lot

Suda – Canon

IWLPC 2015

Global overlay error compensation is not enough… 　　◦ Grid error has many non-linear components

Wafer

3σ X (μm)

3σ Y (μm)

ID1 4.2 7.4ID2 4.9 8.6ID3 4.5 7.4

Wafer

3σ X (μm)

3σ Y (μm)

ID1 5.7 13.2ID2 14.0 10.2ID3 9.6 11.3ID1 ID2 ID3

Die A Overlay Error

We simulated how much Die A overlay error occurred after Global Alignment for Die A

Remove X,Y-mag. X,Y-rot.

Suda – Canon

IWLPC 2015

Die-by-die A lignment for D ie A can dramatically reduce overlay error for Die A

How much overlay error is there for Die B?

Die B Overlay Error

Relative position accuracy of dies in each shot is a key challenge

Wafer

3σ X (μm)

3σ Y (μm)

ID1 3.9 9.1ID2 6.3 7.5ID3 7.1 6.5

ID1 ID2 ID3

Compensated ideally in each shot

Die A

Die B

Suda – Canon

IWLPC 2015

0

2

4

6

8

10

12

14

16

18

20

Ove

rlay error

(m+3

σ) μ

m

X

Y

The stepper has an advantage for FOWLP because of wafer grid compensation

for molding & chip mounting error

Die A Die B Die A Die B Die A Die B

GlobalAlignmentfor die A

Die-by-dieAlignmentfor die A

Original

Suda – Canon

IWLPC 2015

Wafer topography in FOWLP is increased after RDL and PBO layers are layered up

RDL patterning position

Alignment mark patterning position Defocus

Die Die

Molding compound

Scribe Line

Alignment mark patterns are deteriorated due to defocus

Suda – Canon

IWLPC 2015

New alignment mark is robust for defocus Enables us to use sequential alignment tree using

cutting line alignment marks

General Mark

Suggested Mark

30 μm

30 μm15 μmHole

Stable image

xyz主光線像面座標： 0.000000 0.000000 0.000000

[μ m]ピッチメリサジ： 0.239804 0.239804

1

2

3

4 5

6

7

( 2 ) チャート像次元強度 1マスクパターン番号：1ズームステート：

1物体距離番号：1画角番号：

r 0.000000

θ 0.000000

1波長番号：0.365500μ m

1デフォーカス番号：SUM偏光成分：

256× 256サンプリング数：(1 )( )[μ m]描画サイズ個目直径：

y 61.389860

z 61.389860

表示の正規化指示：ＥＱ

0

0.55

xyz主光線像面座標： 0.000000 0.000000 0.000000

[μ m]ピッチメリサジ： 0.239828 0.239828

1

2

3

4 5

6

7



r 0.000000

θ 0.000000

1波長番号：0.365500μ m



y 61.396080

z 61.396080


0

0.55

xyz主光線像面座標： 0.000000 0.000000 0.000000

[μ m]ピッチメリサジ： 0.239861 0.239861

1

2

3

4 5

6

7



r 0.000000

θ 0.000000

1波長番号：0.365500μ m



y 61.404375

z 61.404375


0

0.5540 μm

4 μm

Deteriorating29 μm

Focus　 0 μm 14 μm 　　 25 μm

Suda – Canon

IWLPC 2015




Suda – Canon

IWLPC 2015

FOWLP technology may be an attractive alternative to 3D & 2.5D technology due to cost reductions

FPA-5510iV functions work well to support high-yield 3D/2.5D integration and FOWLP technology

Canon will contribute even more toward diversifying high-density integration technology

Suda – Canon

IWLPC 2015

Suda – Canon

IWLPC 2015

Vertical thick resist patterning◦ Large DOF lens: NA0.18

Enables thick resist patterning with good profile

3D alignment capability◦ Through Silicon Alignment Scope (TSA-Scope)

Enables backside mark detection Wafer edge processing

◦ Wafer Edge Shield (WES)◦ Wafer Edge Exposure (WEE)

Enables ~20% higher chip yield

Suda – Canon

IWLPC 2015

Item Specification

Projection Lens

Magnification

2:1

NA 0.18

Field Size 52 x 34 mm

Resolution ≤ 1.50 μm

IlluminationWavelength 365 nm

Intensity ≥ 13,000 W/m2

Overlay Accuracy ≤ 0.15 μm

Suda – Canon

IWLPC 2015

0.0

5.0

10.0

15.0

20.0

25.0

30.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

DO

F (μ

m)

Line Width (μm)

FPA-5510iV NA0.18

FPA-5510iZ NA0.57

NA0.18 provides sufficient DOF & resolution for 3D/2.5D applications

DOF ConditionCD Error: ±5%Dose Error: 7%

Suda – Canon

IWLPC 2015

Resist must be removed from the wafer edge for electrolytic plating

Wafer

Resist

Resist Hole

Plating Solution

Seal Rubber

Plating Contact

Non-patterned Area

Resist Removed Area

Positive Resist

Expose

Shield

Negative Resist

Shield

Expose

Suda – Canon

IWLPC 2015

Flexible ring-shaped shield around the wafer edge

No contamination

Projection Lens

Illuminator Edge

Blade

Wafer Edge Shield (WES) unit

Rθ

Exposure Area

Suda – Canon

IWLPC 2015

No throughput loss◦ High intensity◦ Exposure at pre-alignment station during

exposure of preceding wafer Variable exposure width & position

◦ Ring shape exposure available; Outside and inside edge can be set independently

Variable width Variable position

Exposure Area

WEE

Suda – Canon

IWLPC 2015

Nearly 20% yield improvement

Non Ring-Shaped Ring-Shaped

1092 chips 1292 chips

Ring-shapedNon-patternedArea

Chip Size: 7 mm×7 mm; Shot size: 49 mm×28 mm Ring-shaped area: 3 mm from wafer edge

Hiromi Suda Canon Inc. [email protected] October 14 th, 2015.

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Transcript of Hiromi Suda Canon Inc. [email protected] October 14 th, 2015.