Higher Performance SSDs with HLNAND
Transcript of Higher Performance SSDs with HLNAND
Flash Memory Summit 2010Santa Clara, CA
Looking Ahead to Higher Performance SSDs with HLNAND
(A New Standard for GB/s-Class SSDs)
Roland SchuetzDirector, Applications & Business Initiatives
MOSAID Technologies Inc.
Soogil JeongVice President, Engineering
INDILINX
Flash Memory Summit 2010Santa Clara, CA
High-Speed Infrastructure in Place
1995 2000 2005 2010USB1.0 (12Mbps)
FireWire400 (400Mbps)FireWire800 (800Mbps)
FireWire3200 (3.2Gbps)
USB2.0 (480Mbps)
SATA-I (1.5Gbps)
SATA-II (3Gbps)
SATA-III (6Gbps)
USB3.0 (4.8Gbps)
PCIe 1.1 (2.5Gbps/Lane)
PCIe 2.0 (5Gbps/Lane)
PCIe 3.0 (8Gbps/Lane)
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Data Rate (Gbps)
Year
HLNAND in a Nutshell
HyperLink interface: Daisy-chain ring, point-to-point connectionsCleaner signalling than parallel busHigher speed & no roll-off with increasing loads
SCALABILITY
Flash Memory Summit 2010Santa Clara, CA
HLNAND SSD Prototype
Flash Memory Summit 2010Santa Clara, CA
HLNAND SSD Flash Anatomy
128GB on a single channel of HLNAND MCPs133MHz, DDR266 HyperLink interface16 MCP, 64 independent banksData addressable 512B –4KB virtual page size
40MB/s
40MB/s
40MB/s
40MB/s
40MB/s
40MB/s
40MB/s
40MB/s
64Gb HLNAND
64GB HLDIMM
Flash Memory Summit 2010Santa Clara, CA
HLNAND SSD System Anatomy
APB Bridge
ROMSRAM ARM7
AHB SyncBridge
SDRAM ControlArbiter
BufferControl
HLNANDControl
SATA PHY Chip
SDRAM 64MB
Host I/F (SATA2)
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
HLNAND64Gb
FPGA
HLDIMM_1 64GB HLDIMM_0 64GB
Flash Memory Summit 2010Santa Clara, CA
HLNAND SSD Per-Channel Performance
@ 75MHz (FPGA limit)• 120MB/s/ch. seq. read• 73MB/s/ch. seq. write
@ 133MHz, translates to:• 213MB/s/ch. seq. read• 130MB/s/ch. seq. write
8 Ch. HL SSD capable of 1.7GB/s read, 1.0GB/s write
GB/s-Class SSDs now possible with HLNAND
Single Channel Performance
Flash Memory Summit 2010Santa Clara, CA
Introducing HLNAND2
Source synchronous clockingJEDEC HSUL_12 interface up to DDR800Independent automatic status bus
Flash Memory Summit 2010Santa Clara, CA
HLNAND2 Features
DDR533 / DDR667 / DDR800JEDEC 1.2V HSUL_12 Interface SignalingSource Synchronous Clock CK & CK#Four bank architectureFully independent 8 die operationBuilt-in EDC (Error Detection Code)DuplexRW™: Simultaneous DDR800 read & write, effectively 1600MB/s data throughput Independent automatic status bus
Flash Memory Summit 2010Santa Clara, CA
256Gb MLC HLNAND2 MCP
100-Balls BGA (18mm x 14mm)
Throughput Advantage of HLNAND
Flash Pg. Size & Read Time
With
in tR
High-Speed NAND Comparisons
88255255# die before roll-off
67MHz (DQS)83MHz133MHz400 MHz
Clock speed
133MT/s166MT/s266MT/s800MT/sTransfer rate
NoYesYesYesSynchronous IO
Toggle-ModeONFi 2.0HLNANDHLNAND2
Flash Memory Summit 2010Santa Clara, CA
Flash Memory Summit 2010Santa Clara, CA
Current High-Speed Enterprise SSD Architecture
PCIe to SATA2Bridge
SATA2FlashCtlr
Flash
Flash
Host
3Gbps
240 Mbps–1.2Gbps
SATA2FlashCtlr
Flash
Flash
SATA2FlashCtlr
Flash
Flash
• Multi-stage fan-out from high-speedserial channel to low speed parallel channel
• Requires several stages of intermediateprotocol conversion
• Several types of hardwareand firmware support
Flash Memory Summit 2010Santa Clara, CA
Simplification with HLNAND
PCIe / HLNANDcontroller
HL
Host
Up to 6.4Gbps
HL
HL
HL
HL
HL
HL
HL
• Fewer stages of protocol translation and fewer different devices• Can implement host interface, controller, and flash interface in
single ASIC• Fewer channels to achieve maximum throughput; therefore lower
ECC, IO, and PCB costs• 8 ch. SSD with DDR800 HLNAND2 achieves 6.4GB/s data rate
Up to 12.8Gbps(PCIe v2.x, x32)
Flash Memory Summit 2010Santa Clara, CA
Summary
Adoption of faster interfaces is progressingHLNAND2 provides 800MB/s/ch. transfer rateHLNAND2 throughput matched closely with high-speed system interconnect like PCIe 2.x & PCIe 3.0System design simplified with HLNANDHigher system throughput with less complexityController cost reduced through duplication reduction (ECC logic, IO)
Higher scalability in performance & capacity
Flash Memory Summit 2010Santa Clara, CA
Resource for HLNAND Flashwww.HLNAND.com