High High High High VoltageVoltageVoltageVoltage SwitchedSwitchedSwitchedSwitched----Mode Mode Mode Mode

Power SupplyPower SupplyPower SupplyPower Supply for Threefor Threefor Threefor Three----Phase Phase Phase Phase

AC AC AC AC AircraftAircraftAircraftAircraft SystemsSystemsSystemsSystems

A Senior Project

Presented to

The Faculty of the Electrical Engineering Department

California Polytechnic State University, San Luis Obispo

In Partial Fulfillment

Of the Requirements for the Degree

Bachelor of Science

By

John Brewer, Jr.

And

Kamaljit Bagha

June, 2010

© 2010 John Brewer, Jr. and Kamaljit Bagha

ii

Table of Contents

Section Page

Title Page i

Table of Contents ii

List of Table and Figures iv

Acknowledgements vi

I. INTRODUCTION 1

II. BACKGROUND 3

2.1 Predator® - Too Versatile For Its Own Good 3

III. REQUIREMENTS 5

IV. DESIGN 7

4.1 Inverter Project Design Overview 7

4.2 The Power Stage 10

4.3 The PWM Control Circuit and Signal Flow 17

4.4 The LC Output Filters 28

V. CONSTRUCTION 32

5.1 PWM Control Circuit Assembly 32

5.2 Inductor Construction 33

5.3 Wire Harnesses, Connectors, and Cable Fabrication 35

5.4 Power Plane Construction 36

5.5 Enclosure Fabrication 36

iii

5.6 System Assembly 37

VI. TESTING 38

VII. CONCLUSION AND RECOMMENDATIONS 45

VIII. BIBLIOGRAPHY 48

Appendices

A. Schematic 50

B. Bill of Materials 66

C. Circuit Board Layout 69

D. Circuit Board IC and Component Locations 70

E. Hardware Configuration and Layout 71

iv

List of Tables and Figures

Table Page

3.1 MIL-STD-704F AC System Requirements [3] 5

3.2 Summary of Inverter Project Requirements 6

B.1 Bill of Materials and Donated Items 66

Figures

2.1 MQ-1 Predator Drone 3

2.2 MQ-9 Reaper Drone, originally named “Predator B” 4

4.1 IGBT Half-Bridge Configuration 7

4.2 Block Diagram of Inverter Project 9

4.3 Bootstrap Supply Topology with Protection 11

4.4 Nomenclature Used for IGBT Switching Transition 15

4.5 PWM Control Signal Flowchart 18

4.6 dsPIC-based Function Generator 19

4.7 Passive Component Nomenclature for UC3637… 21

4.8 Generating a Trigger Pulse 25

4.9 Bode Plot of Second Order LC Filter 28

5.1 Portion of Circuit Board Layout Graphic 32

5.2 Wire Wrapping 33

5.3 Inductor Bobbin 33

5.4 Tightly Wound Inductor 34

v

5.5 Wood Handle to Support Bobbin 34

5.6 Finished Inductor with Connectors and Mylar Tape 34

5.7 Fabricated Wire Harnesses 35

5.8 Top and Bottom Sides of Copper-Clad Board 36

5.9 Inverter System Assembly 37

6.1 Ideal Inverter Pspice Simulation 38

6.2 Output Voltage Waveform of Ideal Inverter Simulation 39

6.3 IGBT Gate Driver and Half-Bridge Pspice Simulation 39

6.4 High-side (green) and low-side (blue) IGBT… 40

6.5 Adjustable Three-Phase Sinusoidal Reference… 42

6.6 Trigger Pulse successfully generated by AD823AN… 42

6.7 Square wave with 97% duty cycle successfully generated… 43

6.8 Three-phase and Neutral-phase Duty Cycle limited… 43

6.9 Three-phase Inverter Output Voltage referenced… 44

6.10 Three-phase Inverter Output Voltage referenced… 44

C.1 Microsoft PowerPoint Circuit Board Layout 69

D.1 IC and Component Circuit Board Location 70

E.1 Hardware Configuration and Layout 71

E.2 Test Bench Setup 72

AcknowledgementAcknowledgementAcknowledgementAcknowledgementssss

We would like to thank –

Mr. John (Jeff) Brewer, Director of Electrical Engineering for the Aircraft

Systems Group at General Atomics Aeronautical Systems, Inc. for providing and

funding a challenging project for us to work on and offering the technical support

needed to complete this project. We appreciate him sharing his knowledge and

insight of the broad range of topics that this project covers and have been inspired

to work hard and never stop learning as electrical engineers.

Dr. Taufik, Professor of Electrical Engineering at California Polytechnic State

University, San Luis Obispo, as our faculty advisor for this project. His dedication

and excellence as a teacher both in the classroom and lab have equipped us with a

solid foundation of knowledge and understanding in the field of power electronics.

His teaching curriculum and techniques significantly contributed to our ability to

“Learn by Doing” here at Cal Poly.

Mr. Jaime Carmo, Cal Poly EE Department Electronics Technician, for his

support and generous donation of time, equipment, and parts throughout the

construction, testing, and fabrication stages of our project.

Mr. Cole Brooks, Cal Poly mechanical engineer and friend, for his assistance

in metal parts fabrication

Our families for supporting our educational endeavors.

Sincerely,

John Brewer, Jr. and Kamaljit Bagha

1

I.I.I.I. INTRODUCTIONINTRODUCTIONINTRODUCTIONINTRODUCTION

With the advent of the first power rectifier by an American engineer and

applied physicist, Robert Hall, in 1952, a new form of power control and conversion

was born – Power Electronics. The successive arrival of thyristors in 1957, bipolar

transistors in the 1960s, power MOSFETs in the late 1970s, and IGBTs in the 1980s

led to the rapid advancement of power electronics in all fields of electrical

engineering [1]. These fields include utility power distribution, industrial electronics,

and especially aircraft electronics because of the small size of power electronic

components. A few applications of power electronics in these fields include power

quality controllers, variable speed drives, and power supplies.

Power electronics is unique in its method of power control and conversion in

that it is based on the switching fully-on and fully-off of semiconductor devices to

regulate power flow. More efficient than linear power regulation which uses

variable resistance to regulate power flow, switching semiconductor devices by

using a technique called “Pulse Width Modulation (PWM)” is the method used in a

modern “switching” or “switched-mode” power supply (SMPS). PWM is a technique

where the duty cycle of the semiconductor switch is manipulated to control power

flow through the switch. As a result, the output voltage delivered to the load can be

2

well regulated to produce a fixed Direct Current (DC) voltage or a desired Alternating

Current (AC) voltage.

There are two types of converter topologies used in SMPS design – isolated

and non-isolated. Transformers are used in the design of isolated converters to

provide flexibility in circuit design by allowing for separate (isolated) input and

output current return paths to “ground.” Non-isolated converters, however, do not

use transformers and the input current ground is used as the ground for the output

load current.

For our application, we have designed a non-isolated SMPS that produces AC

output voltage from DC input voltage – this is known as a DC/AC converter or,

simply, an inverter. It uses the common method of Pulse Width Modulation to

switch Insulated Gate Bipolar Transistors (IGBTs) to control the flow of power from

±DC input voltage “rails” to three-phase, sinusoidal AC output voltage. In the next

section of this report, we will present the background and application of our inverter

design.

3

II.II.II.II. BACKGROUNDBACKGROUNDBACKGROUNDBACKGROUND

Our three-phase, sinusoidal inverter project was sponsored by Jeff Brewer,

the Director of Electrical Engineering at General Atomics Aeronautical Systems, Inc.

(GA-ASI). The purpose of this project was to design and build a proof-of-concept

high-power switched-mode inverter. This project began the development process

for a high-voltage three-phase AC power supply for use on any of the Predator®

Unmanned Aircraft Systems (UAS) that GA-ASI manufactures.

2.1 Predator® – Too Versatile For Its Own Good

Predator® aircraft like the ones shown in Figure 2.1 and Figure 2.2 are used

by multiple branches of the United States’ military and homeland security including

the Air Force, Army, U.S. Customs and Border Protection, Central Intelligence

Agency, and NASA. They are popular for their wide range of applications including

remote sensing, reconnaissance, weapons delivery, search and rescue, and

surveillance. Predator® systems are versatile

aircraft platforms upon which an increasingly

large array of electronic device payloads like

sensors, weapons, and communications

equipment can be mounted. Fig. 2.1 – MQ-1 Predator Drone

Source: Public Domain

4

Currently, these devices are powered by 28 VDC power on the aircraft – one of three

standard aircraft power systems prescribed by MIL-STD-704F [3]. Because these

aircraft are required to support an increasing number of electronic payloads, the

weight of the cables in the aircraft needed to deliver 28 VDC power to these

payloads exceeds practicality. So, to counteract this problem, plans to provide high-

voltage power systems in accordance with MIL-STD-704F on Predator® aircraft are in

effect. It is estimated that the cable weight required to distribute power on the

aircraft will be reduced by a factor of ten when high-voltage power is provided [2].

These plans include the provision of a 270VDC system and a three-phase AC system

as outlined in the next section of this report.

Fig. 2.2 – MQ-9 Reaper Drone, originally named “Predator B”

Source: Public Domain

5

III.III.III.III. REQUIRREQUIRREQUIRREQUIREEEEMENTS MENTS MENTS MENTS

The purpose of our project was to design and build a non-isolated DC/AC

SMPS capable of supplying 10 kW for a standard three-phase AC aircraft power

system. According to MIL-STD-704F,

“AC systems shall provide electrical power using single-phase or three-phase

wire-connected grounded neutral systems. The voltage waveform shall be a

sine wave with a nominal voltage of 115/200 volts [115 VRMS] and a nominal

frequency of 400 Hz” [3].

Because MIL-STD-704F also prescribes AC system requirements like the

sample shown in Table 3.1, the production level version of our inverter will require

the use of closed-loop feedback to provide adequate line and load regulation.

However, designing a closed-loop system was beyond the scope of this project, so

an open-loop system was required.

Table 3.1 – MIL-STD-704F AC System Requirements [3]

Characteristics Limits

Steady State Voltage: 108.0 VRMS to 118.0 VRMS

Voltage Unbalance: 3.0 VRMS (maximum)

Voltage Modulation: 2.5 VRMS (maximum)

DC Component: +0.1 to -0.1 Volts

Voltage Phase Difference: 116° to 124°

Steady State Frequency: 393 Hz to 407 Hz

Frequency Modulation: 4 Hz

Peak Voltage: ±271.8 Volts

6

Lastly, the production level version of our inverter will be powered by the

engine alternator on the aircraft. The three-phase, variable voltage, variable

frequency engine alternator power will be rectified and regulated to produce

±190 VDC rails from which the inverter will draw its power [2]. Since this

rectification and regulation of engine alternator power is beyond the scope of this

project, it was required that our proof-of-concept inverter work from ±125 VDC rails

for three-phase operation given 10Ω resistive loads. This requirement was limited

by the available test equipment in Cal Poly’s EE Department Power Electronics Lab.

The nominal requirements of our inverter project are summarized below in

Table 3.2. In the following section of this report, we will present a system overview

of our inverter project followed by a more detailed discussion of the circuit design

process.

Table 3.2 – Summary of Inverter Project Requirements

Nominal System Requirements

Converter Topology: Non-Isolated SMPS

Input Voltage: ±125 VDC

Output Voltage: 85 VRMS AC

Output Voltage Waveform: Three-Phase, Sinusoidal

Steady State Frequency: 400 Hz

Maximum Output Power: 10 kW

7

IV.IV.IV.IV. DESIGNDESIGNDESIGNDESIGN

This section of our report represents a majority of the work that went into

this project – circuit design. In this section, we will present an overview of our

inverter project followed by a series of discussions covering the details of the circuit

design, signal flow, and discrete components used.

4.1 Inverter Project Design Overview

The design of our three-phase sinusoidal inverter is based on the PWM

switching of N-Channel IGBTs connected in a half-bridge configuration as shown in

Figure 4.1. As the high-side and low-side IGBTs are complementarily switched fully-

on and fully-off, they connect the load to the

+DC and -DC Rails, respectively. Since the

output is connected to one of two voltage

polarities during this method of switching, it is

known as Bipolar Switching. Because the

output voltage is effectively an amplified

version of the PWM Control Input, this stage of

the inverter system can be considered the

Power Amplification stage and is shown in the System Block Diagram in Figure 4.2.

Fig. 4.1 – IGBT Half-Bridge Configuration

Source: John Brewer, Jr.

8

The IGBT Gate Drivers and Floating Bootstrap Supply topology required to drive

N-Channel IGBTs in this configuration are also indicated in Figure 4.2 and will be

discussed in Section 4.2.1.

The PWM Control Input is generated by the PWM Control Circuit block. The

PWM Control Circuitry is responsible for generating the sinusoidal reference

waveforms, establishing the switching frequency, creating PWM signals, limiting the

duty cycle of the PWM signals, and interfacing logic-levels. A thorough discussion of

the PWM Control Circuitry will be presented in Section 4.2.2 of this report.

The final piece of our inverter design is the inductor/capacitor (LC) output

filters on each phase. The LC output filters were designed to smooth the PWM

output of the Power stage and filter out high-frequency harmonics introduced by

IGBT switching. These will be discussed in Section 4.2.3.

An important characteristic to note about our inverter design is the fourth

IGBT Half-Bridge “leg” which is used to create a virtual ground (neutral) through

which phase currents from an unbalanced three-phase load can return to the DC

input supply. The PWM Control Input to this neutral leg will have a nominal 50%

duty cycle, creating a voltage that is one-half the DC supply voltage upon which the

three-phase sinusoidal output voltages will be centered. The creation of this neutral

return is necessary in the case that a bipolar DC supply with ground connection is

unavailable and a unipolar DC supply must be used.

9

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10

4.2 The Power Stage

As mentioned in Section 4.1, the Power Stage consists of two IGBTs

connected in a Half-Bridge configuration. Four identical half-bridge legs form the

foundation of our three-phase inverter and are responsible for controlling power

flow from the DC Input Supply to each phase output voltage – Phase A, Phase B,

Phase C, and Neutral.

Jeff Brewer donated the IGBTs that were to be used for this project –

IRGP50B60PD1, WARP2 Series IGBT with Ultrafast Soft Recovery Diode from

International Rectifier (IR). These IGBTs are high-speed, high-power, SMPS,

N-Channel IGBTs capable of withstanding a collector-to-emitter voltage of 600V.

Driven with a gate-to-emitter voltage of 15V, these IGBTs can source 33A with

maximum turn-on and turn-off delay times of 40ns and 150ns, respectively [4]. With

an operational output voltage of 115VRMS, the resulting power output capability of

all three inverter phases combined can then be calculated to be:

= 3 ∗ ∗ (Eq. 4-1)

∴ = 3 ∗ 33 ∗ 115 = 11.385

In conclusion, using these IGBTs will fulfill our requirement to design a three-

phase inverter capable of supplying 10kW with an output voltage of 115VRMS. In the

next section, we will discuss the floating bootstrap supply topology required for

11

switching N-Channel devices, the IGBT Gate Driver design process, and design

measures taken to protect the IGBTs.

4.2.1 Bootstrapping, IGBT Gate Drivers, and Transient Voltage Protection

N-Channel semiconductor devices are commonly used in half-bridge

configurations as our IGBTs are used in the power stage of our inverter. However,

these N-channel devices require a charge applied to the gate that is positive with

respect to the emitter such that (VGE > VTH). While this does not present a problem

for turning on low-side devices with a power supply referenced to the –DC rail, the

same supply would be unable to turn on the corresponding high-side device as the

high-side emitter follows the output voltage of the half-bridge – a much larger

voltage than the supply voltage. Therefore, a bootstrap supply topology is required.

As illustrated by the schematic of a typical bootstrap supply topology in

Figure 4.3, a bootstrap capacitor is connected from the power supply, VCC, to the

high-side emitter. Due to

the charge storage

characteristics of a

capacitor, the bootstrap

capacitor voltage will rise

+VCC above the high-side

emitter, providing the Fig. 4.3 – Bootstrap Supply Topology with Protection

Source: John Brewer, Jr.

12

necessary gate drive voltage to turn on the high-side device. When an internal

switch in the Gate Driver Integrated Circuit (IC) connects node VB to the high-side

gate, the high-side device will turn on. It will then turn off when the gate is

disconnected from VB and connected to VS by internal switches in the Gate Driver IC.

However, the high-side device will also turn off if the charge on the bootstrap

capacitor is depleted due to parasitic gate current. Because of this, the duty cycle of

the high-side device switching must be limited and the bootstrap capacitor sized

accordingly to prevent premature/uncontrolled turn-off of the high-side device.

For our project, we decided to use the Si8234BB ISOdriver manufactured by

Silicon Labs as our High-Voltage Integrated Circuit (HVIC) Gate Driver. This recently

released HVIC Gate Driver contains two completely isolated high-side/low-side

drivers in one package that are each capable of sourcing 4.0A peak output current.

The isolated drivers are controlled by a single PWM Control Input signal and an

external resistor used to program the deadtime created between the switching of

the high-side and low-side devices. The input logic side of the device is 5V TTL

compatible, while the output side can support the 15V supply used to switch our

IGBTs. Also note that we have incorporated the Disable pin of the Si8234BB device

into our circuit design to provide the functionality of being able to turn combinations

of our phase output voltages on or off [5].

We consulted IR’s “Design Tips for Using Monolithic High Voltage Gate

Drivers” during the design process for our HVIC gate drivers and floating bootstrap

13

supply [6]. To size the bootstrap capacitor, we started by calculating the maximum

voltage that the bootstrap capacitor voltage was allowed to drop (∆VBS) when the

high-side IGBT was supposed to be on. To do this, we decided from Fig. 8 of our

IGBT datasheet that the minimum gate-to-emitter voltage to allow should be 11V in

order to guarantee a collector-to-emitter voltage of about 2V given a collector-to-

emitter current around 33A. Also, we used a value of 1V for the typical forward

voltage drop of the MUR460 power rectifier used to protect VCC as shown in

Figure 4.3 [7]. As a result, we obtain

∆ = − − , − , (Eq. 4-2)

∴ ∆ = 15 − 1 − 11 − 2 ≅ 1

We then confirm that VGE,min > VBSUV- where VBSUV- is the high-side supply

undervoltage negative going threshold of 8.10V as indicated in Table 1 of the

“Si823x” datasheet from Silicon Labs [5].

The next step in sizing the bootstrap capacitor was to consider the following

factors contributing to a decrease in VBS:

- IGBT turn-on required Gate charge (QG) = 308nC (max) [4]

- IGBT Gate-Emitter leakage current (IGES) = 100nA [4]

- Output supply quiescent current (IDDAQ) = 3.0mA (max) [5]

- Bootstrap diode instantaneous reverse current (ILK_D) = 50μA [7]

- Bootstrap capacitor leakage current (ILK_C) = 0μA (use ceramic capacitors)

- High-side on time (TH,on) = 24.5μs (98% duty cycle at 40kHz)

14

Then we have

#$% = # + ' + (() + %*_, + %*_- ∗ ./, (Eq. 4-3)

∴ #$% = 30812 + 31001 + 3.04 + 505 + 056 ∗ 24.558 ≅ 38312

And the minimum size of the bootstrap capacitor can be calculated by

2, = )9:9;<

∆=>? (Eq. 4-4)

∴ 2, = @A@

B=≅ 3831C

So, to account for estimation error and temperature drift, we decided to use a

bootstrap capacitance of 660nF, almost twice as big as the calculated CBOOT,min. As

mentioned earlier, MUR460 power rectifiers are an ideal choice for use as the

bootstrap diode in our bootstrap supply design. These devices were also donated to

our project and can withstand a reverse voltage of 600V and have a reverse recovery

time of less than 100ns [7].

The final design issues to be mentioned regarding the design of the IGBT gate

drivers are the addition of decoupling capacitors, sizing of gate resistances, and

measures taken for protecting the IGBTs and HVIC Gate Drivers. Sufficient

decoupling capacitance was added to our gate driver design by placing ceramic and

electrolytic capacitors in parallel with the gate drive supply voltage very close to

both the low-side Gate Driver output pins and the bootstrap diode. The ceramic

capacitor provides a fast charge tank and limits D

DEF by reducing the equivalent

series resistance while the electrolytic provides a longer lasting charge tank.

15

The process for sizing the gate resistances consisted of both calculations to

derive ballpark figures and hardware experimentation. From “Design Tips for Using

Monolithic High Voltage Gate Drivers,” we can estimate the necessary size of the

turn-on gate resistor by fixing the switching-time. As shown in Figure 4.4, the

switching time is defined

as the time spent to

reach the end of the

plateau voltage resulting

from charging the IGBT

gate capacitances with

QGC and QGE. Estimating

an appropriate switching time to be about 115ns and knowing QGC and QGE to be

105nC and 45nC, respectively, we can calculate

$=$ = )GHI)GJ

KLM (Eq. 4-5)

∴ $=$ = BNOIPO

BBOQ≅ 1.3

And

R$% =HH T =UVW;XJY;GJ

(Eq. 4-6)

where Vge* is approximated to be 6.2V from Fig. 17 of our IGBT datasheet [4], and

R$% RZ3Q [\]^6 & R, (Eq. 4-7)

Fig. 4.4 – Nomenclature Used for IGBT Switching Transition

Source: International Rectifier [6]

16

Where RON(source) is 2.7Ω according to the Si8234BB datasheet, and RG,on is the value

for the high-side IGBT gate resistor [5]. As a result, we have

R, = BO=T_.`=

B.@$− 2.7Ω ≅ 4Ω

And following IR’s Design Tip, we size the low-side IGBT gate resistor to be larger

than the gate resistor of the high-side device – about 5Ω. This will result in softer

switching of the low-side device and a reduction in magnitude of the voltage

transients caused by parasitic inductances during switching.

Lastly, the design of the Power stage includes devices added to protect IGBTs

and HVIC Gate Drivers from transient voltage spikes caused by parasitic inductances

in the circuit. First, Zener clamp diodes with a reverse voltage breakdown voltage of

16V are added across the gate-to-emitter junctions of both high-side and low-side

devices. Shown in Figure 4.3, these Zener clamps protect the HVIC Gate Driver

output, sink current generated by transient voltage spikes occurring on the collector,

and keep the IGBT gate-to-emitter voltage from exceeding the maximum limit of

20V [4]. Another clamp device used is the series combination of a 16V Zener diode

and MUR460 Power Rectifier positioned between the VS pin of the HVIC Gate Driver

and the –DC rail also shown in Figure 4.3. The purpose of this clamp device is to

guarantee that VS does not exceed maximum undervoltage limits when negative

voltage transient spikes are induced by parasitic inductances. The production level

version of our inverter will include the placement of reverse-biased transient voltage

17

suppression diodes with a reverse breakdown voltage <600V across the collector-to-

emitter IGBT terminals. These will protect the IGBTs from damage caused by voltage

transients on the DC supply rails or half-bridge output node. Due to the DC input

supply test limits, we omitted these diodes from our proof-of-concept design.

The circuit schematics for the four Power Stages of our inverter design can be

found on Sheets 11, 12, 13, and 14 of the system schematic in the Appendices. In

the next section of this report, we will discuss the PWM Control Circuit and signal

flow.

4.3 The PWM Control Circuit and Signal Flow

The PWM Control Circuit is the “brain” of our inverter project and is

responsible for generating our three-phase sinusoidal reference signals, producing

PWM Control signals for all three-phases and neutral, limiting the duty cycle of the

PWM Control signals, and interfacing logic levels. It was designed using discrete

analog components with the exception of a Microchip dsPIC 16-bit Digital Signal

Controller-based function generator. Considerations for choosing the discrete

analog devices we used included availability, ease of prototype implementation,

proven reliability, low replacement cost, and extreme temperature tolerance for

military temperature requirements.

18

In this section of the report, we will present a discussion of the circuit

components used to perform these tasks and cover the details of the circuit design

required to interface these components and generate PWM Control Input signals for

the HVIC Gate Driver of each IGBT half-bridge. Figure 4.5 illustrates the general flow

of a single phase PWM Control signal.

Fig. 4.5 – PWM Control Signal Flowchart

Source: John Brewer, Jr.

19

4.3.1 Generating Three-Phase Sinusoidal Reference Signals

The first step in the design of the PWM Control Circuit was to generate three

sinusoidal reference voltages, each having 120° of phase displacement from the

others. Fortunately, this step was already complete before we began our project.

Manufactured and donated by GA-ASI, the Microchip dsPIC Digital Signal Controller-

Based Function Generator shown in Figure 4.6 supplies three-phase sinusoidal

waveforms with accurate sine shape and phase displacement. The frequency and

amplitude of the output sinusoids

are adjustable, but for our

application they are set to have a

frequency of 400 Hz and peak-to-

peak amplitude of 2V.

In order to make the

amplitude of our inverter output

voltage waveforms adjustable,

remove the DC offset from the reference sinusoids, and buffer the reference

sinusoids, we AC coupled each of the sinusoidal phase voltages from the function

generator to adjustable gain, non-inverting amplifiers designed using TL082 JFET

Input Op-Amps. Simple RC highpass filters with a cutoff frequency of 1 Hz were used

for the AC coupling. The TL082 op-amps were chosen because of their suitable slew

rate of 13V/μs, low Total Harmonic Distortion of 0.003%, ability to operate from

Fig. 4.6 – dsPIC-based Function Generator

Source: John Brewer, Jr.

20

±15V supplies, and compact 8-pin packages containing two op-amps each. The

circuit schematic for this step in the PWM Control Circuit can be located on Sheet 3

of the system schematic in the Appendices.

4.3.2 Generating PWM Signals from Reference Sinusoids

The next step in the design of the PWM Control Circuit was to generate the

PWM Control signals for each phase including neutral by comparing the reference

sinusoids to a triangle wave having a frequency equal to the desired IGBT switching

frequency. Using a PWM Controller IC is the most efficient way to do this, so we

chose the Unitrode UC3637 Switched-Mode PWM Controller for DC Motor Drives.

The UC3637 was chosen because of its high reliability, robustness, and

widespread use in industry. It is easy to program and provides a built in error

amplifier, under-voltage lockout, and can operate from dual power supplies [8].

Concurrently, multiple UC3637 ICs can be readily synchronized according to

Unitrode’s Design Note about “Design Considerations for Synchronizing Multiple

UC3637 PWMs” [9]. This was an important quality of the UC3637 since four PWM

Controller ICs were required in the PWM Control Circuit and the ability to

synchronize them would simplify circuit construction.

We arbitrarily decided to establish the Neutral phase PWM Controller as the

Master PWM device. This IC was “programmed” with the passive components

shown in Figure 4.7 according to the following design requirements:

21

• Triangle Wave frequency of 40kHz (same as the IGBT switching frequency).

• Triangle wave amplitude of 20 VP-P (large to increase noise immunity).

• Modulation scheme with no deadtime (since the Si8234BB IGBT Gate Driver

supplies the necessary high-side/low-side switching deadtime).

• Under-voltage lockout level of 10.75V (to prevent switching IGBTs when

there is not enough supply voltage to fully turn them on).

Fig. 4.7 – Passive Component Nomenclature for UC3637

Master Device Programming

Source: John Brewer, Jr.

Consulting the Unitrode UC3637 Datasheet and following the Unitrode

Application Note U-102, we calculated the following [8] [10]:

R 3I=9c6T3T=?6W?

(4-8)

∴ R 3IBN =6T3T BO =6

N.O$= 50Ω ≅ 47.5Ω

22

2 W?`de3I=9c6T3T=9c6f (4-9)

∴ 2 N.O$

`∗PNg/h∗e3IBN =6T3TBN =6f= 313iC ≅ 300 iC

For clarity, we note that the Unitrode Application Note U-102 suggests that the

constant current used to charge the external capacitor, CT, be within the range of 0.3

to 0.5 mA. Because the amplitude of the triangle wave has been designed fairly

large, we programmed ISET to a value on the higher end of this range, 0.5 mA, as

used in Eq. 4-9. Using this higher charging current performs a secondary feature of

allowing the use of a larger capacitor, CT, that will be able to store enough charge to

drive the input of a TL082 op-amp configured as a voltage-follower. This will

produce a buffered triangle wave used to drive the UC3637 slave devices and the

AD823AN op-amp used for generating a trigger pulse for the HCF4538B Monostable

Multivibrator

Since +VTH and -VTH should be symmetrical at ±10V in our application, we set

R1 = R5 and calculate REQ (where REQ = R2 + R3 + R4) after choosing reasonable values

for R1 and R5. Using an iterative process to determine values for R1 and R5, we

• Calculated REQ

• Calculated the approximate bias current, IBIAS, through the resistor

divider created by R1, REQ, and R5 between +VS and -VS.

• Adjusted values accordingly to limit the bias current to an order of

hundreds of microamps. This prevented unnecessary power loss while

23

maintaining the ability to adequately charge the PWM controller

comparator inputs.

As a result,

RB RO 20.4Ω

R) = ` ∗ j ∗ =9c

=? T =9c (4-10)

∴ R) = ` ∗ `N,PNNk ∗ BN=

BO= T BN== 81,600 Ω

We also needed to ensure that the +VSLV node voltage indicated in Figure 4.7

was always less than the magnitude of the triangle wave despite any drift in

resistance, the UC3637 Master PWM device characteristics, or the AD823AN op-amp

characteristics. This will guarantee the generation of a trigger signal for the

HCF4538B Monostable Multivibrator which is used to create a square wave with

frequency equal to the triangle wave and duty cycle of 98%. In order to do this, we

needed to determine the minimum voltage difference, ∆Vmin, required between +VTH

and +VSLV. Following the procedure outlined in Unitrode Design Note DN-53A, we

determined ∆Vmin to be about 1.5V, requiring a ballpark resistance for R2 and R4 to

be 6.3kΩ [9]. However, based upon the hardware available during the construction

phase of our project,

R` = RP = 5.62Ω and R@ = 68.1Ω

Yielding

W$ = I=?T3T=?6

mInIjIoIp (4-11)

24

∴ W$ IBO= T 3TBO=6

`N,PNNk I O,_`Nk I _A,BNNk I O,_`Nk I `N,PNNk≅ 2505

Lastly, we used the equation provided in the UC3637 IC datasheet to

establish an undervoltage lockout level of 10.75V. Using a 100kΩ resistor for R6, we

calculated

$ = `.O∗3qIr6

q (4-12)

∴ Rs = =?9;Y9 ∗ q

`.O− R_ = BN.sO=∗BNNgk

`.O− 100Ω = 330Ω

At this point, the simplicity of synchronizing the other three UC3637 slave

devices becomes evident. Besides adding 0.1μF decoupling capacitors to all device

pins that are tied to a fixed voltage, we simply connect the +VSLV node to the +VTH

slave device pins, the –VSLV node to the –VTH slave device pins, the SD pin of the

master device to the SD pins of the slave devices, and the buffered triangle wave

output from the TL082 voltage-follower to pins 2, 8, and 10 of the slave PWM

devices.

The -15V low/+15V high PWM Control Input signals are each interfaced with

their respective 74AC00 CMOS NAND Gates by a current limiting resistor/voltage

divider/Schottky diode network that reduces the signal to 0.4V low/+5V high.

In the next sections of this report, we will discuss the portions of the PWM

Control Circuit that limits the duty cycle of the PWM Control Inputs to 98%.

25

4.3.3 Generating a Trigger Pulse

As mentioned in the previous section, our PWM Control Circuit design

includes the use of an AD823AN rail-to-rail FET Input op-amp as a comparator.

According to the AD823AN datasheet, this op-amp has a high slew rate of 22V/μs

and can operate from ±15V supplies [11]. As a result, this op-amp provides the

speed needed for a short switching transition time and required no voltage level

shifting to interface the ±20V buffered triangle wave. Although the AD823AN is a

dual op-amp package, only one of the op-amps is needed by our control circuit.

With the buffered triangle wave tied to the positive input and the +VSLV

voltage tied to the negative input of the comparator, a +15V pulse with duration of

about 1μs is generated when the triangle wave is at its peak and exceeds the +VSLV

threshold as illustrated in Figure 4.8.

This -15V low/+15V high trigger pulse

is interfaced with the HCF4538B

Monostable Multivibrator through a

current limiting resistor and Schottky

diode network that reduce the trigger

pulse to a 0.4V low / +15V high pulse.

4.3.4 Monostable Multivibrator

After being triggered by the trigger pulse delivered by the AD823AN

comparator, the HCF4538B Monostable Multivibrator configured as a non-

Fig. 4.8 – Generating a Trigger Pulse

Source: John Brewer, Jr.

26

retriggerable one-shot generates a 24.5μs pulse. Since the trigger pulse is delivered

every 25μs, the equivalent waveform produced is a 40kHz square wave with a duty

cycle of 98%. This 0V low/15V high signal is interfaced with the 74AC00 CMOS

NAND Gates through a simple resistor divider reducing it to a 0V low/+5V high

signal. The timing equations and wiring configuration for a non-retriggerable one-

shot design were given by the HCF4538B datasheet [12]. As illustrated in our

schematic (See Appendix) we paired a 5,600pF timing capacitor, C38, with a 10kΩ

potentiometer, R22, so we could adjust the output pulse of width, T, according to the

equation

. R`` 2@A (4-13)

∴ R`` jt `P.OuQ

O,_NNv= 4.375Ω

4.3.5 High-speed CMOS NAND Gates

The 74AC00 CMOS NAND Gates used in our PWM Control Circuit provide the

logical AND function needed to limit the duty cycle of the PWM Control Input signals

to 98% [13]. By “ANDing” the PWM Control input signal for each phase of our

inverter with the square wave output by the One-Shot, the duty cycle of the PWM

Control Input signals are effectively limited to 98%. This provides the high-side IGBT

off-time necessary for recharging the bootstrap capacitor as discussed in Section

4.2.1.

27

4.3.6 Supplying Power to the PWM Control Circuit and Bootstrap Supply

After having figured out how to drive our inverter IGBTs and design the PWM

Control Circuit, we needed to figure out how to supply power to the low-voltage side

of our project. Since the function generator donated to our project by GA-ASI came

with its own power supply, we only needed to supply +15 VDC, -15 VDC, and +5 VDC

to our circuit. For these voltages, we bought two 15V and one 5V isolated AC/DC

wall adapters – the first two sold as “Notebook Adapters” and the latter as an

“Internet Router Adapter.” Since these adapters are isolated, we were able to

reference our PWM Control Circuit DC Bias Supply voltages to the most negative

voltage used for the DC Input Supply to our inverter – a requirement for properly

driving our Half-Bridge IGBT topology with a Bootstrap Supply.

4.3.7 Using Decoupling Capacitors

As we complete our discussion of the PWM Control Circuit, it is important to

note the use of decoupling capacitors throughout our circuit design. The use of

0.1μF ceramic capacitors tied between logic ground and any IC pin connected to a

bias voltage provides sufficient AC decoupling and noise immunity. It is also

important to note the use of sufficiently larg electrolytic bias supply capacitors

located at the circuit board D-sub connector where the power is delivered to the

board.

28

4.4 The LC Output Filters

The design process for our inverter project included the design of three

Second-Order LC filters to be used for smoothing the output voltage waveforms for

each phase of our inverter. The design of these LC output filters was based on the

400Hz output voltage frequency and the 40kHz PWM switching frequency. As

illustrated by the Bode plot in

Figure 4.9, we designed the LC

output filter to have a corner

frequency of 2kHz so it would

effectively pass the 400Hz

voltage waveform while

sufficiently attenuating the 40kHz

PWM switching frequencies. We

also designed the LC filter to have

a low output impedance of 2Ω.

Therefore, using

L = 159μH and C = 40μF,

w B`x√% (4-14)

∴ w B`xzBOu/PNu 1,995~ " 2~

Fig. 4.9 – Bode Plot of Second Order LC Filter

Source: John Brewer, Jr.

29

And,

% (4-15)

∴ BOu/PNu 1.99Ω ≅ 2Ω

4.4.1 Inductor Design

During the design process of the inductors for our inverter, we received

some much needed help from Jeff Brewer [2]. The most significant factor in the

inductor design process was the desired inductance and maximum amount of

current that would flow through an inductor during inverter operation.

Although the nominal output current of each inverter phase is 33A, we

designed the inductors for our inverter to be able to carry up to 50A. Based on the

equation for energy stored in an inductor, we needed to design inductors that could

each store

% = B

`` (4-16)

∴ QK \^ = B

`∗ 1595 ∗ 3506` = 0.19875 8

Then using

= `∗LV∗BNo

∗*∗* (4-17)

∴ = `∗N.BAsO∗BNo

ONNN∗P_A∗N.O= 34.2 4P

where

AP = area product in cm4.

30

Kj = the current density coefficient for a given core and a given

temperature rise.

Ku = the cross sectional area of copper to the total window area or packing

factor.

Bmax = the maximum flux density in Gauss.

from selecting an AMCC-50, size 10, PowerLite C-Core [2] [14] [15]. These PowerLite

cut C-cores are made out of Metglas iron alloy material and will not only make our

inductors easy to fabricate but also allow for fine tuning of inductance by adjusting

the air gap and using an Impedance Bridge

To determine the minimum number of turns, Nmin, and the length of air gap,

Lgap, needed in each leg of the cut C-core inductor, we used

%WH,∗BNt

∗$U (4-18)

∴ = BOu/∗ON$∗BNt

O,NNN∗@.`]n = 49 E18

where

L = Inductance of the inductor in microHenries.

IDC,max = Maximum current through the inductor in Amps.

Agap = Total cross sectional area of the air gap including fringing.

And

v =.`∗x∗$U∗BNn∗Zn

% (4-19)

∴ v = .`∗x∗@.`]n∗BNn∗Pn

BOu/= 0.304 1ℎ8.

31

Lastly, we determined that although making an inductor by wrapping

insulated Copper Foil around a Ferrite Core would result in lower core losses for the

beneficial design tradeoff of higher copper loss, it would be hard to fabricate for a

prototype. So, we chose 10AWG magnet wire with a heavy insulation build for

withstanding temperatures up to 200°C to wrap our AMCC-50 cores with [16]. We

were able to successfully wrap our inductor bobbins with 49 turns and connect two

bobbins in parallel, one on each inductor leg, for a generous inductor current

capacity of 50A.

In the next section of this report, we will discuss the construction phase of

our inverter project.

32

V.V.V.V. CONSTRUCTIONCONSTRUCTIONCONSTRUCTIONCONSTRUCTION

The construction and assembly phase of our proof-of-concept inverter

project consisted of six main parts – PWM Control Circuit assembly, Inductor

construction, Wire Harnesses, Connectors, and Cable fabrication, Power Plane

construction, Enclosure fabrication, and System assembly.

5.1 PWM Control Circuit Assembly

Before starting construction of the PWM Control Circuit, we used Windows

Paint to create scale drawings of our perforated circuit board (PerfBoard),

components, and ICs. We then copied these scale drawings into Microsoft

PowerPoint where we were then

able to freely move, place, label, and

“wire” components according to our

circuit design. Figure 5.1 shows a

part of our Circuit Board Layout.

To make connections on our

circuit board, we used a combination

of soldering and wire wrapping;

however, soldering was only used to solder short connections like decoupling

capacitors to IC pins while wire wrapping constitutes a majority of our connections.

Fig. 5.1 – Portion of Circuit Board Layout Graphic

Source: John Brewer, Jr.

33

A common prototype technique, wire wrapping uses a wire wrap tool to tightly wrap

30AWG Kynar wire around special wire wrap “posts.”

Using two PerfBoards, one on top of the other, provides a

much stronger circuit board to work with and helps keep

wire wrap posts straight. Figure 5.2 illustrates this

technique. For our proof-of-concept prototype, the design

and fabrication of a Printed Circuit Board (PCB) would not

have been cost effective and would have made circuit

modifications difficult.

5.2 Inductor Construction

To construct the inductors, we needed to wrap 10AWG enameled wire 49

times around the inductor bobbins shown in Figure 5.3. As shown in Figure 5.4, we

needed to guarantee that the wire was wrapped very tightly around each bobbin so

that two bobbins would fit on one core. In

order to prevent cracking a bobbin during

the wrapping process, Jeff Brewer

fabricated the wood handle shown in

Figure 5.5 to fit snugly inside each bobbin

as it was wound.

Fig. 5.2 – Wire Wrapping

Source: John Brewer, Jr.

Fig. 5.3 – Inductor Bobbin

Source: John Brewer, Jr.

34

When it was time to put two wire-wrapped

bobbins on a core, we used the right-hand-rule to

determine the orientation of the bobbins on the

core to guarantee that the flux induced by the

coiled wire on each bobbin was flowing through

the core in the same direction. Using an

Impedance Bridge, we adjusted the air gap of

each inductor to obtain our desired inductance at 2kHz – 159μH. We then used

small squares of PerfBoard as spacers inside the bobbins between the core halves to

maintain the necessary air

gap of each inductor.

Using a sharp edge,

we scraped about an inch of enamel coating from each end of the wires to be

connected. Lastly, we crimped and soldered them to a connector and wrapped up

the inductor using high-

temperature Mylar tape

as shown in Figure 5.6.

Fig. 5.5 – Wood Handle to Support Bobbin

Source: John Brewer, Jr.

Fig. 5.4 – Tightly Wound Inductor

Source: John Brewer, Jr.

Fig. 5.6 – Finished Inductor with Connectors and Mylar Tape

Source: John Brewer, Jr.

35

5.3 Wire Harnesses, Connectors, and Cable Fabrication

In order to simplify the assembly, transportation, testing, and modification

process, we designed and fabricated the following wire harnesses, connectors, and

cables:

• For signals and voltages delivered to our circuit board from the function

generator and low-voltage bias power supply jacks, we wired, soldered, and

applied heat-shrink to the 15-pin D-sub connector shown in Figure 5.7.

• To connect to the function generator 8-pin inline header output pins, we

used the mating female crimp contact receptacle also shown in Figure 5.7.

• To connect to the output enable switch voltages from the front panel of our

enclosure, we used a 10-pin inline header with mating crimp contact

receptacle also shown

in Figure 5.7.

• To connect the DC

Input Voltages to our

Input Capacitors and

Power Planes, we used

three parallel lines of

stranded 10AWG wire with crimp/ring connectors.

Fig. 5.7 – Fabricated Wire Harnesses

Source: John Brewer, Jr.

36

• To connect output voltage nodes from the copper-clad circuit board to the

inductors and the LC output filters to the enclosure panel, we used stranded

10AWG wire with crimp/ring connectors. These ring connectors in

conjunction with nuts, bolts, washers, and lock washers made it quick to

assemble and disassemble our prototype for modifications.

5.4 Power Plane Construction

In order to effectively reduce parasitic inductances in the DC Input Voltage

supply path, we used double-sided copper-clad board for the ±input voltage

delivered to the IGBTs. We used a combination of precise cutting and drilling to

create isolated copper pads with at

least a 3:1 ratio of length to width for

current flow. A section of both the

top and bottom power planes are

shown in Figure 5.8.

5.5 Enclosure Fabrication

For ease of transportation,

setup, and testing of our inverter

prototype, Jaime Carmo generously donated his time and materials to fabricate a

Plexiglas enclosure for us. This enclosure allowed us to effectively and efficiently

mount all of our system components and display our project for exhibition.

Fig. 5.8 – Top and Bottom Sides of Copper-Clad Board

Source: John Brewer, Jr.

37

5.6 System Assembly

System assembly consisted of placing and arranging system components,

drilling mounting holes in the Plexiglas enclosure, and fastening components

together or to the enclosure with wire ties, circuit board standoffs, nuts, bolts,

washers, and lock washers. Our final System Assembly is shown in Figure 5.9.

Fig. 5.9 – Inverter System Assembly

Source: John Brewer, Jr.

38

VI.VI.VI.VI. TESTINGTESTINGTESTINGTESTING

For our project, we performed several stages of testing – Ideal Inverter

Pspice simulation, IGBT Gate Driver and Half-Bridge Pspice simulation, PWM Control

Circuit hardware testing, PWM Control Circuit and single IGBT Half-Bridge hardware

low power testing, and full system testing.

For the Ideal Inverter Pspice simulation, we simulated an open-loop

switched-mode single phase PWM inverter circuit with Neutral phase using ideal

components as shown in Figure 6.1 to obtain the output sinusoidal waveform shown

in Figure 6.2.

Fig. 6.1 – Ideal Inverter Pspice Simulation

Source: John Brewer, Jr.

39

For the IGBT Gate Driver and Half-Bridge Pspice simulation shown in

Figure 6.3, we simulated an IR2113 Gate Driver and IRGP50B60PD1 Half-Bridge

driven with a 40kHz, 50% duty cycle square wave with 1μs of deadtime programmed

in between high-side and low-side switching. Despite not being able to use the

Si8234BB IGBT gate driver in our simulation, we were still able to analyze the

bootstrap power supply topology used to turn the high-side IGBT on. The gate-to-

Time

45.0ms 45.5ms 46.0ms 46.5ms 47.0ms 47.5ms 48.0ms 48.5ms 49.0ms 49.5ms 50.0msV(R_LOAD:1)- V(R_LOAD:2)

-120V

-80V

-40V

-0V

40V

80V

120V

Fig. 6.2 – Output Voltage Waveform of Ideal Inverter Simulation

Source: John Brewer, Jr.

Fig. 6.3 – IGBT Gate Driver and Half-Bridge Pspice Simulation

Source: John Brewer, Jr.

40

emitter voltage waveforms

and output current waveform

are shown in Figure 6.4.

We tried to limit the

time spent developing and

analyzing the Pspice

simulations for our inverter

project because it was difficult

to accurately model all of the

parasitic elements that would

affect the high-power performance of our hardware design in the end.

Concurrently, our detail-oriented approach to the design of the PWM Control Circuit

and the thorough analysis of the aforementioned design tips and application notes

published by International Rectifier and Silicon Labs regarding HVIC Gate Drivers and

the bootstrap supply topology warranted immediate prototyping and hardware

testing.

As a result, we constructed a prototype of our PWM Control Circuit design,

tested it, and observed successful results. Because we implemented resistance

trimmers at critical points in the circuit, we were able to fully tune the prototype

design. Next, we constructed a low-power single phase prototype of the IGBT Gate

Driver with bootstrap supply and Half-Bridge topology. At this point in the testing,

0s 5us 10us 15us 20us 25us 30usV(U2:2)- V(U2:3) V(U3:2)- V(U3:3)

-10V

0V

10V

20V

SEL>>

I(Rload)-20A

0A

20A

40A

Fig. 6.4 – High-side (green) and low-side (blue) IGBT

gate-to-emitter voltage waveforms. Load

current waveform (top).

Source: John Brewer, Jr.

41

we encountered problems regarding bias supply ground referencing, low-side

decoupling capacitor sizing, and gate resistance sizing which caused us to take a

closer look at IR’s design notes and modify our circuit design. After doing so, our

testing yielded successful results for low-power switching of our IGBTs using ±39VDC

input supply and less than 1A output current.

After completing assembly of the final version of our proof-of-concept three-

phase inverter design, we performed full system tests. Due to a miscommunication

during a discussion about the DC Power available for testing in Cal Poly’s EE labs, we

were only able to test all three-phases of our inverter with a ±DC input supply

voltage of ±48V due to test equipment voltage and current limits. However, these

tests were all successful.

After powering-up the PWM Control Circuit with the inverter outputs

disabled, we turned on each phase and gradually increased the ±DC input supply

voltage while monitoring all node voltages on the high-voltage side of our circuit –

IGBT Gate Driver pin voltages, IGBT gate, collector, and emitter voltages, supply

voltages, and output voltage. After reaching test equipment current limits, we

reported the following about Figure 6.5 through Figure 6.10:

Fig. 6.5 – Adjustable Three

38kHz Triangle Wave successfully generated and compared wi

signals to produce three

Fig. 6.6 – Trigger Pulse successfully generated by AD823AN Op

Three-Phase Sinusoidal Reference signals successfully generated, UC3637

38kHz Triangle Wave successfully generated and compared with Sinusoidal Reference

signals to produce three-phase PWM Control Input signals.

ger Pulse successfully generated by AD823AN Op-Amp Comparator.

42

signals successfully generated, UC3637

th Sinusoidal Reference

Amp Comparator.

Fig. 6.7 – Square wave with 97% duty cycle successfully generated by Trigger Pulse and HCF4538B

One-Shot.

Fig. 6.8 – Three-phase and Neutral

generated.

Square wave with 97% duty cycle successfully generated by Trigger Pulse and HCF4538B

phase and Neutral-phase Duty Cycle limited PWM Control Input sign

43

Square wave with 97% duty cycle successfully generated by Trigger Pulse and HCF4538B

Duty Cycle limited PWM Control Input signals successfully

Fig. 6.9 –Three-phase Inverter Output Voltage referenced to supply ground with ±48VDC Input

Voltage. Output voltage is 87 V

current is supply limit of 6.5 A.

Fig. 6.10 –Three-phase Inverter Output Voltage reference

Voltage. Output voltage is 86 V

supply limit of 6.5 A.

phase Inverter Output Voltage referenced to supply ground with ±48VDC Input

Voltage. Output voltage is 87 VP-P, 61 VRMS. Output RMS current is 6.2 A. Input RMS

current is supply limit of 6.5 A.

phase Inverter Output Voltage referenced to virtual ground with ±46VDC Input

Voltage. Output voltage is 86 VP-P, 61 VRMS. Output RMS current is 6.2 A. Input RMS current is

44

phase Inverter Output Voltage referenced to supply ground with ±48VDC Input

. Output RMS current is 6.2 A. Input RMS

to virtual ground with ±46VDC Input

. Output RMS current is 6.2 A. Input RMS current is

45

VII.VII.VII.VII. CONCLUSIONCONCLUSIONCONCLUSIONCONCLUSIONSSSS AND RECOMMENDATIONSAND RECOMMENDATIONSAND RECOMMENDATIONSAND RECOMMENDATIONS

Designing and fabricating a proof-of-concept high-voltage switched-mode

three-phase inverter capable of supplying 10kW covered a multitude of design

processes and proved to be a challenging endeavor. However, ensuring that a

detail-oriented approach was taken in the research, design, construction, and testing

stages of this project contributed to its successful completion and thorough

presentation in this report. While the original requirements for this project were

not met due to limitations in lab test equipment, observed test results yielded

successful system performance at lower power levels than intended for nominal

operation. Continued development of the proof-of-concept inverter system that has

been designed and fabricated for this project will assuredly lead to a production-

level version with closed-loop feedback and possibly the following

recommendations.

Given the relatively high-current output capabilities of the Si8234BB HVIC

IGBT Gate Driver, up to two more IGBTs can be placed in parallel with each high-side

and low-side IGBT in the power stage to increase the system current output

capability while maintaining suitable IGBT switching transition times. However,

limitations to this increase in current output capability will rise from parasitic

inductance in the supply current path and action will be necessary to protect against

46

transient voltages. Limitations will also rise from the inability to sufficiently cool

IGBTs while minimizing parasitic inductance by maintaining close IGBT proximity.

The development of a floating supply to replace the bootstrap supply

topology designed for this project would eliminate the duty cycle limitations on the

high-side IGBT. A floating supply able to be ground referenced to the switching

output of the half-bridge would provide for unlimited high-side IGBT on time under

closed-loop control.

Development of a digital microprocessor-based PWM Control system could

potentially reduce the amount of space required by the PWM Control block and

allow for more versatile or accurate control performance. A digital PWM control

system could also have improved noise immunity and temperature tolerance.

If analog PWM control is desired, the design of a well laid-out surface mount

technology PCB is recommended. The signal voltages of the analog system designed

for this project could then be reduced for faster edge transitions so long as the

control circuit is effectively protected from noise and electromagnetic interference

(EMI).

As mention in Section 4.2.3.1, using a ferrite core wrapped with insulated

copper foil for the system inductors would result in lower core and copper losses

than the inductors in the current proof-of-concept system exhibit. This would

decrease the amount of cooling required by the inductors which would increase the

system quality.

47

Having made these recommendations, we maintain that the High-Voltage

Switched-Mode Power Supply for Three-Phase AC Aircraft Systems that we have

designed for this senior project presented to the Electrical Engineering faculty at

California Polytechnic State University, San Luis Obispo will fulfill the requirements

set by the sponsor, Jeff Brewer, after proper high-power testing, tuning, and no

significant design changes have been made.

48

VIII.VIII.VIII.VIII. BIBLIOGRAPHYBIBLIOGRAPHYBIBLIOGRAPHYBIBLIOGRAPHY

[1] Power Semiconductor Device,

http://en.wikipedia.org/wiki/Power_semiconductor_device,

Accessed June 4, 2010.

[2] Brewer, John (Jeff), Director of Electrical Engineering, Aircraft Systems Group,

General Atomics Aeronautical Systems, Inc. Interview.

[3] MIL-STD-704F,

http://www.wbdg.org/ccb/FEDMIL/std704f.pdf,

Accessed June 5, 2010.

[4] International Rectifier Datasheet PD-94625B,

http://www.irf.com/product-info/datasheets/data/irgp50b60pd1.pdf,

Accessed June 6, 2010.

[5] Silicon Labs Datasheet Si8234x,

http://www.silabs.com/Support%20Documents/TechnicalDocs/Si823x.pdf,

Accessed June 7, 2010.

[6] International Rectifier Design Tips DT04-4 Rev A,

http://www.irf.com/technical-info/designtp/dt04-4.pdf,

Accessed June 7, 2010.

[7] ON Semiconductor Datasheet MUR460,

http://www.onsemi.com/pub_link/Collateral/MUR420-D.PDF,

Accessed June 7, 2010.

[8] Unitrode Datasheet UC3637,

http://focus.ti.com/lit/ds/symlink/uc1637.pdf,

Accessed June 7, 2010.

49

[9] Unitrode Design Note DN-53A,

http://focus.tij.co.jp/jp/lit/an/slua184/slua184.pdf,

Accessed June 7, 2010.

[10] Unitrode Application Note U-102,

http://focus.ti.com/lit/an/slua137/slua137.pdf,

Accessed June 7, 2010.

[11] Analog Devices Datasheet AD823AN,

http://www.analog.com/static/imported-files/data_sheets/AD823.pdf,

Accessed June 7, 2010.

[12] STMicroelectronics Datasheet HCF4538B,

http://www.st.com/stonline/books/pdf/docs/2089.pdf,

Accessed June 7, 2010.

[13] Fairchild Semiconductor Datasheet 74AC00,

http://www.fairchildsemi.com/ds/74%2F74AC00.pdf,

Accessed June 7, 2010.

[14] McLyman, Colonel Wm. T. Transformer and Inductor Design Handbook.

Marcel Dekker Inc., Monticello, New York. 2004

[15] PowerLite C-Cores,

http://www.metglas.com/downloads/powerlite.pdf,

Accessed June 8, 2010.

[16] Applied Magnets AWG10-11,

http://www.magnet4less.com/product_info.php?products_id=175,

Accessed June 8, 2010.

50

APPENDICESAPPENDICESAPPENDICESAPPENDICES

A. Schematic

The following pages, 51 through 65, contain the Three-Phase Sinusoidal Inverter

schematic generated for this project.

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

THREE PHASE INVERTER

NOTES: UNLESS OTHERWISE SPECIFIED

CONTENTS

1. ALL RESISTORS ARE 1/8W, 1%

2. ALL CAPACITORS ARE 10%, 50V.

TABLE OF CONTENTS

1 2 3 4 5 6 7

IO CONNECTORS

SIGNAL BUFFERING

NEUTRAL PWM

PHASE-A PWM

PHASE-B PWM

PHASE-C PWM

8

10 11

12

13

14

15

PWM LIMIT LOGIC

PHASE-A GATE DRIVER

9

PWM LIMIT TIMING

PWM LIMIT LOGIC

PHASE-B GATE DRIVER

PHASE-C GATE DRIVER

NEUTRAL GATE DRIVER

OUTPUT FILTERS

Eng

inee

r: J

. BR

EW

ER

, JR

.

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

115

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

115

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

115

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

IO CONNECTORS

THREE PHASE INVERTER

J2

1 9 2 3 10

4 11

5 6 13

7 14

8 15

12

SPARE

SPARE

J1

1 2 3 4 5 6 7 8 9 10

NC

Eng

inee

r: J

. BR

EW

ER

, JR

.

DG

ND

+5V

-15V

15V

_RT

N5V

_RT

N+

15V

12V

_RT

N+

12V

15V

_RT

N15

V_R

TN

5V_R

TN

+15

V-1

5V+

5V15

V_R

TN

5V_R

TN

12V

_RT

N

DG

ND

-190

V_S

UP

PLY

SIN

_A

[3]

SIN

_B

[3]

SIN

_C

[3]

+5V

+5V

+5V

C_S

D_S

WC

H

[16]

5V_R

TN

N_S

D_S

WC

H

[17]

5V_R

TN

A_B

_SD

_SW

CH

[1

4,15

]

5V_R

TN

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

215

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

215

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

215

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

C3

820u

F25

V

C3

820u

F25

V

C4

4.7u

FC

44.

7uF

C5

820u

F25

V

C5

820u

F25

V

C2

4.7u

FC

24.

7uF

C91

560u

FC

9156

0uF

C6

4.7u

FC

64.

7uF

C1

820u

F25

V

C1

820u

F25

V

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SIGNAL BUFFERING

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.

+15

V

-15V

+15

V

-15V

DG

ND

15V

_RT

N

DG

ND

15V

_RT

N

DG

ND

15V

_RT

N

15V

_RT

N

+15

V

15V

_RT

N

-15V

15V

_RT

N

+15

V

15V

_RT

N

-15V

+15

V

+15

V

-15V

-15V

[2]

SIN

_A

SIN

_A_B

UF

[5

]

[2]

SIN

_B

SIN

_B_B

UF

[6

]

TR

I_B

UF

[5

,6,7

,9]

[4]

TR

I_W

AV

E

[2]

SIN

_C

SIN

_C_B

UF

[7

]

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

315

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

315

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

315

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

C9

0.1u

FC

90.

1uF

R7

100k

R7

100k

R2

1.0k

R2

1.0k

R4

100k

R4

100k

C10

10uF

16V

C10

10uF

16V

C11

0.1u

FC

110.

1uF

R3

20k

1/4W

R3

20k

1/4W

U2A

TL0

82U2A

TL0

82+3

-2

V+8

V-4

OU

T1

C7

10uF

16V

C7

10uF

16V

C8

0.1u

FC

80.

1uF

U1B

TL0

82U1B

TL0

82+5

-6

V+8

V-4

OU

T7

C13

10uF

16V

C13

10uF

16VC12

0.1u

FC

120.

1uF

R5

1.0k

R5

1.0k

U1A

TL0

82U1A

TL0

82+3

-2

V+8

V-4

OU

T1

R9

20k

1/4W

R9

20k

1/4W

R1

100k

R1

100k

R8

1.0k

R8

1.0k

U2B

TL0

82U2B

TL0

82+5

-6

V+8

V-4

OU

T7

R6

20k

1/4W

R6

20k

1/4W

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

MASTER PWM

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.-1

5V

-15V

15V

_RT

N

+15

V

15V

_RT

N

15V

_RT

N

15V

_RT

N

-15V

+15

V

+15

V

15V

_RT

N

+15

V

-15V

15V

_RT

N

TR

I_W

AV

E

[3]

NE

UT

RA

L_P

WM

[1

1]

SLV

_TH

RS

H+

[5

,6,7

,9]

SLV

_TH

RS

H-

[5,

6,7,

9]

PW

M_U

VLO

[5

,6,7

]

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

415

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

415

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

415

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

R11

5.62

kR

115.

62k

C19

0.1u

F

C19

0.1u

FR

1610

k1/

4W

R16

10k

1/4W

R12

68.1

kR

1268

.1k

U3

UC

3637

U3

UC

3637

E/A

OU

T17

CT

2

+A

IN11

-AIN

10

+B

IN8

-BIN

9

AO

UT

4

BO

UT

7

+C

/L12

-C/L

13

+E

/A15

-E/A

16

ISE

T18

SD

14

+V

TH

1

-VT

H3

+V

S6 5

-VS

R13

5.62

kR

135.

62k

R20

150k

R20

150k

R15

47.5

kR

1547

.5k

R19

150k

R19

150k

C14

300p

FC

1430

0pF

C15

0.1u

FC

150.

1uF

R17

100k

R17

100k

R14

20.5

kR

1420

.5k

C87

0.1u

FC

870.

1uF

R10

20.5

kR

1020

.5k

C18

0.1u

F

C18

0.1u

F

R18

330k

R18

330k

C16

0.1u

FC

160.

1uFC

170.

1uF

C17

0.1u

F

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PHASE-A PWM

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.

+15

V

15V

_RT

N

-15V

15V

_RT

N15

V_R

TN

15V

_RT

N15

V_R

TN

[4]

SLV

_TH

RS

H+

[4]

SLV

_TH

RS

H-

[3]

TR

I_B

UF

A_P

WM

[1

0]

[4]

PW

M_U

VLO

[3]

SIN

_A_B

UF

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

515

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

515

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

515

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

C20

0.1u

FC

200.

1uF

U4

UC

3637

U4

UC

3637

E/A

OU

T17

CT

2

+A

IN11

-AIN

10

+B

IN8

-BIN

9

AO

UT

4

BO

UT

7

+C

/L12

-C/L

13

+E

/A15

-E/A

16

ISE

T18

SD

14

+V

TH

1

-VT

H3

+V

S6 5

-VS

C22

0.1u

FC

220.

1uF

C23

0.1u

F

C23

0.1u

F

C21

0.1u

FC

210.

1uF

C24

0.1u

F

C24

0.1u

F

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PHASE-B PWM

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.

+15

V

15V

_RT

N

-15V

15V

_RT

N15

V_R

TN

15V

_RT

N15

V_R

TN

[4]

SLV

_TH

RS

H+

[4]

SLV

_TH

RS

H-

[3]

TR

I_B

UF

B_P

WM

[1

0]

[4]

PW

M_U

VLO

[3]

SIN

_B_B

UF

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

615

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

615

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

615

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

C28

0.1u

F

C28

0.1u

F

C25

0.1u

FC

250.

1uF

U5

UC

3637

U5

UC

3637

E/A

OU

T17

CT

2

+A

IN11

-AIN

10

+B

IN8

-BIN

9

AO

UT

4

BO

UT

7

+C

/L12

-C/L

13

+E

/A15

-E/A

16

ISE

T18

SD

14

+V

TH

1

-VT

H3

+V

S6 5

-VS

C29

0.1u

F

C29

0.1u

FC

270.

1uF

C27

0.1u

FC

260.

1uF

C26

0.1u

F

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PHASE-C PWM

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.

+15

V

15V

_RT

N

-15V

15V

_RT

N15

V_R

TN

15V

_RT

N15

V_R

TN

[4]

SLV

_TH

RS

H+

[4]

SLV

_TH

RS

H-

[3]

TR

I_B

UF

C_P

WM

[1

1]

[4]

PW

M_U

VLO

[3]

SIN

_C_B

UF

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

715

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

715

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

715

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

C31

0.1u

FC

310.

1uF

C30

0.1u

FC

300.

1uF

C33

0.1u

F

C33

0.1u

F

U6

UC

3637

U6

UC

3637

E/A

OU

T17

CT

2

+A

IN11

-AIN

10

+B

IN8

-BIN

9

AO

UT

4

BO

UT

7

+C

/L12

-C/L

13

+E

/A15

-E/A

16

ISE

T18

SD

14

+V

TH

1

-VT

H3

+V

S6 5

-VS

C32

0.1u

FC

320.

1uF

C34

0.1u

F

C34

0.1u

F

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PWM LIMIT TIMING

THREE PHASE INVERTER

16 8

6 10

1 2 3 4 5 11 12 13 14 15

7 9

Cx(

1)

RxC

x(1)

RE

SE

T(1

)

+T

R(1

)

-TR

(1)

-TR

(2)

+T

R(2

)

RE

SE

T(2

)

RxC

x(2)

Cx(

2)V

ss

VD

D

Q1

Q1/

Q2

Q2/

HC

F45

38B

U8

Eng

inee

r: J

. BR

EW

ER

, JR

.

+15

V

+15

V

15V

_RT

N

+15

V

15V

_RT

N

15V

_RT

N

15V

_RT

N

+15

V

-15V

-15V

15V

_RT

N

-15V

15V

_RT

N

15V

_RT

N

DU

TY

_LIM

IT

[10,

11]

[4]

SLV

_TH

RS

H+

[3]

TR

I_B

UF

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

815

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

815

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

815

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

R21

1.0k

R21

1.0k

D1

SD

103A

D1

SD

103A

C39

0.1u

F

C39

0.1u

F

U7B

AD

823A

NU

7BA

D82

3AN

+5

-6

V+8

V-4

OU

T7

C38

5600

pFC

3856

00pF

R22

10k

1/4W

R22

10k

1/4W

U7A

AD

823A

NU

7AA

D82

3AN

+3

-2

V+8

V-4

OU

T1

C37

0.1u

FC

370.

1uF

C36

0.1u

FC

360.

1uF

C35

0.1u

FC

350.

1uF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PWM LIMIT LOGIC

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.

15V

_RT

N

15V

_RT

N

15V

_RT

N

15V

_RT

N

+5V

5V_R

TN

15V

_RT

N

15V

_RT

N

[9]

DU

TY

_LIM

IT

[5]

A_P

WM

A_D

RIV

E

[14]

B_D

RIV

E

[15]

[9]

DU

TY

_LIM

IT

[6]

B_P

WM

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

915

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

915

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

915

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

R24

10.2

k

R24

10.2

k

C40

0.1u

FC

400.

1uF

R23

10.2

k

R23

10.2

k

U9D

74A

C00

U9D

74A

C00

12 1311

D2

SD

103A

D2

SD

103A

R28

10.2

k

R28

10.2

k

R26

20.5

k

R26

20.5

k

R25

10.2

kR

2510

.2k

U9B

74A

C00

U9B

74A

C00

4 56

R27

10.2

kR

2710

.2k

D3

SD

103A

D3

SD

103A

U9C

74A

C00

U9C

74A

C00

9 108

R31

20.5

k

R31

20.5

k

R29

10.2

k

R29

10.2

k

U9A

74A

C00

U9A

74A

C00

1 23

R32

10.2

kR

3210

.2k

R30

10.2

kR

3010

.2k

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PWM LIMIT LOGIC

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.

15V

_RT

N

15V

_RT

N

15V

_RT

N

15V

_RT

N

+5V

5V_R

TN

15V

_RT

N

15V

_RT

N

[9]

DU

TY

_LIM

IT

[9]

DU

TY

_LIM

IT

[7]

C_P

WM

[4]

NE

UT

RA

L_P

WM

C_D

RIV

E

[16]

NE

UT

RA

L_D

RIV

E

[17]

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1015

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1015

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1015

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

R36

20.5

k

R36

20.5

k

U10

C

74A

C00

U10

C

74A

C00

9 108

R33

10.2

k

R33

10.2

k

R37

10.2

kR

3710

.2k

R39

10.2

k

R39

10.2

kR

4010

.2k

R40

10.2

k

R41

20.5

k

R41

20.5

k

U10

D

74A

C00

U10

D

74A

C00

12 1311

D4

SD

103A

D4

SD

103A

R42

10.2

kR

4210

.2k

U10

A

74A

C00

U10

A

74A

C00

1 23

R38

10.2

k

R38

10.2

k

R35

10.2

kR

3510

.2k

D5

SD

103A

D5

SD

103A

C41

0.1u

FC

410.

1uF

U10

B

74A

C00

U10

B

74A

C00

4 56

R34

10.2

k

R34

10.2

k

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PHASE-A GATE DRIVER

THREE PHASE INVERTER

6

10

4 5

11121314

7

9

DIS

AB

LE

DT

NC

VD

DI

GN

DI

GN

DB

Si8

234B

B

U11

1 2 3 8

1516P

WM

NC

VD

DI

VO

B

VD

DB

NC

NC

GN

DA

VO

A

VD

DA

Eng

inee

r: J

. BR

EW

ER

, JR

.

+5V

5V_R

TN

15V

_RT

N

+15

V

+19

0V

-190

V15

V_R

TN

+15

V

5V_R

TN

[2]

A_B

_SD

_SW

CH

PH

AS

E_A

[1

8]

[10]

A

_DR

IVE

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1115

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1115

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1115

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

C45

0.1u

FC

450.

1uF

R45 4.

7

R45 4.

7

D8

MU

R46

0D

8M

UR

460

D6

MU

R46

0D

6M

UR

460

C49

0.1u

FC

490.

1uF

16V

D10

16V

D10

C48

10uF

C48

10uF

C46

0.33

uFC

460.

33uF

U12

IRG

P50

B60

PD

1

U12

IRG

P50

B60

PD

1

11

22

33

R43

100k

1/4W

R43

100k

1/4W

C43

0.1u

FC

430.

1uF

16V

D9

16V

D9

C47

0.33

uFC

470.

33uF

U13

U13

11

22

33

C82

0.33

uFC

820.

33uF

16V

D7

16V

D7

C44

10uF

C44

10uF

R44 3.

9

R44 3.

9

C42

0.1u

F

C42

0.1u

F

C86

0.1u

FC

860.

1uF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PHASE-B GATE DRIVER

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.

21 83

16 15N

C

PW

M

VO

B

VD

DI

NC

VD

DB

GN

DA

NC

VD

DA

VO

A

10

611

5413 1214

7

9

DT

DIS

AB

LE

NC

GN

DI

VD

DI

GN

DB

U14

Si8

234B

B

+5V

5V_R

TN

15V

_RT

N

+15

V

+19

0V

-190

V15

V_R

TN

+15

V

5V_R

TN

[2]

A_B

_SD

_SW

CH

PH

AS

E_B

[1

8]

[10]

B

_DR

IVE

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1215

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1215

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1215

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

16V

D14

16V

D14

C83

0.33

uFC

830.

33uF

16V

D16

16V

D16

C50

0.1u

F

C50

0.1u

F

C56

10uF

C56

10uF

D15

MU

R46

0D

15M

UR

460

C88

0.1u

FC

880.

1uF

C53

0.1u

FC

530.

1uF C

550.

33uF

C55

0.33

uF

U15

IRG

P50

B60

PD

1

U15

IRG

P50

B60

PD

1

11

22

33

R46

100k

1/4W

R46

100k

1/4W

C51

0.1u

FC

510.

1uF

C52

10uF

C52

10uF

R47 3.

9

R47 3.

9

U16

U16

11

22

33

R48 4.

7

R48 4.

7

C57

0.1u

FC

570.

1uF

C54

0.33

uFC

540.

33uF

16V

D17

16V

D17

D13

MU

R46

0D

13M

UR

460

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PHASE-C GATE DRIVER

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.

21 83

16 15N

C

PW

M

VO

B

VD

DI

NC

VD

DB

GN

DA

NC

VD

DA

VO

A

10

611

5413 1214

7

9

DT

DIS

AB

LE

NC

GN

DI

VD

DI

GN

DB

U17

Si8

234B

B

+5V

5V_R

TN

15V

_RT

N

+15

V

+19

0V

-190

V15

V_R

TN

+15

V

5V_R

TN

[2]

C_S

D_S

WC

H

PH

AS

E_C

[1

8]

[11]

C

_DR

IVE

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1315

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1315

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1315

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

C63

0.33

uFC

630.

33uF

U18

IRG

P50

B60

PD

1

U18

IRG

P50

B60

PD

1

11

22

33

C59

0.1u

FC

590.

1uF

C60

10uF

C60

10uF

R50 3.

9

R50 3.

9

U19

U19

11

22

33

R51 4.

7

R51 4.

7

C65

0.1u

FC

650.

1uF

C89

0.1u

FC

890.

1uF

C62

0.33

uFC

620.

33uF

16V

D24

16V

D24

D20

MU

R46

0D

20M

UR

460

16V

D21

16V

D21

16V

D23

16V

D23

C84

0.33

uFC

840.

33uF

C58

0.1u

F

C58

0.1u

F

R49

100k

1/4W

R49

100k

1/4W

C64

10uF

C64

10uF

D22

MU

R46

0D

22M

UR

460

C61

0.1u

FC

610.

1uF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

NEUTRAL GATE DRIVER

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.

21 83

16 15N

C

PW

M

VO

B

VD

DI

NC

VD

DB

GN

DA

NC

VD

DA

VO

A

10

611

5413 1214

7

9

DT

DIS

AB

LE

NC

GN

DI

VD

DI

GN

DB

U21

Si8

234B

B

+5V

5V_R

TN

15V

_RT

N

+15

V

+19

0V

-190

V15

V_R

TN

+15

V

5V_R

TN

[2]

N_S

D_S

WC

H

NE

UT

RA

L [

18]

[11]

N

EU

TR

AL_

DR

IVE

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1415

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1415

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1415

Mon

day,

Jun

e 07

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

R53 3.

9

R53 3.

9

U22

U22

11

22

33

R52

100k

1/4W

R52

100k

1/4W

R54 4.

7

R54 4.

7

C73

0.1u

FC

730.

1uF

C70

0.33

uFC

700.

33uF

16V

D31

16V

D31

D27

MU

R46

0D

27M

UR

460

C85

0.33

uFC

850.

33uF

16V

D28

16V

D28

16V

D30

16V

D30

C66

0.1u

F

C66

0.1u

F

C72

10uF

C72

10uF

D29

MU

R46

0D

29M

UR

460

C69

0.1u

FC

690.

1uF C

710.

33uF

C71

0.33

uF

U21

IRG

P50

B60

PD

1

U21

IRG

P50

B60

PD

1

11

22

33

C67

0.1u

FC

670.

1uF

C90

0.1u

FC

900.

1uF

C68

10uF

C68

10uF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

OUTPUT FILTERS

THREE PHASE INVERTER

Eng

inee

r: J

. BR

EW

ER

, JR

.

-190

V

+19

0V

PW

R_G

ND

PW

R_G

ND

PW

R_G

ND

PW

R_G

ND

SIN

_A_O

UT

SIN

_B_O

UT

SIN

_C_O

UT

[14]

P

HA

SE

_A

[15]

P

HA

SE

_B

[16]

P

HA

SE

_C

[17]

N

EU

TR

AL

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1515

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1515

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

A

1515

Sun

day,

Jun

e 06

, 201

0

ES

CH

EM

AT

IC, T

HR

EE

PH

AS

E IN

VE

RT

ER

C80

3300

uF35

0V

C80

3300

uF35

0V

C74

20uF

400V

C74

20uF

400V

L1 160u

H

L1 160u

H

C81

3300

uF35

0V

C81

3300

uF35

0V

L2 160u

H

L2 160u

H

C79

20uF

400V

C79

20uF

400V

L3 160u

H

L3 160u

H

C77

20uF

400V

C77

20uF

400V

L4 160u

H

L4 160u

H

C78

20uF

400V

C78

20uF

400V

C76

20uF

400V

C76

20uF

400V

C75

20uF

400V

C75

20uF

400V

66

B. Bill of Materials

Table B.1 – Bill of Materials and Donated Items

Item Unit

Price ($) Quantity

Total

Price ($)

Hardware

CS Hyde Metalized Mylar Tape, 2.2 mil. Thick,

1' x 72 yds 13.5 1 13.5

SPDT 6A F.LVR Switch 3.69 2 7.38

SPDT 6A R.LVR Switch 3.69 1 3.69

D-Sub 15 Pin Male 2.49 1 2.49

D-Sub 15 Pin Female 2.49 1 2.49

Pre-Punched IC-Spacing Perfboard 2-3/4"x6" 3.99 3 11.97

2-Sided Cooper Clad Board 4.5"x6.125" 3.99 3 11.97

Assorted Cable Ties 8" 5.99 1 5.99

8-10 Stud Ring Terminals 0.14 21 2.94

Door Handles 3.49 2 6.98

PCB Standoff 1" 0.45 4 1.8

PCB Standoff 2 1/4" 0.35 2 0.7

Crimp Pins Male 0.1 15 1.5

Plastic Rectangular Crimp Pin Receptacle 0.5 2 1

Corner Brace 1-1/2" 0.63 4 2.52

White Screw Bumper 0.49 8 3.92

Ring Tongue Connector 0.25 13 3.25

#4-40 x 1/2' Round Head - Slotted Bolt 0.1 12 1.2

#4-40 x 1/2' Round Head - Phillips Bolt 0.1 4 0.4

#4-40 Nut 0.03 10 0.3

#6-32 x 3/8' Round Head - Slotted Bolt 0.1 16 1.6

#6-32 Nut 0.03 16 0.48

#6 Lock Washer 0.06 28 1.68

#6 SAE Washer 0.03 40 1.2

#10-32 x 3/8" Round Head - Slotted Bolt 0.1 8 0.8

#10-32 x 1/2" Round Head - Slotted Bolt 0.1 8 0.8

#10-32 x 5/8" Round Head - Slotted Bolt 0.1 5 0.5

#10-32 x 3/4" Round Head - Slotted Bolt 0.1 16 1.6

#10-32 x 1" Rounded - Slotted Bolt 0.1 9 0.9

#10-32 x 1/2" Flat Head- Phillips Bolt 0.1 8 0.8

#10-32 Nut 0.03 59 1.77

#10 Lock Washer 0.06 75 4.5

#10 SAE Washer 0.03 69 2.07

Aluminum Flat Plate 9.85 1 9.85

67

Polyolenfin Heat Shrink Tubing 3/32" 1.79 1 1.79

Polyolenfin Heat Shrink Tubing 3/32" 1.95 1 1.95

IC Socket Mach Pin WW 8Pos Gold - AR08-HZW/T-R 1.69 3 5.07

IC Socket Mach Pin WW 14Pos Gold - AR14-HZW/T-R 2.53 2 5.06

IC Socket Mach Pin WW 16Pos Gold - AR16-HZW/T-R 2.9 5 14.5

IC Socket Mach Pin WW 18Pos Gold - AR18-HZW/T-R 2.9 4 11.6

Square Machine Post - 100 4.99 1 4.99

Coaxial DC Power Jack 3.29 4 13.16

Coaxial DC Power Plug 3.29 4 13.16

Electronics

Texas Instruments - OpAmp Dual JFET Input -

TL082CP 0.77 2 1.54

Unitrode - SM Crtl for DC Motor Drive - UC3637 7.28 4 29.12

Analog Devices Inc - OpAmp JFET R-R Dual -

AD823AN 5.64 1 5.64

Fairchild Semiconductor - Quad 2 Input Nand -

74AC00B 0.6 2 1.2

International Rectifier - IGBT - IRGP50B60PD1 8.28 16 132.48

STMicroelectronics - Multivibrator - HCF4538B 0.65 1 0.65

Silicon Labs - High Side / Low Side Driver - Si8234BB 3.71 4 14.84

Mallory CGS332T350X5L 3300μF 350VDC Capacitor 71.45 2 142.9

United Chemi-Con - Cap Elect 820uF 50V 1.29 3 3.87

Panasonic - ECG - Cap 4.7uf 25V Cer - PCC2251CT-ND 0.79 3 2.37

TDK Corp - Cap Cer 10uF 16V X7R RAD -

FK20X7R1C106K 0.83 3 2.49

Panasonic - ECG - Cap Elect 10uF 400V - EEU-

ED2G100 0.67 8 5.36

BC Components - Cap Cer .10UF 50V -

K104K15X7RF5TH5 0.06 51 3.06

Murata Electronics NA - Cap Cer 300pF 50V 0.3 1 0.3

Murata Electronics NA - Cap Cer 5600pF 50V 0.62 1 0.62

TDK Corporation - Cap Cer 0.33uF 50V -

FK24X7R1H334K 0.21 12 2.52

United Chemi-Con - Cap Elect 560uF 50V 0.86 1 0.86

Diodes Inc - Diode Schottky 40V 400MW - SD103A-T 0.65 5 3.25

ON Semiconductor - Switchmode -Diode 4A 600V 0.65 8 5.2

Murata Electronics NA - Trim Pot Cerm 100kOhm - 1.38 8 11.04

Stackpole Electronics Inc - RES 1kOhm 1/8W 5% - 0.09 4 0.36

Murata Electronics NA - Trim Pot Cer 20kOhm 1.38 3 4.14

Yageo - Res 20.5kohm 1/4W 1% Metal Film 0.57 6 3.42

Stackpole Electronics - Res MF 1/8W 5.62kOhm 1% 0.15 2 0.3

Stackpole Electronics Inc - Res MF 1/8W

68.1kOhm 1% 0.15 1 0.15

68

Stackpole Electronics Inc - Res MF 1/8W

47.5kOhm 1% 0.15 1 0.15

Murata Electronics NA - Trim Pot Cerm

10kOhm 12Trn 1.81 2 3.62

Stackpole Electronics Inc - Res MF 1/8W

330kOhm 1% 0.15 1 0.15

Stackpole Electronics Inc - Res MF 1/8W

150kOhm 1% 0.15 2 0.3

Stackpole Electronics Inc - Res MF 1/8W

10.2kOhm 1% 0.15 16 2.4

Stackpole Electronics Inc - Res MF 1/8W 3.9Ohm 1% 0.15 4 0.6

Stackpole Electronics Inc - Res MF 1/8W 4.7Ohm 1% 0.15 4 0.6

Wire

UL- Stranded Hookup Wire - 22AWG - Red 25' 2.33 1 2.33

UL- Stranded Hookup Wire - 22AWG - Green 25' 2.33 1 2.33

UL- Stranded Hookup Wire - 22AWG - Black 25' 2.33 1 2.33

10AWG - Mil Spec - M81044/ 9-10-9 - White 10' 4 1 4

10AWG - Mil Spec - M81044/ 9-10-0 - Black 10' 4 1 4

26AWG - Stranded HookupWire - Red - 25' 2.25 1 2.25

26AWG - Stranded HookupWire - Black - 25' 2.25 1 2.25

26AWG - Assorted Stranded HookupWire - 25' 4.99 1 4.99

Magnet Wire / Winding Wire - 10 AWG, 11LBS 124.99 1 124.99

Wire Roll Repl 30AWG Blue 50' 9.12 1 9.12

Wire Roll Repl 30AWG Yellow 50' 9.12 1 9.12

Wire Roll Repl 30AWG Green 50' 9.12 1 9.12

Wire Roll Repl 30AWG Orange 50' 9.12 1 9.12

Grand

Total 757.27

Donated Items Quantity

Plexiglass Project Box 22 3/8"X 20 1/8" X 9 1/4" 1

dsPIC Funtion Generator 1

Electrocube 945B 20μF 400VDC Capacitor 6

Powerlite C-Core AMCC 50 8

Powerlite Bobbin AMCC-50BOB 8

69

C. Circuit Board Layout

Fig. C.1 – Microsoft PowerPoint Circuit Board Layout

Source: John Brewer, Jr. and Kamaljit Bagha

70

D. Circuit Board IC and Component Locations

Fig. D.1 – IC and Component Circuit Board Location

Source: John Brewer, Jr. and Kamaljit Bagha

71

E. Hardware Configuration and Layout

Fig. E.1 – Hardware Configuration and Layout

Source: Kamaljit Bagha

72

Fig. E.2 – Test Bench Setup

Source: Kamaljit Bagha