High-Speed Serial Interface Circuits and Systems

Lect. 1 – Introduction

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● Goals

● Lecturer: Prof. Woo-Young Choi (최우영) Room: B625, Tel: 02-2123-2874 Email: wchoi@yonsei.ac.kr, Web: tera.yonsei.ac.kr

● Prerequisite- Solid background in electronic engineering- Proficiency in CMOS electronic circuits

- Introduction to high-speed serial interface circuits and systems- Design practice for high-speed serial interface circuits

High-Speed Serial Interface

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Network Interface• Wireline/Wireless

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PPPoE: Point-to-Point Protocol over Ethernet

Interfaces inside Desktop Computer

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Interfaces inside Smartphone

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mipi: Mobile Industry Processor Interface

LLI: Low Latency Interface SSIC: Super Speed InterChipUniPort: Unified Protocol

UFS: Universal Flash StorageDigRF: Digital RF

DSI: Display Serial InterfaceCSI: Camera Serial Interface

D-PHY: 80Mbs to 1Gbps, no symbol coding, no CDRM-PHY: up to 5Gbps, 8B10B, CDR

SLIMBus: Serial Low-Power Inter-Chip Media Bus

SPMI: System Power Management Interface

BIF: Battery Interface

GBT: Giga Bit Trace

RFFE: RF Front-End

Why “serial”?• Problems with parallel interface

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Channel

Channel

DATAN

CLK

Channel

Channel

DATA1

DATA2

Tx Rx

N+1 pins!

Sampler

Sampler

Sampler

– Pin count / package / PCB wiring constraint– Skew

Why “serial”?• Serial interface

– To send only high-speed data / to recover clock in Rx side– No skew problem / only 2 pin count– Often differential signals for common-mode noise, supply noise

rejection

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ChannelDATA+

ChannelDATA-

Tx Rx

Only 2 pins

Sampler

ClockRecovery

Why “serial”?• Gigabit Media Independent Interface- Reduced area, power, complexity lower cost- Reduced crosstalk, SSN, EMI lower BER

9http://www.eetimes.com/design/communications-design/4142422/Going-Serial-in-Gigabit-Ethernet-Designs

• Data-rate requirement continuously increases

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Trends for Higher Speed

Display trendHigher resolution

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(Ultra High Definition)

(High Definition)(Full High Definition)

(Wide Quad High Definition)

Higher-Speed Interfaces in Desktop Computers

• Key bandwidth bottleneck points are memory (FSB: Front-Side Bus) and graphics interface (PCIe)

Integrated memory controller with serial I/O (5Gb/s) to memory

Increasing PCIe from 2.5Gb/s (Gen1) to 16Gb/s (Gen4)

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Interfaces in Notebook

2013-113

USB 3.0 (Universal Serial Bus): 5Gb/s

PCI Express 2.0 (Peripheral Component Interconnect Express): 5Gb/s

LPDDR3 (Low Power Double Data Rate Dynamic Random Access Memory): 6.4Gb/s

USB 2.0 (Universal Serial Bus): 480Mb/s

eDP (Embedded DisplayPort) : 2.7Gb/s

Thunderbolt : 10.3125 Gb/s

DisplayPort 1.2 : 5.4Gb/s

Mac Book Air

Demands for Higher-Speed Interface (larger I/O bandwidth)

• Single Multi Many-Core μProcessors

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Key Block Diagram

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Serializer TxDriver

RxEqualizer Sampler

ClockRecovery

Deserializer

PLL

Channel

Tx Rx

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n

12n …12

n

- High-speed interface- High-speed digital I/O - High-speed serdes (Serializer/Deserializer)

Research Trends

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(Fom "Introduction to Digital I/O",IEEE Solid-Sate Circuits Magazine,Fall 2015)

(Based on papers presented at ISSCC) (Based on papers presented at ISSCC)

Key Block Diagram

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References- "Design of Integrated Circuits for Optical Communications" by Razavi- Lecture notes for "High-Speed Links Circuits and Systems", Prof. Palermo, TAMU

Topics to be cover in this course- PLL- Tx Driver, Channel, Equalizer- Serializer/Deserizer/CDR

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- Tests (2, 30% )- Design Exercise (Every week, 30%)- Design Projects (2, 30% ) - Attendance and class participation (10%)

● Grades

● Tuesday: Lecture on a topicThursday: Design Exercise

Class hour changes Tuesday: 9:30 – 10:45 am (B701, except on 3/8 when we meet at A125

for Spectre tutorial)Thursday: 11:00 – 12:15 am (A125)

Display trend

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Pixels Frame rate Bit/pixel Data rate

HD 1280x720 30 24 663Mb/s

FHD 1920x1080 60 24 3Gb/s

WQHD 2560x1440 60 24 5.3Gb/s

UHD 4096x2160 60 24 12Gb/s

Graphics display solution