High Speed Digital Systems Lab

Asic Test Platform

Supervisor: Michael Yampolsky

Assaf Mantzur Gal Rotbard

Project Midterm Presentation One-Semester Project

Winter 2008/09

February 09

Reminder: Tester Objectives

• The tester objective is to test the functional correctness of the component

• The tester provides inputs to the component and compares the outputs with the expected/wanted outputs

• Allow the user to:– Determine the test vectors– Configure the application for the DUT and save the

configuration for further use– View and analyze results

Reminder: Project DescriptionHOST

User Interface

FPGA (with PSDB)

Component

Input

DUT

Known Functionality

Reminder: Application Description

•PCI

BUS

•FPGA

•Analyzer

•Controller

•The Host

Application

Generator

Progress so far…

• Set a communication Protocol between the software and the hardware

• Close a loop with the hardware

• Basic design of the host application GUI

SW

HW

Inputs->outputs

Host application

DDR 2 BANK A

Page1

Page2

DDR 2 BANK B

Page1

Page2

FPGA(short)

DMADMA

PCI BU

S

PCI BU

S

The Host Application• Application User Interface:– Our application will have two main screens:• Configuration• Debug

– Our host will interact with the user through these screens

• Application to HW interface– Using the protocol decided by both groups, we will

interact with the FPGA through registers

Configuration mode• Allow the user to configure system to the DUT

parameters and save them in a configuration file (for further use)– For each DUT that has a saved configuration file ,

the user will not need to reconfigure it, only to load the file.

• The application will fill the relevant registers with the configuration information for the HW (according to protocol) in debug mode

Configuration mode screen

Configuration mode – Pins table• The user will add inputs and outputs to the pins

table• The pins (or buses) will be added

with a name (decided by the user)• The user will fill the test values

(in the .csv file) according to thenames given in this pinstable

• We will create a Template for the.csv file according to pins table(future slide)

Debug Mode• This is the main part of our application• This mode allows the user to:– Load the configuration into the Tester’s registers– Load the inputs file– Load Macro file (instructions)– Load wanted outputs (golden model)– Save the current outputs– Compare outputs

Debug mode screen

Debug Mode – Load Tester• Load the configuration into the Tester’s

registers– In this part, the application will verify that the DUT

ID matches the ID we receive from the HW.– If not, an error screen will appear

Debug Mode – Load inputs file• The user will load the inputs (test vectors)

through a .csv file– .csv is created through Microsoft Office Excel

• Example:– A is an 8 bit input bus– B is a one bit input pin – C is a 3 bit input bus

• Each line represents aninput cycle and producesan output value

Debug Mode – Load Macro file• The user will load a Macro (.txt) file with

Macro instructions for our application• We will implement it as an interpreted

language

Debug Mode – outputs• Load Wanted outputs– Loads a .csv file with wanted outputs (golden

model) according to input file• Save outputs– Save the outputs in a .csv file (can be opened with

Microsoft Office Excel)• Compare– Compares two files and produces a comparison

report

Application Debug modes• Run System– Verifies that the configuration, input file and

Macro file were all loaded successfully • Stop system• In order to check the system, there will be a

test mode with two modes:– System self test– Internal loop (protocol)

Future ScheduleAssignment Date

•Finishing I/O loop with h/w (Milestone)•Finishing application GUI design•Separation from h/w group

1/2 – 10/2

•Application and GUI implementation•Implementation of Configuration Mode

11/2 – 28/2

•Implementation of Debug Mode 1/3 – 14/3

•System Test and Debug 15/3 – 28/3

•Final Presentation 29/3