High Speed Digital Design Project
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High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date: Januar 2010 Part B - Final Presentation
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High Speed Digital Design Project. SpaceWire Router. Part B - Final Presentation. Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date: Januar 2010. Project Goal. - PowerPoint PPT Presentation
Transcript of High Speed Digital Design Project
High Speed Digital Design ProjectSpaceWire Router
Student: Asaf BercovichInstructor: Mony OrbachSemester: Winter 2009/20102-Semester ProjectDate: Januar 2010
Part B - Final Presentation
Project Goal• Designing a SpaceWire Switch Core (Router)
compatible to ECSS-E-50-12A standard with the “Path Addressing” routing scheme.
Project Results• D1117_SPWPort – SpaceWire Network Device• D1117_SPWRepeater – SpaceWire Network Repeater• D1117_SPWRouter – SpaceWire Router
System Topology
SpaceWire Router
System Topology
D1117_SPWRouter
PORT
• Low latency• Point-to-point• Wormhole
Routing• Asynchronous
communication• Path Addressing• 100 Mb/s of Total
Traffic.
Layer 2 (Character Level) Network Port
Receiver
D1117 SpaceWire PortArchitecture
Port Controller
DinSin
DoutSout
Sys Clock
Reset
RX DATA / Control
TX DATA / Control
Link Start
State Machine
Transmitter
FIFORX CLOCK
FIFO
Write
Ready
ReadyRead
Read
Ready
ReadyWrite
Link Ready
Tx Clock
System Topology
D1117_SPWRouter
PORT
• Low latency• Point-to-point• Wormhole
Routing• Asynchronous
communication• Path Addressing• 100 Mb/s of Total
Traffic.
SpaceWire Packet Format
<DESTINATION<<CARGO<<END OF PACKET<
SpaceWire Packet
A SpaceWire ‘Routing Switch’ shall transfer packets from the input port of the switch where the packet arrives, to a particular output port determined by the packet destination address.
SpaceWire ‘Routing Switch’
Routing with Path-Addressing
4 3 2 Cargo EOP
Layer 2 Repeater
SPW Port-0
Read Interface
RX_EMPTY
READ_EN
RX_CONTROL
RX_DATASPW
Por
t-1
Writ
e In
terf
ace TX_FULL
TX_WRITE
TX_CONTROL
TX_DATA
SpaceWire Connection Broker
SpaceW
ire signals
SpaceW
ire signals
D1117_SPWRepeater
ENABLE
Router Architecture
Read Interface
Read Interface S
paceWire M
ux
SPW Port-0
Read Interface
RX_EMPTY
READ_EN
RX_CONTROL
RX_DATA
SPW Port-1
Read Interface
RX_EMPTY
READ_EN
RX_CONTROL
RX_DATA
SPW Port-2
Read Interface
RX_EMPTY
READ_EN
RX_CONTROL
RX_DATA
SPW
Por
t-0
Writ
e In
terf
ace TX_FULL
TX_WRITE
TX_CONTROL
TX_DATA
SPW
Por
t-1
Writ
e In
terf
ace TX_FULL
TX_WRITE
TX_CONTROL
TX_DATA
SPW
Por
t-2
Writ
e In
terf
ace TX_FULL
TX_WRITE
TX_CONTROL
TX_DATA
Writ
e In
terf
ace
Writ
e In
terfa
ce S
pace
Wire
Mux
RX_EMPTY
READ_EN
RX_CONTROL
RX_DATA
TX_FULL
TX_WRITE`
TX_CONTROL
TX_DATA
SpaceWire Connection Broker
Source Address Register
SpaceWire Router Control
HEA
DER
_DELETIO
N
EN_D
EST_AD
DR
_REG
ISTER
REGISTERED_SOURCE_ADDR
Packet Detection
Unit
Destination Address Register
REGISTERED_DEST_ADDR
SYSTEM_CLOCK
EN_SO
UR
CE_A
DD
R_R
EGISTER
EOP Detection
Unit
EN_PA
CK
ET_DELIVERY
PACKET_DETECTEDEOP_DETECTED
Router Controller
PACKET_DETECTED=1EOP_DETECTED=1
“CONFIGURESOURCEADDRESS”
EN_SRC_ADDR_REGISTER = 1 All other controller output signals are zero.
“CONFIGUREDESTINATION
ADDRESS”EN_DEST_ADDR_REGISTER = 1
HEADER_DELETION = 1 All other controller output signals are zero.
“WAIT FOR EOP/EEP”
EN_PACKET_DELIVERY = 1All other controller output signals are zero.
“IDLE”All controller output signals are zero.
“RESET”
SPW PORT RESET = 1All other controller output signals are zero.
Hardware in test• GR-RASTA running D1117_SPWRouter
as SpaceWire router.
• Gaisler GRESB – Gaisler Ethernet Bridge.(To be explained.)
• 3 PCs as SpacWire stations connected to one D1117 SpaceWire Router. Together they form a SpaceWire network based on ‘Path Addressing’ routing.
Software in test• TCP Test Tool 2.3 Freeware.
www.SimpleComTools.com
Main Test Topology
Core : D1117 SpaceWire RouterFPGA : GR-RASTA
SPW-0 SPW-1 SPW-2
Logic LinkPC-0
OS: WindowsPC-1
OS: WindowsPC-2
OS: Windows
Main Test Topology
Core : D1117 SpaceWire RouterFPGA : GR-RASTA
SPW-0 SPW-1 SPW-2
PC-0OS: Windows
PC-1OS: Windows
PC-2OS: Windows
Gaisler SpaceWire Ethernet BridgeSPW-0 SPW-1 SPW-2
Ethernet
Ethernet
SpaceW
ire
SpaceWire Ethernet Bridge
Gaisler SpaceWire Ethernet BridgeSPW-0 SPW-1 SPW-2
EthernetSPW Physical Port Ethernet/IPv4/TCP - Transmit
Ethernet/IPv4/TCP - Receive
#0 SPW-0 2000 2001
#1 SPW-1 3000 3001
#2 SPW-2 4000 4001
Main Test Topology
Core : D1117 SpaceWire RouterFPGA : GR-RASTA
SPW-0 SPW-1 SPW-2
PC-0OS: Windows
PC-1OS: Windows
PC-2OS: Windows
Gaisler SpaceWire Ethernet BridgeSPW-0 SPW-1 SPW-2
Ethernet
Ethernet
SpaceW
ire
PC-0
Path Address Destination Address
Cargo
TCP Message Header specifying transmission of a SpaceWire packet the size of 6 bytes.
IP Address of GRESB on the IP network.
The TCP Listening Socket on the GRESB.
2000 TCP port corresponds for transmission on SpaceWire port 0.
Send button for dispatching the TCP Message to GRESB
Main Test Topology
Core : D1117 SpaceWire RouterFPGA : GR-RASTA
SPW-0 SPW-1 SPW-2
PC-0OS: Windows
PC-1OS: Windows
PC-2OS: Windows
Gaisler SpaceWire Ethernet BridgeSPW-0 SPW-1 SPW-2
Ethernet
Ethernet
SpaceW
ire
PC-1
Encapsulated SpaceWire PacketTCP Message Header
specifying reception of a SpaceWire packet the size of 5 bytes.
Test Miscellaneous• “2 Routers Topology” was tested in addition to
the “Main Topology” to simulate complex routes in a SpaceWire network with more then one router.
• D1117_SPWRouter delivered successfully thousands of SpaceWire packets originated in PCs, to correct destinations which are PCs as well on the same SpaceWire network.
Further Possibilities
• The router can be redesigned for multiple connections ‘routing matrix’. Currently the datapath of the router can only support one simultaneous connection from port to port.
• The router can be extended to support more SpaceWire routing schemes. (Not just Path Addressing + Header Deletion).
• The router can be redesigned for higher data rate ~200Mhz on the XC2v6000 FPGA using pipeline design.
• Writing a software Device Driver for windows to virtually make GRESB a SpaceWire network connection on a PC. It can be done by implementing a Device Driver which exposes an Ethernet Device abstraction towards Windows and on the other side, coding SpaceWire packets on GRESB. Such a Device Driver actually solves the problem of “Ethernet over SpaceWire” for PC.
End
