High-Speed CMOS Clock and Data Recovery Circuit for ...
Transcript of High-Speed CMOS Clock and Data Recovery Circuit for ...
SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Seong-Jun Song 1
MS Thesis
Design and Implementation ofHigh-Speed CMOS Clock and Data Recovery
Circuit for Optical Interconnection Applications
Seong-Jun Song
Dec. 20, 2002Semiconductor System Laboratory,
Department of Electrical Engineering and Computer Science,Korea Advanced Institute of Science and Technology (KAIST)
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Outline
! Introduction! Motivation! Problem Definition! Proposed 1/8-Rate CDR! Building Blocks! Measurement Results! Conclusion & Further Works
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IntroductionOptical Input Data Noise Corrupted Data Boosted Data
Recovered ClockRetimed DataRecovered Clock
PreAmp
PostAmp
DecisionCircuit
ClockRecovery
Circuit
Freq.Divider
1:4DEMUX
NetworkInterfaceFramer
AGC*
* AGC : Automatic Gain Control
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Motivation
III-V, Si Bipolar, SiGe HBT
☺ Very high-speed☺ Inherently low noise# High cost# High power consumption# Not compatible with
other technologies
☺ Low cost☺ High level of integration☺ Low power consumption# Less speed# High noise
CMOS
Long-Haul Applications(SONET, Gigabit Ethernet)
Short-Haul Applications(Backplane, Chip-to-Chip)
The Solution is Novel CDR Architecture and Circuit Techniques
In CMOS !!!
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Outline
! Introduction! Motivation! Problem Definition! Proposed 1/8-Rate CDR! Building Blocks! Measurement Results! Conclusion & Further Works
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Generic CDR Configuration
PreAmp
PostAmp
DecisionCircuit
ClockRecovery
CircuitFreq.
Divider
1:4DEMUX
NetworkInterfaceFramer
AGC
PhaseDetectorPhase
DetectorLoopFilter
LoopFilter VCOVCOEdge
DetectorEdge
Detector
Clock and Data Recovery (CDR)
PLL-Based Clock Recovery Circuit
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Performance Limitation of 0.25-µµµµm CMOS *Max. Performance ≅≅≅≅ 2GHz (2-Gb/s)
Delay Delay Delay
! Simulation result for 0.25-µµµµm CMOS differential ring oscillators with resistive loads and isolation buffers
Simple VCO3 4 5 6 7
0.8
1.2
1.6
2.0
2.4
M
ax. O
scill
atio
n Fr
eque
ncy
(GH
z)
A Number of Delay Stages* M. Fukaishi, et al., JSSC, Dec. 1998
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Substrate Noise Effect of VCO
Substrate noise voltage
* M. van Heijningen, et al., JSSC, Aug. 2002
VCO
PreAmp
PostAmp
CDR 1:4DEMUX
Si Substrate
Noise-SensitiveAnalog Blocks
VCOSwitching Noise
f ∝∝∝∝ *
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Conventional CDR Techniques (1/2)
! Half-Rate Clock Technique **# Half-rate clock frequency (2GHz)# Close to performance limitation# Difficult to design VCO
0 1 2 3 4Data
CK
0 1 2 3 4Data
CK
! Full-Rate Clock Technique *# Full-rate clock frequency (4GHz)# Impossible to design VCO
** M. Rau, et al., JSSC, July 1997
* M. Soyuer, et al., JSSC, Dec. 1993
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Conventional CDR Techniques (2/2)
! Oversampling Technique *☺ Quarter-rate clock frequency (1GHz)☺ Easier to design VCO# Highly clock phase resolution# Quantization jitter# Extra decision logic
0 1 2 3 4Data
CK0
CK1
CK2
* C.-K. Yang, et al., JSSC, May 1998
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Outline
! Introduction! Motivation! Problem Definition! Proposed 1/8-Rate CDR! Building Blocks! Measurement Results! Conclusion & Further Works
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Proposed CDR Technique! 1/8-Rate Clock Technique *
☺ 1/8-rate clock frequency (0.5GHz)☺ Very easy to design VCO☺ No quantization jitter☺ No extra decision logic☺ Can do 1:4 DEMUX# Complex design
0 1 2 3 4 5 6 7 8 9Data
CK0
CK1
CK2
CK3
* S.-J. Song, et al., ESSCIRC, Sept. 2002* S.-J. Song, et al., to be published for JSSC, July 2003
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Proposed 1/8-Rate CDR Architecture
! Proposed 1/8-rate CDR circuit can achieve higher speed operation, lower power consumption, and smaller area.
DecisionCircuit
ClockRecovery
Circuit
Freq.Divider
1:4DEMUX
Merging
1/8-RateCDR
Circuit
Conventional Full-Rate CDR
Multiple Funtional Blocks
Proposed 1/8-Rate CDR
A Single Functional Block
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Proposed 1/8-Rate CDR Circuit
1/8-Rate Phase DetectorPerforming 1:4 DEMUX
VCO(0.5GHz) LPF
ChargePump
DT
CT
NRZ Data(4-Gb/s)
CK
0
CK
1
CK
2
CK
3
6-BitCoarseControlWord
6
D0
D1
D2
D3
Four Half-Quadrature 1/8-Rate Clocks (0.5GHz)
1:4Demultiplexed
Data(1-Gb/s)
Din
CK0 CK1 CK2 CK3
Clock Output Buffers
CC[5:0]
Dat
a O
utpu
t Buf
fers
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Outline
! Introduction! Motivation! Problem Definition! Proposed 1/8-Rate CDR! Building Blocks! Measurement Results! Conclusion & Further Works
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Choice of VCO Configuration
☺ Wide tuning range☺ Different phase clock generation# Low center frequency# Low Q factor# High phase noise & jitter
Delay Delay Delay
Ring Oscillator LC Oscillator
☺ High center frequency☺ High Q factor☺ Low phase noise & jitter# Narrow tuning range# Large area
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Choice of Inductor Load
VC
Spiral Inductor Load Active Inductor Load
☺ Moderately high Q factor (>>10)☺ Small area☺ Easy to design# Noise caused by resistor and MOS
# Low Q factor (3~5)# Large area# Dependent on process# Difficult to design
C
osc
V
LC1
1
∝∝∝∝
∝∝∝∝
ωωωω
mgL 1∝∝∝∝
CVC ∝∝∝∝
D
m
osc
I
gLC
∝∝∝∝
∝∝∝∝
∝∝∝∝
1ωωωω
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Voltage-Controlled Oscillator
* DCC : Duty Cycle Correction
! Four half-quadrature phase clocks! Delay stage with active inductor load ! DCC for using both rising and falling edges of clock
Delay Delay Delay Delay
CK0 CK0 CK1 CK1 CK2 CK2 CK3 CK3
FeedbackIsolation Buffers
with DCC
Coarse ControlFine Control
6
*
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Feedback Isolation Buffer
Vin Vout
(a) Block Diagram (b) Transistor-Level Implementation
High CMRR Feedback
Resistive Feedback
Vin Vout
Duty-Cycle Correction
Bandwidth Extension
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Single Delay Stage of the VCOActive
InductorLoad
6-bit DigitalCoarse Tuning
Folded DifferentialFine Tuning
M1 M2 M3 M4
M9
32I 16I 8I 4I 2I I
Vfine_ctrl
M8M7M6M5
Vout
Vin
M10 M11 M12
R1 R2
R3 R4
6-BitCoarseControlWord
6
NKVKFRosc VCO_Coarsefine_ctrlVCO_Fine ++++++++====∴∴∴∴ ωωωωωωωω 630,...,for ====N
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1/8-Rate Linear Phase Detector
D Q
Din
D Q
CK0
D Q
D Q
CK1
D Q
D Q
CK2
D Q
D Q
CK3
Dat
a &
Clo
ck T
rans
ition
(DC
T)D
etec
tor
Dat
a &
Clo
ck T
rans
ition
(DC
T)G
ener
ator DT
CT
DCT0
DCT1
DCT2
DCT3
Four Demultiplexed Data (D0~D3)
ToCharge Pump
! Three tasks! Data Transition Detection! Linear phase error detection! Data regeneration
! Data demultiplexing
! No systematic offset
! Employing proposed folded current-mode logic family(D-latch, MUX, and XOR)
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1/8-Rate Linear PD Characteristic
CK
Data
250ps
Data-CK delay
Data to CK delay (ps)
V CT
- VD
T (m
V)
0 50 100 150 200 250 300 350 400 450 500-80
-60
-40
-20
0
20
40
60
80
100
LockingPoint
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Current-Mode Logic (CML)
CK
D
Q
D
Q
CK
☺ High speed operation☺ Low power consumption# High supply voltage# Need for level shifter
☺ Higher speed operation☺ Low supply voltage☺ No need for level shifter☺ Wide input/output range# High power consumption# Large area
Conventional CML D-Latch Proposed Folded CML D-Latch
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Proposed Folded CML Family *
D1
Q
CK
D0 B
Q
A
B
Folded MUX * Folded XOR *
01 DCKDCKQ ⋅⋅⋅⋅++++⋅⋅⋅⋅==== BABABAQ ⊕⊕⊕⊕====⋅⋅⋅⋅++++⋅⋅⋅⋅====
* S.-J. Song, et al., to be published for JSSC, July 2003
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Fully Differential Charge Pump
t
DT
CT
Vctrl
* CMFB : Common-Mode Feedback
DT
CMFB
Vctrl
CT
LPF
*
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Outline
! Introduction! Motivation! Problem Definition! Proposed 1/8-Rate CDR! Building Blocks! Measurement Results! Conclusion & Further Works
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Chip Microphotograph
! 0.25-µµµµm Standard CMOS! 0.9 x 1.0 mm2VCO
1/8-RatePhase Detector
Performing 1:4 DEMUX
LPF
CP
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Test Fixture
4-Gb/s Data In
Four 1-Gb/s Recovered Data Out
Four 0.5GHz Recovered Clock Out
FR-4 PCB
Gold Wire Bonding
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Measured Recovered Clock
100 ps/div
! For 231-1 PRBS input data at 4-Gb/s,
10 d
B/d
iv
1 MHz/div
-112dBc/Hz @ 1MHz offset
47ps pk-pk5.2ps RMS
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Measured Eye Diagrams
1/8-RateCDR
CircuitDin
CK0 CK1 CK2 CK3
D0D1D2D3
231-1 PRBS Data Input (4-Gb/s)
Four Recovered Clock Output (0.5GHz)
Four Recovered Data Output (1-Gb/s)
V: 200 mV/div, H: 200 ps/div
V: 200 mV/div, H: 500 ps/div
V: 200 mV/div, H: 200 ps/div
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Recovered Clock and Data
500 ps/div
200
mV/
div
1-Gb/sDemultiplexed
Recovered Data (D0)
0.5GHzRecovered Clock (CK0)
! For 231-1 PRBS input data at 4-Gb/s,
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Measured VCO CharacteristicDifferential Fine Tuning 6-Bit Digital Coarse Tuning
! KVCO_Fine = 75 MHz/V! Fine Tuning Range = 70 MHz (14%)
! KVCO_Coarse = 2.5 MHz/Word Step! Coarse Tuning Range = 150 MHz (30%)
Mea
sure
d VC
O F
requ
ency
(MH
z)
0 10 20 30 40 50 60 70
380
400
420
440
460
480
500
520
540
6-Bit Coarse Control Word (N)M
easu
red
VCO
Fre
quen
cy (M
Hz)
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8
450
460
470
480
490
500
510
520
530
Differential Fine Control Voltage (V)
Dosc I∝∝∝∝ωωωωDosc I∝∝∝∝ωωωω
NKVKFRosc VCO_Coarsefine_ctrlVCO_Fine ++++++++====∴∴∴∴ ωωωωωωωω 630,...,for ====N
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Performance Summary
16 MHzCapture RangeFour 1-Gb/sRecovered Data
0.5 GHzRecovered Clock
< 10-6BER for 231-1 PRBS
0.25-µµµµm standard CMOSTechnology0.9 x 1.0 mm2Active Area
2.5 VSupply Voltage
70 mWPower Dissipation(excluding output buffers)
5.2 ps RMSClock Jitter for 231-1 PRBS-112 dBc/HzPhase Noise at 1-MHz offset
75 MHz/VVCO Fine Tuning Gain
4-Gb/sNRZ Data Rate
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Proposed Performance Index
(Gb/s) Rate Data V2.5
VoltageSupplynConsumptio Power
mW 70m0.25
Technology ××××
⋅⋅⋅⋅
⋅⋅⋅⋅
µµµµ
Normalized Data Rate =
! From O. T.-C. Chen, et al., JSSC, Jan. 2002,
! Frequency index in PLL is derived by
(MHz) VoltageSupply V1.8
m0.35Technology FF ××××
⋅⋅⋅⋅
====∗∗∗∗
µµµµ
! By taking account into power consumption in CDR circuit,
! Proposed performance index in CDR circuit can be expressed as
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Performance Comparison
(Gb/s) Rate Data V2.5
VoltageSupplynConsumptio Power
mW 70m0.25
Technology ××××
⋅⋅⋅⋅
⋅⋅⋅⋅
µµµµ
Normalized Data Rate =
0.250.250.250.25----µµµµm CMOSm CMOSm CMOSm CMOS2.5 V2.5 V2.5 V2.5 V70 70 70 70 mWmWmWmW4444----Gb/sGb/sGb/sGb/s4444----Gb/sGb/sGb/sGb/s1/81/81/81/8----Rate ClockRate ClockRate ClockRate ClockThis WorkThis WorkThis WorkThis Work
0.24-µµµµm CMOS1.93 V84 mW4-Gb/s2.47-Gb/s2x-Oversampling[8]
0.25-µµµµm CMOS2.5 V153 mW5-Gb/s2.29-Gb/s3x-Oversampling[7]
0.5-µµµµm CMOS3.3 V973.5 mW4-Gb/s0.76-Gb/s3x-Oversampling[6]
0.18-µµµµm CMOS1.8 V83 mW6-Gb/s2.62-Gb/sHalf-Rate Clock[5]
0.5-µµµµm CMOS3.3 V85 mW1-Gb/s2.17-Gb/sHalf-Rate Clock[4]
0.18-µµµµm CMOS1.8 V285 mW10-Gb/s1.27-Gb/sHalf-Rate Clock[3]
0.35-µµµµm CMOS3.3 V150 mW1.25-Gb/s1.08-Gb/sHalf-Rate Clock[2]
0.6-µµµµm CMOS5 V300 mW1-Gb/s1.12-Gb/sFull-Rate Clock[1]
TechnologySupply Voltage
Power ConsumptionData RateNormalized
Data RateCDR TechniqueReference
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Normalized Performance Comparison
[1] H. Wang, et al., ISSCC, 1999[2] K. Iravani, et al., CICC, 1998[3] J. E. Rogers, et al., ISSCC, 2002[4] M. Rau, et al., JSSC, July 1997[5] K. Nakamura, et al., SOVC, 1998[6] C.-K. Yang, et al., JSSC, May 1998[7] S.-H. Lee, et al., JSSC, Dec. 2002[8] M.-K.E. Lee, et al., SOVC, 20020 1 2 3 4 5 6 7 8 9 10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Nor
mal
ized
Dat
a R
ate
(Gb/
s)
CMOS CDR Circuits
Full-Rate Clock Half-Rate Clock Oversampling 1/8-Rate Clock
[1] [2] [3] [4] [5] [6] [7] [8] ThisWork
50% Increase
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Outline
! Introduction! Motivation! Problem Definition! Proposed 1/8-Rate CDR! Building Blocks! Measurement Results! Conclusion & Further Works
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Conclusion
! A high-speed and low-power CDR circuit has been introduced :
!!!! Exploiting 1/8-rate clock technique
!!!! Using a 0.25-µµµµm standard CMOS technology
!!!! Single functional block merging clock recovery circuit,decision circuit, divider, and 1:4 DEMUX
! The proposed CDR demonstrates 4-Gb/s and 70mW operationsuitable for low cost optical interconnection applications.
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Further Works
! Fully Integrated Frequency-Locked Loop! Broadband frequency detection
! Improvement of BER! To improve SNR ! To improve Clock Jitter Characteristic
! Need for Detailed Mathematical Analysis
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Supplemental Materials
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Operation of 1/8-Rate PD (1/4)0 1 2 3 4 5 6 7 8 9 10 11 12Din
CK0
CK1
CK2
CK3
0 + 1
1 + 2
2 + 3
3 + 4
4 + 5
5 + 6
6 + 7
7 + 8
8 + 9
9 + 10
10 + 11
11+12
DT
CT
DCT0
DCT1
DCT2
DCT3
0 4 8 12
1 5 9
2 6 10
3 7 11
D0
D1
D2
D3
D Q
Din
D Q
CK0
D Q
D Q
CK1
D Q
D Q
CK2
D Q
D Q
CK3
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Operation of 1/8-Rate PD (2/4)0 1 2 3 4 5 6 7 8 9 10 11 12Din
CK0
CK1
CK2
CK3
0 + 1
1 + 2
2 + 3
3 + 4
4 + 5
5 + 6
6 + 7
7 + 8
8 + 9
9 + 10
10 + 11
11+12
DT
CT
DCT0
DCT1
DCT2
DCT3
0 4 8 12
1 5 9
2 6 10
3 7 11
D0
D1
D2
D3
D Q
Din
D Q
CK0
D Q
D Q
CK1
D Q
D Q
CK2
D Q
D Q
CK3
Dat
a &
Clo
ck T
rans
ition
(DC
T)D
etec
tor
DCT0
DCT1
DCT2
DCT3
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Operation of 1/8-Rate PD (3/4)0 1 2 3 4 5 6 7 8 9 10 11 12Din
CK0
CK1
CK2
CK3
0 + 1
1 + 2
2 + 3
3 + 4
4 + 5
5 + 6
6 + 7
7 + 8
8 + 9
9 + 10
10 + 11
11+12
DT
CT
DCT0
DCT1
DCT2
DCT3
0 4 8 12
1 5 9
2 6 10
3 7 11
D0
D1
D2
D3
D Q
Din
D Q
CK0
D Q
D Q
CK1
D Q
D Q
CK2
D Q
D Q
CK3
Dat
a &
Clo
ck T
rans
ition
(DC
T)D
etec
tor
DCT0
DCT1
DCT2
DCT3
Four Demultiplexed Data (D0~D3)
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Operation of 1/8-Rate PD (4/4)0 1 2 3 4 5 6 7 8 9 10 11 12Din
CK0
CK1
CK2
CK3
0 + 1
1 + 2
2 + 3
3 + 4
4 + 5
5 + 6
6 + 7
7 + 8
8 + 9
9 + 10
10 + 11
11+12
DT
CT
DCT0
DCT1
DCT2
DCT3
0 4 8 12
1 5 9
2 6 10
3 7 11
D0
D1
D2
D3
D Q
Din
D Q
CK0
D Q
D Q
CK1
D Q
D Q
CK2
D Q
D Q
CK3
Dat
a &
Clo
ck T
rans
ition
(DC
T)D
etec
tor
Dat
a &
Clo
ck T
rans
ition
(DC
T)G
ener
ator DT
CT
DCT0
DCT1
DCT2
DCT3
Four Demultiplexed Data (D0~D3)
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Example
CK0
CK1
CK2
CK3
DCT0
DCT1
DCT2
DCT3
Din
0 1 1 0 0 1 0 0 1 1 1
DT
CT