High-Performance Analog-to-Digital Converters: Evolution ... · High-Performance Analog-to-Digital...
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High-Performance Analog-to-Digital Converters: Evolution and Trends
Pedro Figueiredo
Topical Workshop on Electronics for Particle Physics 2015
28th September 2015
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ADC performance: Evolution
ADC architectures: Relationships, Speed, Performance
Technology Scaling: Difficulties and Opportunities
Synopsys digitally calibrated Pipeline and SAR ADCs
Outline
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Translates an analog input signal into its binary coded representation (N bit), at a certain rate (fs)
The Analog-to-Digital Converter
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Sampling
vI
t
Quantization
vIQ
t
Clock Signal (fs)
Quantization Step (VLSB)
Encoding
011011101010010101111000010000000000
vIS
t
TS = 1/fs
vI Energy Efficiency
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Data from Prof. Murmann’s Survey [1]
Evolution of ADC performance
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
20 30 40 50 60 70 80 90 100 110 120
P/fs
[p
J]
SNDR [dB]
Conversion Energy vs SNDR
VLSI 1997-2004
ISSCC 1997-2004
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
20 30 40 50 60 70 80 90 100 110 120
P/fs
[p
J]
SNDR [dB]
Conversion Energy vs SNDR
VLSI 1997-2004
ISSCC 1997-2004
ISSCC 2005-2014
VLSI 2005-2013
~80x Energy Efficiency improves 2x [2]:- Low/Medium Resolution: every ~1.6 yrs- High Resolution: every ~5.4 yrs
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1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
20 30 40 50 60 70 80 90 100 110 120
P/fs
[p
J]
SNDR [dB]
Conversion Energy vs SNDR
VLSI 1997-2004
ISSCC 1997-2004
ISSCC 2005-2014
VLSI 2005-2013
FOMw=1 fJ/conv-step
FOMw=10 fJ/conv-step
Walden’s FOM=P/(2ENOB.fs)
Evolution of ADC performance
Assumptions: 1 extra bit P increases 2Power scales linearly with fs
Range of applicability
Best FOM: 10/12b 40kS/s-4MS/s low VDD
6-8b >1 GSPS ADCsLower power efficiency
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Power per conversion-step as a function of fs
Evolution of ADC performance
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11
P/2
^EN
OB
[W
/co
nve
rsio
n-s
tep
]
fs [Hz]
Power/Conversion-step vs fs
VLSI 1997-2004
ISSCC 1997-2004
FOMw=1 fJ/conv-step
FOMw=10 fJ/conv-step
FOMw=100 fJ/conv-step
FOMw=1 pJ/conv-step
7 pJ/conv.step
0.5 pJ/conv.step
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11
P/2
^EN
OB
[W
/co
nve
rsio
n-s
tep
]
fs [Hz]
Power/Conversion-step vs fs
VLSI 1997-2004
ISSCC 1997-2004
ISSCC 2005-2014
VLSI 2005-2013
FOMw=1 fJ/conv-step
FOMw=10 fJ/conv-step
FOMw=100 fJ/conv-step
FOMw=1 pJ/conv-step
100 fJ/conv.step
10 fJ/conv.step
1 fJ/conv.step
But still a significant number ofpublications in this
frequency range
Many more high frequency ADCs(though max reported fs increased only ~2x)
Record FOM values- Wireless Sensor Networks
- Internet of Things6
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Some of Synopsys ADC implementations
Evolution of ADC performance
0.01
0.1
1
25 30 35 40 45 50 55 60 65 70
Technology [nm]
FOM
/FO
MR
ef
AD
C
2.5x
1.7x
5x
Ref. ADC: 10 bit 80 MS/s Pipeline ADC
12 bit 200 MS/s Pipeline ADC with digital calibration
12 bit 80 MS/s SAR ADC with digital calibration
Estimate
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ADC architectures typically presented as different and (somewhat) unrelated alternative solutions…
• … each with its own pros and cons …
• … each best suited to certain resolution and fs
Here we will focus on fundamental operations and how they are related [3]
ADC architectures
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ADC fundamental operations: sampling and quantization
Single bit ADC:
Multi-bit ADC:
Single and Multi-bit ADCs
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Conversion Process:Search the DAC output that
best approaches the sampled input...
... i.e. minimize the residue ...
... and then use bout=ddac
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SAR ADC is the direct implementation of the elementary multi-bit architecture
Very efficient:• Re-uses same hardware in each cycle
• Necessary number of cycles grows linearly with resolution: N cycles for N bits
• Performance limited by DAC nonlinearity
SAR ADC
S/HvI
q
DACddac
bout
+-
VREF
Successive
Approximation
Register
Output
Registers
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If DAC provides several outputs simultaneously: possible to search several codes in parallel
Different codes are searched by different paths Faster: N/NC cycles to complete a conversion Number of parallel paths: 2Nc
Differences between them degrade performance Examples: 2 and 3 bit per cycle SAR ADCs [4,5]
Speed Increase: Parallelization in the code-search process
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S/HvI q
DACddac
bout
+-
VREF
Multi-bit quantizer
residue
NC bit quantizer
S/HvI
DAC
+ -
++ E
nc
od
ing
an
d C
on
tro
l
1
2Nc
-1
2Nc
bout
-
-
VREF
Multi-step Cyclic Subranging ADC
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Taking this parallelization to the limit: NC=N
All codes are searched simultaneously
Flash ADC
Speed Increase: Parallelization in the code-search process
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Another possibility is pipelining:
• Quantization process is divided in several steps that occur in a pipelined fashion:
o Typically, quantizers have low resolution low parallelization in the code search process
• At a given clock cycle, the ADC is quantizing several different samples
Speed Increase: Pipelining
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Pipelined ADCs: Practical considerations lead to the structure shown below.
Each stage constituted by:
• Quantizer
• Residue calculator/amplifier block – MDAC
oResidue: error signal corresponding to what is left to quantize
Speed Increase: Pipelining
MDAC
S/HvI
Quantizer 1
N1 bits
N1 Quantizer k
Nk bits
bout
Stage 1 Stage k
+-
Residue 1
VREF
S/H
Quantizer 2
N2 bits
N2
Stage 2
+-
Residue 2Residue
k-1
2N1-1 2
N2-1
S/H
MDAC
S/H S/H
DAC
N1 bits
DAC
N2 bits
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Quantizer specifications are relaxed (low resolution)
MDAC non-idealities limit performance
• Gain error of S/H, DAC and residue amplifier limit overall linearity
• In practice this translates into stringent gainspecifications of the amplifier implementing the MDAC
Speed Increase: Pipelining
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Non-linearity of the DAC(s) limits performance Additionally:
• Use of Pipelining Residue Amplification Relaxed Quantizers
Performance limited by amplification blocks
• Use of Parallelization in the code search process Quantizer only ADCs Many parallel paths
Performance limited by differences between
parallel paths (offsets)
SAR ADCs use none of the above: limited only by DAC non-linearity
Speed Increase Technique Limitations
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Another parallelization possibility is time-interleaving
Different samples processed by independent paths• Differences of offset, gain, sampling instants degrade
performance
Unit ADCs use the parallelization/pipelining techniques previously discussed
Nch ADCs fs increases Nch times
Parallelization: in time domain
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Example: 6b 90GS/s ADC with64 unit SAR ADCs [6]
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Technology Scaling – the bad• Reduction of gm/gds
• Headroom limitations caused by VDD reduction• Bad CMOS switches• Higher variability• Transistor properties and matching more and more
dependent on surroundings• Higher interconnect delays
… and the good• Faster devices• Digital processing is increasingly powerful, cheap and low
power - available to overcome limitations in the analog sub-blocks of ADCs
ADC implementations in advanced technologies
Digitally Assisted Analog
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Typical 1.5b MDAC circuit• f1: Sampling f2: Residue Amplification
Negative feedback around a high-gain amplifier sets residue amplification gain very accurately
Increasingly difficult to attain high gain in nanoscale technologies
Class A amplifiers not power efficient
ADCs with residue calculation/amplification
CF=C
vI
-
+b×VREF
CR=C
f1
f1
f2
f2
f1'
f1: sampling phase
f2: amplification phase
vO
f1
A0
b={-1,0,+1} depending
of quantizer decision
CLp
f2
f2
Next stage
inext stage
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Techniques to improve power efficiency:
• Opamp switching reduces power consumption during reset phase, but introduces speed or headroom limitations [7-9]
• Opamps can be shared between stages in order to ensure they are being used at all times [10-13]
• Class AB amplifiers [14] may be used, but are more complex and have limited effectiveness
ADCs with residue calculation/amplification
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Techniques to improve power efficiency:
• Use of low gain amplifiers and digital calibration
• Opamp substituted by comparator + current source[15,16].
oNo stability and gain-bandwidth product limitations
o Stops consuming when the desired voltage is reached
ADCs with residue calculation/amplification
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Techniques to improve power efficiency:
• Open loop amplifiers based on transconductances[17,18]:
oGain is parasitic and PVT dependent, and non-linearity is non-negligible. Complex digital calibration required
• Open loop amplifiers that are not based on transconductances:
– Parametric amplification [19,20]
– Bucket brigade circuits [21,22]
o Even larger non-linearity and dependence of parasitics/PVT
oDigital calibration complexity is further increased
ADCs with residue calculation/amplification
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Calibration of amplifier finite gain and capacitor mismatches
• Fast startup time and robustness against VDD/Temp variations
Stages with reduced output swing
Opamp switching technique with no speed or signal swing limitations
.
12b 200MS/s digitally calibrated pipeline ADC
1.5 bitCalibrated
Stage 1
1.5 bitCalibrated
Stage 2
1.5 bitCalibrated Stage 10
1.5 bitUncalibrated
Stage 1
1.5 bitUncalibrated
Stage 2
1.5 bitUncalibrated
Stage 3
Digital Calibration and Error Correction
2
b[2]
ts[2]
2
b[1]
ts[1]
2
b[10]
ts[10]
2
b[11]
2
b[12]
2
b[13]
3
bout
vI
12
3 bit Flashb[14]
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Gain error of S/H, and residue amplifier, and mismatches of the DAC cause GEi and GEo1
Digital gain calibration: Multiply by 1/GEo
.
12b 200MS/s digitally calibrated pipeline ADC
Ideal
MDAC
DAC
N1 bits
2N1-1+
-vI
Quantizer 1
N1 bits
N1
Stage 1
VREF
Nbck bit
Backend
ADC
bout,lsb+
Nbck
bout
N
bout,msb
vO1
2Nbck-1
S/H
S/H GEoGEi
1/GEo~
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Determination of digital coefficients
12b 200MS/s digitally calibrated pipeline ADC
Foreground(Fast Startup)
Background(Adapt coef. as
VDD/Temp varies)
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U.S. Patent8 742 961
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Capacitor CD:
• Injects the Pseudo-Random Binary Sequence on the central segment
• Shifts L/R segments in order to reduce signal swing
o Lower amplifier non-linearity
oRelaxed settling specifications
12b 200MS/s digitally calibrated pipeline ADC
26U.S. Patent8 797 196
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Amplifier:
• Single stage, high-swing A016dB only
• Switching of CB reduces power consumption in f1
oNo speed or signal swing limitations
12b 200MS/s digitally calibrated pipeline ADC
IBIAS
vdiode vB
vBCMvBCM
fB
fA
S1
CB
vOPvON
vOP
vON
VCM
Common-Mode
Feeback Network
vIN vIP
fA
fB
f2
Amplification
Phase
vB
vdiode
VDD
VDD
0
U.S. Patent8 610 422
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Measurement results:
Calibration off Calibration on
12b 200MS/s digitally calibrated pipeline ADC
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No need for highly linear or gain accurate blocks better adapted to nanometer technologies
Non-linearity of the DACs inside the quantizers:
• Caused by random deviations on its constitutive elements
• Matching improved by using devices with larger area
oResistive ladder DACs: increased parasitics
o Switched capacitor DACs: sets a minimum limit for the value of the capacitors (as does noise)
• May also be addressed by digital calibration
Quantizer-only ADCs
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Performance of flash/subranging/time-interleaved SAR ADCs limited by comparator offsets
Add pre-amplifier with offset sampling
• Static consumption
• Non-negligible residual offset [23]
Quantizer-only ADCs
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Offset calibration:• Programmable capacitor or current source arrays in
dynamic comparator [24,25]
• Auxiliary diff pair and switched capacitor integrator [23,26]o No speed reduction
o Marginal power increase
o High calibration-range/calibration-step
ratio
o (Almost) perfect offset removal
Quantizer-only ADCs
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Averaging [23,27,28]
• Offset of comparators is a weighted sum of several amplifiers
• Offsets become correlated
• Lower area devices may be used
Quantizer-only ADCs
R0 R0 R0 R0 R0 R0R1
R1
R1
R1
R1
R1
VDD
ISS ISS ISS
-VREF 0 VREFvIvI vI
R0 R0R1
R1
ISS
vI
R0 R0R1
R1
ISS
vI-kVREF kVREF
0-1-k 1 k
AveragingNetwork
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Stochastic flash ADCs [29,30]:
• Fully synthesized in a digital flow
• >>2N minimum size comparators with the same VREF
• Output code obtained by counting the number of ‘1’
• Nonlinear transfer function: Gaussian cumulative distribution Linearization through digital calibration
Quantizer-only ADCs
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Asynchronous architecture.
Operation independent of clk duty cycle
Low noise fully dynamic comparator
Use of time-interleaving: 12b 160MS/s and 320MS/s ADCs
12b 80MS/s digitally calibrated SAR ADC
Sw-CapacitorS/H+ Subtractor+
DACvI
bout
clk
Data Register
Raw digital code
Timing and State Machine
Digital Calibration
residue
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DAC with capacitive dividers avoids the exponential increase on the number of (small) unit capacitors
Digital calibration: addresses random capacitor mismatches and sensitivity to parasitics in the capacitive divider nodes.• Measures capacitor ratios at startup
• Corrects the raw code provided by the SAR
12b 80MS/s digitally calibrated SAR ADC
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Measurement results:
Calibration bypassed Calibration on
12b 80MS/s digitally calibrated SAR ADC
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Reviewed ADC performance evolution in the last 10 years
Main trend: energy efficiency improvement
Conclusions
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ADC architectures
• SAR ADC is the direct implementation of the elementary multi-bit ADC architecture
• Speed increase: use parallelization in the code-search process or pipelining
• This yields ADCs based only on quantizers, and those based on residue amplification for further quantization
o…which have significantly different trade-offs
• Speed also increases by parallelizing in time-domain: time-interleaving
Conclusions
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Conclusions
Reviewed challenges/benefits introduced by technology scaling
Digitally Assisted Analog trend: • Relaxed analog circuits’ complexity…
• …traded favorably by extra digital complexity
Disclosed a few details about Synopsys 12b digitally calibrated pipeline and SAR ADCs• Illustrated how the use of digital calibration can
dramaticaly improve performance
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