High Level Languages: A Comparison By Joel Best. 2 Sources The Challenges of Synthesizing Hardware...
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Transcript of High Level Languages: A Comparison By Joel Best. 2 Sources The Challenges of Synthesizing Hardware...
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Sources
The Challenges of Synthesizing Hardware from C-Like Languages by Stephen A. Edwards
High-Level Synthesis Fundamentals from "Low-Power High-Level Synthesis for
Nanoscale CMOS Circuits" by Saraju P. Mohanty
Synthesis from C in Electronic System Level (ESL) Design By Christopher Sullivan
4
Electronic System Level Design
Description of the system with a higher level of abstraction
Necessary for complex SoCs Decreased development time Simulation is much easier
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The High-level Synthesis Process (cont’d) Compilation
Behavior converted to internal representations Data flow graph (DFG) Control flow graph (CFG)
TransformationDFGs and CFGs optimized and transformed Hardware optimizations such as associative
and commutative operations
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The High-level Synthesis Process (cont’d) Scheduling and Resource Allocation
Temporal partitioning of DFG and CFG to allow for concurrency
Trade-offs such as area and timing accounted for
Control steps needed and variable lifetimes determined
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The High-level Synthesis Process (cont’d) Binding
Functional unit binding Map an operation to a functional unit
Memory unit binding Maps variables or constants to registers, RAM, or
ROM
Output Generation
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Using C for Hardware
Familiar to many programmers Easier hardware/software co-design C-reference designs available for many
applications Developed for von Neumann architecture
Control unit, memory, ALU Fundamentally sequential
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C for Modeling
Simulation is much faster at behavioral level than at the register-transfer level
Transaction-level ModelingSeparates functional units from
communicationMost parts not synthesizable
SystemC most commonly used
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Communication
ChannelsChannel data type for communication between
parallel processesReceiver and transmitter must be ready at the
same time (synchronization)
Examples: Handel-C, HardwareC, Bach C
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Communication (cont’d)
Multiple PrimitivesChannel can be a signal, buffer, FIFO,
semaphore, mutex, etc Interfaces and ports for communication
between functional unitsEvents used for synchronization
Examples: SpecC, SystemC
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Communication in SpecC
interface I1{ bit[63:0] Read(void); void Write(bit[63:0]);};
channel C1 implements I1;
behavior B1(in int, I1, out int);
behavior B(in int p1, out int p2){ int v1; C1 c1; B1 b1(p1, c1, v1), b2(v1, c1, p2);
void main(void) { par { b1.main(); b2.main(); } }};
b1 b2
v1
c1B
p1 p2
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Concurrency
Explicit Parallelism Which code is parallel and which is sequential
specified by the programmer e.g. Handel-C
Implicit Parallelism (SystemC) Similar to HDLs System describes processes which run in parallel
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Concurrency (cont’d)
Compiler-identified Parallelisme.g. TransmogrifierC, CatapultCGood concurrent programming required
Much different than software concurrency model
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SpecC Example (Explicit)
behavior B_pipe{ B b1, b2, b3;
void main(void) {pipe{b1.main(); b2.main(); b3.main(); } }};
B_par
b1
b3
b2
B_seq
b1
b3
b2
B_fsm
b1
b3
b2
b5 b6
b4
B_pipe
b1
b3
b2
behavior B_seq{ B b1, b2, b3;
void main(void) { b1.main(); b2.main(); b3.main(); }};
behavior B_fsm{ B b1, b2, b3, b4, b5, b6; void main(void) { fsm { b1:{…} b2:{…} …} }};
behavior B_par{ B b1, b2, b3;
void main(void) { par{b1.main(); b2.main(); b3.main(); } }};
Sequentialexecution
FSMexecution
Concurrentexecution
Pipelinedexecution
Source: SpecC Lanugage Tutorial
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Timing Implicit rules for inserting clocks Handel-C
Each assignment or delay is 1 clock cycle Channel communication is 1 clock cycle
Transmogrifier C Each loop iteration and function call takes a cycle
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Timing (cont’d)
Explicit clock definition (SystemC, Ocapi)For sequential logic, wait statements are usedCombinational logic is implicit
Clock constraint definition (HardwareC)Clock constraints for a particular section of
code are specified
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Data Types
No ANSI-C types smaller than a byteActually…
Compiler-driven data typesCompiler chooses type size based on its useTransmogrifierC allows for preprocessor
pragmas to specify integer widthC2Verilog uses a GUI to set variable width
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Data Types (cont’d)
Adding hardware types to CAllow specification of integer widthAdd boolean typeE.g. Handel-C, Bach C, SpecC
Using C++ typesC++ type system allows for bit-level typingSystemC provides classes for variable-width
integers and fractional numbers
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Hardware Control
All languages differ in amount of control given over the hardware
Handel-CTarget FPGA specified for compilationMemory types such as RAM can be explicitly
specifiedMacros provided for common operations
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Hardware Control (cont’d)
SpecC:GUI used to specify how to translate certain
constructs to hardware HardwareC
Uses #pragmas within the code to specify timing or resource constraints
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Pointers Supported by Ocapi and SystemC and as
long as the target is SynthesizableCompile-time determinable
Not supported by Handel-C, TransmogrifierC, HardwareC, and most others
Active area of research
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Conclusions
Higher abstraction than RTL needed for complex system-on-chip systems
C provides a proven foundation for behavioral description
Most challenges can be overcome with a variety of methods