High Input Voltage, Low Quiescent Current, Low … EMP8042 Elite Semiconductor Memory Technology...
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ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 1/16
High Input Voltage, Low Quiescent Current, Low-Dropout Linear Regulator
General Description The EMP8042 is a high voltage, low quiescent current,
low dropout regulator with 150mA output driving
capacity. The EMP8042, which operates over an
input range up to 20V, is stable with any capacitors,
whose capacitance is larger than 1μF, and suitable
for powering battery-management ICs because of
the virtue of its low quiescent current consumption
and low dropout voltage. Below the maximum
power dissipation (please refer to Note. 5), It
guarantees delivery of 100mA output current, and
supports preset output voltages ranging from 1.3V to
6.0V with 0.1V increment.
EMP8042 also includes bandgap voltage reference,
constant current limiting and thermal overload
protection. It’s available in both of SOT-23-5,SOT-89-3
and SOT-23-3 miniature packages.
Applications g Logic Supply for High Voltage Batteries
g Keep-Alive Supply
g 3-4 Cell Li-ion Batteries Powered systems
Features g 150mA output current driving capacity
g 780mV typical dropout at Io=150mA
g 13µA typical quiescent current
g 1µA typical shutdown mode
g Up to 20V input range
g Stable with small ceramic output capacitors
(1µF)
g Over temperature and over current
protection
Ordering Information Part Number Remark
EMP8042 ±2.5% output voltage tolerance
EMP8042B ±1.0% output voltage tolerance
Typical Application
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 2/16
Connection Diagrams
SOT-23-3
3
1 2
VIN
GND VOUT
Order information EMP8042-XXVF05NRR/ EMP8042B-XXVF05NRR XX Output voltage VF05 SOT-23-5 Package NRR RoHS & Halogen free package
Rating: -40 to 85°C Package in Tape & Reel
EMP8042-XXVG03NRR/ EMP8042B-XXVG03NRR XX Output voltage VG03 SOT-89-3 Package NRR RoHS & Halogen free package
Rating: -40 to 85°C Package in Tape & Reel
EMP8042B-XXVN03NRR XX Output voltage VN03 SOT-23-3 Package NRR RoHS & Halogen free package
Rating: -40 to 85°C Package in Tape & Reel
Order, Marking and Packing Information Package Vout Product ID. Marking Packing
SOT-23-5
3.3V EMP8042-33VF05NRR
Tape & Reel
3Kpcs 5.0V EMP8042-50VF05NRR
ADJ EMP8042-00VF05NRR
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 3/16
SOT-89-3
3.3V EMP8042-33VG03NRR
Tape & Reel
1Kpcs 5.0V EMP8042-50VG03NRR
SOT-23-5
3.0V EMP8042B-30VF05NRR
8042BTracking Code
5 4
1 32PIN1 DOT
Tape & Reel
3Kpcs
3.3V EMP8042B-33VF05NRR
5.0V EMP8042B-50VF05NRR
ADJ EMP8042B-00VF05NRR
SOT-89-3
3.0V EMP8042B-30VG03NRR
8042BTracking Code
1 32PIN1 DOT
Tape & Reel
1Kpcs 3.3V EMP8042B-33VG03NRR
5.0V EMP8042B-50VG03NRR
SOT-23-3
3.0V EMP8042B-30VN03NRR
8042BTracking Code
3
1 2PIN1 DOT
Tape & Reel
3Kpcs 3.3V EMP8042B-33VN03NRR
5.0V EMP8042B-50VN03NRR
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 4/16
Pin Functions Name SOT-23-5 SOT-89-3 SOT23-3 Function
VIN 1 2 3
Supply Voltage Input
Require a minimum input capacitor of close to 1µF to ensure stability
and sufficient decoupling from the ground pin.
GND 2 1 1 Ground Pin
EN 3 N/A N/A
Shutdown Input
The EN pin is pulled “High” internally. Set the regulator into the disable
mode by pulling the EN pin low.
ADJ
4 N/A N/A
Adjust:
Feedback input. Connect to resistive voltage-divider network.
Vref2R1R1VOUT ⋅⎟⎠
⎞⎜⎝
⎛ +=
NC
(Fixed
output)
No connection
VOUT 5 3 2 Output Voltage Functional Block Diagram
FIG.1. Functional Block Diagram of EMP8042
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 5/16
Absolute Maximum Ratings (Notes 1, 2)
VIN ,EN -0.3V to 22V
Power Dissipation (Note 5)
Storage Temperature Range -65°C to 150°C
Junction Temperature (TJ) 160°C
Lead Temperature (Soldering, 10 sec.) 260°C
ESD Rating
Human Body Model 2KV
Operating Ratings (Note 1, 2)
Supply Voltage (EMP8042) 3.0V to 20V
Supply Voltage (EMP8042B) 2.7V to 20V
Operating Temperature Range -40°C to 85°C
Thermal Resistance (θJA , Note 3)) 152°C/W (SOT-23-5)
101°C/W (SOT-89-3)
Thermal Resistance (θJC , Note 4)) 81°C/W (SOT-23-5)
54°C/W (SOT-89-3)
Electrical Characteristics TA = 25°C, VOUT(NOM)=5V; unless otherwise specified, all limits guaranteed for VIN = VOUT +1V, CIN = COUT =1µF.
Symbol Parameter Conditions Min Typ
(Note 6) Max Units
ΔVOTL Output Voltage Tolerance IOUT = 10mA
VOUT (NOM) +1V ≤ VIN ≤ 20V
EMP8042 -2.5 +2.5 % of
VOUT (NOM) EMP8042B -1 +1
Vref Reference voltage EMP8042 1.176 1.200 1.224
V EMP8042B 1.188 1.200 1.212
IOUT Maximum Output Current Average DC Current Rating 150 mA
ILIMIT Output Current Limit 300 mA
IQ Supply Current
IOUT = 0.1mA 13 50
µA IOUT = 100mA 50 100
IOUT = 150mA 80 130
Shutdown Supply Current VOUT = 0V, EN = GND 1 5
VDO Dropout Voltage
VOUT=5.0V (Note. 7)
IOUT = 30mA 135
mV IOUT = 100mA 500
IOUT = 150mA 780
ΔVOUT
Line Regulation IOUT = 1mA,
(VOUT + 1V) ≤ VIN ≤ 20V 0.1 %
Load Regulation 0.1mA ≤ IOUT ≤ 100mA 0.5 %
en Output Voltage Noise IOUT=10mA,10Hz ≤ f ≤ 100kHz
VOUT = 5.0V 800 µVRMS
VEN EN Input Threshold VIH, (VOUT + 1V) ≤ VIN ≤ 20V 1.0
V VIL, (VOUT + 1V) ≤ VIN ≤ 20V 0.3
IEN EN Input Bias Current EN = GND or VIN 0.1 µA
TSD
Thermal Shutdown
Temperature 160
Thermal Shutdown Hysteresis 30
tON Start-Up Time COUT = 1.0µF, VOUT at 90% of Final Value 500 µs
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 6/16
Note 1: Absolute maximum ratings indicate limits beyond which damage may occur. Note 2: All voltages are in respect to the potential of the ground pin. Note 3: θJA is measured in the natural convection at TA=25 on a high effectively thermal conductivity test board (2
layers, 2S0P). Note 4: θJC represents the resistance between the chip and the top of the package case. Note 5: Maximum power dissipation for the device is calculated using the following equation:
JAθAT - J(MAX)T
DP =
Where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. For example, for the SOT-89-3 package θ JA=101°C/W, TJ(MAX)=160°C and using TA=25°C, the maximum power dissipation is 1.33W. The derating factor (-1/θJA)=-9.9mW/°C. Below 25°C the power dissipation figure can be increased by 9.9mW per degree and similarly decreased by this factor for temperatures above 25°C.
Note 6: Typical values represent the most likely parametric norm. Note 7: Dropout voltage is measured by reducing VIN until VOUT drops to 98% its nominal value.
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 7/16
Typical Performance Characteristics Unless otherwise specified, VIN = VOUT (NOM) + 1V, VOUT=5V, CIN = COUT = 1.0µF, TA = 25°C
PSRR vs. Frequency (VOUT=5.0V) Dropout Voltage vs. Load Current (VOUT=5.0V)
Frequency (Hz)
T
10 20 50 100 200 500 1k 2k 5k 10k 20k 50k100k-70
-60
-50
-40
-30
-20
-10
0
PSR
R(d
B)
1mA10mA30mA50mA
Vout=5V
0mV
100mV
200mV
300mV
400mV
500mV
600mV
700mV
0mA 20mA 40mA 60mA 80mA 100mAIout
Drop
out v
olta
ge
25 -40 85
Dropout Voltage vs. Temp (VOUT=5.0V) VOUT vs. IOUT (VOUT=3.3V)
0mV
100mV
200mV
300mV
400mV
500mV
600mV
700mV
-45 -30 -15 0 15 30 45 60 75 90Temperature
Drop
out v
olta
ge
30mA 100mA
3.23.223.243.263.283.3
3.323.343.363.383.4
1mA 20mA 40mA 60mA 80mA 100mA 150mAIOUT
VOUT
(V)
-40'C 25'C 85'C
Enable Response (VOUT=5.0V, IOUT=0.1mA) Enable Response (VOUT=5.0V, IOUT=30mA)
~400us
~400us
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 8/16
Typical Performance Characteristics (cont.) Unless otherwise specified, VIN = VOUT (NOM) + 1V, VOUT=5V, CIN = COUT = 1.0µF, TA = 25°C
Line transient (IOUT=1mA) Line transient (IOUT=30mA)
Vin(1V/div)
Vout(20mV/div)
Time(100us/div)
Vin(1V/div)
Vout(50mV/div)
Time(100us/div)
Load transient (VOUT=5.0V) Load transient (VOUT=5.0V)
Vout(200mV/div)
Iout(50mA/div)
Time(100us/div)
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 9/16
Application Information
General Description
Referring to Fig.1 as shown in the Functional Block Diagram section, the EMP8042 adopts the classical regulator
topology in which negative feedback control is used to perform the desired voltage regulating function. The
negative feedback is formed by using feedback resistors (R1, R2) to sample the output voltage for the
non-inverting input of the error amplifier, whose inverting input is set to the bandgap reference voltage. By the
virtue of its high open-loop gain, the error amplifier operates to ensure that the sampled output feedback
voltage at its non-inverting input is virtually equal to the preset bandgap reference voltage.
The error amplifier compares the voltage difference at its inputs and produces an appropriate driving voltage
to the P-channel MOS pass transistor to control the amount of current reaching the output. If there are
changes in the output voltage due to load changes, the feedback resistors register such changes to the
non-inverting input of the error amplifier. The error amplifier then adjusts its driving voltage to maintain virtual
short between its two input nodes under all loading conditions. In a nutshell, the regulation of the output
voltage is achieved as a direct result of the error amplifier keeping its input voltages equal. This negative
feedback control topology is further augmented by the shutdown, the fault detection, and the temperature
and current protection circuitry.
Output Capacitor
The EMP8042 is specially designed for use with ceramic output capacitors of as low as 1.0µF to take advantage
of the savings in cost and space as well as the superior filtering of high frequency noise. Capacitors of higher
value or other types may be used, but it is important to make sure its equivalent series resistance (ESR) is
restricted to less than 0.5Ω. The use of larger capacitors with smaller ESR values is desirable for applications
involving large and fast input or output transients, as well as for situations where the application systems are not
physically located immediately adjacent to the battery power source. Typical ceramic capacitors suitable for
use with the EMP8042 are X5R and X7R. The X5R and the X7R capacitors are able to maintain their
capacitance values to within ±20% and ±10%, respectively, as the temperature increases.
No-Load Stability
The EMP8042 is capable of stable operation during no-load conditions, a mandatory feature for some
applications such as CMOS RAM keep-alive operations.
Input Capacitor
A minimum input capacitance of 1µF is required for EMP8042. The capacitor value may be increased without
limit. Improper workbench set-ups may have adverse effects on the normal operation of the regulator. A case
in point is the instability that may result from long supply lead inductance coupling to the output through the
gate capacitance of the pass transistor. This will establish a pseudo LCR network, and is likely to happen under
high current conditions or near dropout. A 10µF tantalum input capacitor will dampen the parasitic LCR action
thanks to its high ESR. However, cautions should be exercised to avoid regulator short-circuit damage when
tantalum capacitors are used, for they are prone to fail in short-circuit operating conditions.
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 10/16
Power Dissipation and Thermal Shutdown
Thermal overload results from excessive power dissipation that causes the IC junction temperature to increase
beyond a safe operating level. The EMP8042 relies on dedicated thermal shutdown circuitry to limit its total
power dissipation. An IC junction temperature TJ exceeding 160°C will trigger the thermal shutdown logic,
turning off the P-channel MOS pass transistor. The pass transistor turns on again after the junction cools off by
about 30°C. When continuous thermal overload conditions persist, this thermal shutdown action then results in
a pulsed waveform at the output of the regulator. The concept of thermal resistance θJA (°C/W) is often used
to describe an IC junction’s relative readiness in allowing its thermal energy to dissipate to its ambient air. An IC
junction with a low thermal resistance is preferred because it is relatively effective in dissipating its thermal
energy to its ambient, thus resulting in a relatively low and desirable junction temperature. The relationship
between θJA and TJ is as follows:
TJ = θJA x (PD) + TA
TA is the ambient temperature, and PD is the power generated by the IC and can be written as:
PD = IOUT (VIN - VOUT)
As the above equations show, it is desirable to work with ICs whose θJA values are small such that TJ does not
increase strongly with PD. To avoid thermally overloading the EMP8042, refrain from exceeding the absolute
maximum junction temperature rating of 160°C under continuous operating conditions. Overstressing the
regulator with high loading currents and elevated input-to-output differential voltages can increase the IC die
temperature significantly.
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 11/16
Application Circuit for ADJ output
Vref2R1R1VOUT ⋅⎟⎠⎞
⎜⎝⎛ +=
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 12/16
Package Outline Drawing SOT-23-5
TOP VIEW
SIDE VIEW
PIN#1 MARK
1 3
5 4
DETAIL A
E E1
e
D
A
A1
L
1 3
b
DETAIL A
c
Min. Max.
A 0.90 1.45
A1 0.00 0.15
b 0.30 0.50
c 0.08 0.25
D 2.70 3.10
E 1.40 1.80
E1 2.60 3.00
e
L 0.30 0.60
0.95 BSC
SymbolDimension in mm
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 13/16
Package Outline Drawing SOT-89-3
Min Max
A 1.4 1.6
b 0.4 0.56
c 0.35 0.41
D 4.4 4.6
D1 1.5 1.83
E 2.29 2.6
E1 3.94 4.25
e
L 0.89 1.2
Dimension in mmSymbol
1.50 BSC
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 14/16
Package Outline Drawing SOT-23-3
A1
A
e
D
E1
b c
L
DETAIL A
TOP VIEW
SIDE VIEW DETAIL A
PIN#1MARK
1 2
3
1 2 3
E
Min. Max.
A 0.90 1.45
A1 0.00 0.15
b 0.30 0.50
c 0.08 0.25
D 2.70 3.10
E 1.40 1.80
E1 2.60 3.00
e
L 0.30 0.60
1.90 BSC
SymbolDimension in mm
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 15/16
Revision History
Revision Date Description
0.1 2010.08.27 Original
1.0 2011.02.23
1. Skip “Preliminary” 2. Page1 revise “Typical Application“ 3. Page2 add SOT-23-5 package 4. Page3 add SOT-23-5 “Pin Functions”
1.1 2011.12.12
1) Added ADJ output voltage option 2) Modified 100mA output driving capacity to 150mA. 3) Modified the output voltage accuracy is based on
Iout=10mA this condition. 4) Added Iout=150mA spec. into electrical characteristics
table.
1.2 2012.04.20
1) Added the typical value of supply current IQ=13uA at Iout=0.1mA.
2) Updated the maximum value of supply current IQ=50uA at Iout=0.1mA.
3) Updated the package outline drawing.
1.3 2012.08.31 1) Added the typical value of shutdown supply current
IQ=1uA at EN=GND. 2) Added the EN input Threshold.
1.4 2013.10.04 Updated the package outline drawing.
1.5 2017.06.26 Added EMP8042B series product
ESMT EMP8042
Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2017 Revision: 1.5 16/16
Important Notice
All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.