High Frequency Transformer Linked Converters For Photovoltaic Applications Q Li [Thesis]

“The old year is closing;

What’s done is done.

Look forward to the New Year

And let’s have some fun!”

- Pamela Summers

HIGH FREQUENCY TRANSFORMER LINKED CONVERTERS

FOR PHOTOVOLTAIC APPLICATIONS

Quan Li, B.Eng., M.Eng.

Dissertation submitted in partial fulfilment

of the requirements for the degree of

Doctor of Philosophy

Faculty of Sciences, Engineering and Health

Central Queensland University

Rockhampton

Australia

30 June 2006

ii

ABSTRACT

This thesis examines converter topologies suitable for Module Integrated Converters

(MICs) in grid interactive photovoltaic (PV) systems, and makes a contribution to

the development of the MIC topologies based on the two-inductor boost converter,

which has received less research interest than other well known converters.

The thesis provides a detailed analysis of the resonant two-inductor boost converter

in the MIC implementations with intermediate constant DC links. Under variable

frequency control, this converter is able to operate with a variable DC gain while

maintaining the resonant condition. A similar study is also provided for the resonant

two-inductor boost converter with the voltage clamp, which aims to increase the

output voltage range while reducing the switch voltage stress. An operating point

with minimized power loss can be also established under the fixed load condition.

Both the hard-switched and the soft-switched current fed two-inductor boost

converters are developed for the MIC implementations with unfolding stages. Non-

dissipative snubbers and a resonant transition gate drive circuit are respectively

employed in the two converters to minimize the power loss.

The simulation study of a frequency-changer-based two-inductor boost converter is

also provided. This converter features a small non-polarised capacitor in a second

phase output to provide the power balance in single phase inverter applications.

Four magnetic integration solutions for the two-inductor boost converter have also

been presented and they are promising in reducing the converter size and power loss.

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TABLE OF CONTENTS

ABSTRACT ................................................................................................................ii

TABLE OF CONTENTS ...........................................................................................iii

LIST OF FIGURES..................................................................................................viii

LIST OF TABLES ..................................................................................................xvii

LIST OF SYMBOLS................................................................................................xix

LIST OF ACRONYMS...........................................................................................xxx

ACKNOWLEDGEMENTS ..................................................................................xxxii

DECLARATION..................................................................................................xxxiii

PUBLICATIONS .................................................................................................xxxiv

1. INTRODUCTION...............................................................................................1

2. LITERATURE SURVEY ...................................................................................6

2.1 Stand Alone versus Grid Interactive Systems .............................................7

2.2 Possible Arrangements for Grid Interactive Systems..................................8

2.3 Figures of Merits of State-of-the-Art MICs ..............................................12

2.3.1 Power Density ...................................................................................13

2.3.2 Efficiency ..........................................................................................14

2.3.3 Mean Time Between Failures and Mean Time to First Failure.........14

2.3.4 Balance of System Cost.....................................................................15

2.4 Possible MIC Topologies ..........................................................................16

2.4.1 MIC with an Intermediate Constant DC Link ...................................19

2.4.2 MIC with an Unfolding Stage ...........................................................24

2.4.3 MIC with a Frequency Changer ........................................................39

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2.5 Summary....................................................................................................43

3. RESEARCH OPPORTUNITIES ......................................................................45

3.1 Power Balance in the MICs.......................................................................45

3.1.1 Power Balance Issue in the Single Phase Converters........................45

3.1.2 Three-Phase PV Converters ..............................................................48

3.2 Two-Inductor Boost Converter..................................................................52

3.2.1 Two-Inductor Boost Converter with an Intermediate Constant DC

Link....................................................................................................55

3.2.2 Two-Inductor Boost Converter with an Unfolding Stage .................57

3.2.3 Two-Inductor Boost Converter with a Frequency Changer ..............57

3.3 Summary....................................................................................................59

4. ZERO-VOLTAGE SWITCHING TWO-INDUCTOR BOOST CONVERTER..

...........................................................................................................................60

4.1 Introduction ...............................................................................................60

4.1.1 Three Circuit Parameters ...................................................................61

4.1.2 Wide Load Range Operation .............................................................64

4.2 Design Method and Control Function .......................................................65

4.2.1 Design Method ..................................................................................66

4.2.2 Control Function................................................................................68

4.3 Wide Load Range Operation of the ZVS Two-Inductor Boost Converter 71

4.3.1 State Analysis ....................................................................................71

4.3.2 Design Process...................................................................................76

4.3.3 Theoretical and Simulation Waveforms............................................87

4.3.4 Experimental Results.......................................................................100

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4.4 ZVS Two-Inductor Boost Converter with the Voltage Clamp................106

4.4.1 Topology..........................................................................................106

4.4.2 State Analysis ..................................................................................107

4.4.3 Design Process.................................................................................117

4.4.4 Theoretical and Simulation Waveforms..........................................131

4.5 Comparisons of the Two ZVS Two-Inductor Boost Converters.............144

4.5.1 Output Voltage Range .....................................................................144

4.5.2 Switching Frequency Range............................................................144

4.5.3 Resonant Inductor............................................................................145

4.5.4 Switch Voltage Stress......................................................................145

4.5.5 Soft-Switching Condition................................................................145

4.5.6 Efficiency ........................................................................................146

4.6 Power Loss Analysis ...............................................................................146

4.6.1 Variable Power Loss Terms ............................................................147

4.6.2 Optimised Operating Point ..............................................................157

4.7 Summary..................................................................................................159

5. INTEGRATED MAGNETICS .......................................................................161

5.1 State Analysis of the Hard-Switched Two-Inductor Boost Converter with

Discrete Magnetics ..................................................................................163

5.2 Integrated Magnetics with Magnetic Core Integration............................168

5.2.1 Two-Inductor Boost Converter with Structure A Magnetic Integration

.........................................................................................................169

5.2.2 Equivalent Input and Transformer Magnetising Inductances .........171

5.2.3 DC Gain...........................................................................................177

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5.2.4 DC and AC Flux Densities ..............................................................178

5.2.5 Current Ripples................................................................................184

5.3 Integrated Magnetics with Winding Integration......................................186

5.3.1 Winding Integration Technique.......................................................186

5.3.2 Structure B Magnetic Integration ....................................................188

5.3.3 Structures C and D Magnetic Integration........................................192

5.4 Comparisons of the Four Magnetic Integration Structures .....................203

5.4.1 Structure A Magnetic Integration....................................................204

5.4.2 Structure B Magnetic Integration ....................................................204

5.4.3 Structure C Magnetic Integration ....................................................209

5.4.4 Structure D Magnetic Integration....................................................212

5.4.5 Comparisons ....................................................................................219

5.5 Experimental Waveforms of the Hard-Switched Two-Converter Boost

Converter with Structures A and C Magnetic Integration.......................221

5.6 Soft-Switched Two-Inductor Boost Converter with Structure B Magnetic

Integration................................................................................................224

5.6.1 ZVS Two-Inductor Boost Converter with Structure B Magnetic

Integration........................................................................................224

5.6.2 Equivalent Input and Transformer Magnetising Inductances .........226

5.6.3 DC Fluxes........................................................................................234

5.6.4 State Analysis ..................................................................................236

5.6.5 Theoretical and Experimental Waveforms......................................240

5.7 Summary..................................................................................................245

6. CURRENT FED TWO-INDUCTOR BOOST CONVERTER.......................246

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6.1 Buck Conversion Stage ...........................................................................246

6.2 Hard-Switched Current Fed Two-Inductor Boost Converter ..................249

6.2.1 Circuit Diagram...............................................................................249

6.2.2 Non-Dissipative Snubbers ...............................................................252


6.3 Soft-Switched Current Fed Two-Inductor Boost Converter ...................295

6.3.1 Circuit Diagram...............................................................................296

6.3.2 Resonant Gate Drive........................................................................298


6.4 Summary..................................................................................................322

7. TWO-INDUCTOR BOOST CONVERTER WITH A FREQUENCY

CHANGER......................................................................................................324

7.1 Introduction .............................................................................................325

7.2 Two-Inductor Boost Converter with a Frequency Changer ....................326

7.2.1 Circuit Diagram...............................................................................326

7.2.2 Constant Power Output....................................................................327

7.2.3 Open Loop PWM ............................................................................330

7.2.4 Closed Loop Transformer Volt-Second Balance Control ...............335

7.2.5 Simulation Results...........................................................................337

7.3 Summary..................................................................................................344

8. CONCLUSIONS .............................................................................................345

REFERENCES........................................................................................................351

APPENDIX COMMERCIAL AC MODULE INVERTERS ..............................376

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LIST OF FIGURES

Figure 2.1 World PV Cell/Module Production (1988-2005).......................................7

Figure 2.2 Central Converter Technology...................................................................9

Figure 2.3 String Converter Technology...................................................................10

Figure 2.4 MIC Technology ......................................................................................11

Figure 2.5 MIC with a Line Frequency Transformer ................................................17

Figure 2.6 MIC with a High Frequency Transformer ...............................................17

Figure 2.7 Isolated DC-DC Converters .....................................................................19

Figure 2.8 MIC with an Intermediate Constant DC Link..........................................20

Figure 2.9 Topology Proposed in [51] ......................................................................20

Figure 2.10 Topology Proposed in [52] ....................................................................21

Figure 2.11 MIC with an Unfolding Stage................................................................25









Figure 2.20 Topology Proposed in [70] and [72] ......................................................30



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Figure 2.25 Topology Proposed in [77] and [78] ......................................................32

Figure 2.26 The Topology Proposed in [79] and [80]...............................................33

Figure 2.27 Topologies Proposed in [81]-[84] ..........................................................34






Figure 2.33 MIC with a Frequency Changer.............................................................40

Figure 2.34 Bi-Directional Switches .........................................................................40

Figure 2.35 Topology Proposed in [104] ..................................................................41




Figure 3.1 Simulation Waveforms of the Single Phase Resistive Load....................47

Figure 3.2 Three-Phase Photovoltaic Converter .......................................................48

Figure 3.3 Simulation Waveforms of the Three-Phase Resistive Load ....................49

Figure 3.4 Two-Inductor Boost Converter with a Three-Phase PWM Inverter ........50

Figure 3.5 Three-Phase PV Converter Derived from the Current-Tripler Rectifier .51

Figure 3.6 Three Phase Two-Inductor Boost Converter ...........................................52

Figure 3.7 Current-Doubler Rectifier ........................................................................55

Figure 3.8 Hard-Switched Two-Inductor Boost Converter with a PWM Inverter....56

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Figure 3.9 Soft-Switched Two-Inductor Boost Converter with a PWM Inverter .....56

Figure 3.10 Hard-Switched Two-Inductor Boost Converter with an Unfolder.........58

Figure 3.11 Soft-Switched Two-Inductor Boost Converter with an Unfolder ..........58

Figure 3.12 Two-Inductor Boost Converter with a Frequency Changer...................58

Figure 4.1 ZVS Two-Inductor Boost Converter........................................................61

Figure 4.2 Equivalent Resonant Circuit ....................................................................62

Figure 4.3 Resonant Waveforms of One Discontinuous Mode.................................63

Figure 4.4 Four Possible States .................................................................................73

Figure 4.5 Resonant Capacitor Voltage and Inductor Current Waveforms ..............74

Figure 4.6 Surface Vd in Region 1.............................................................................77

Figure 4.7 Surfaces VQ,peak and VQ,rating in Region 1 .................................................79

Figure 4.8 Surfaces ),(,1 kh dαα and ),(,2 kh dαα .......................................................80

Figure 4.9 Control Function )( dM αα .......................................................................82

Figure 4.10 Surface Vd in Region 2...........................................................................83

Figure 4.11 Surfaces VQ,peak and VQ,rating in Region 2 ...............................................84

Figure 4.12 Surfaces ),( 1,1 kh ∆∆ and ),( 1,2 kh ∆∆ in Region 2 ..................................85

Figure 4.13 Control Function )( 1∆∆M .....................................................................86

Figure 4.14 Theoretical Waveforms of Point 1 .........................................................89

Figure 4.15 Simulation Waveforms of Point 1..........................................................90





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Figure 4.25 Simulation Waveforms of Point 6........................................................100

Figure 4.26 Experimental Waveforms of Point 1....................................................102





Figure 4.31 Output Voltage under Each Operating Point .......................................105

Figure 4.32 ZVS Two-Inductor Boost Converter with the Voltage Clamp ............107

Figure 4.33 Six Possible States in Operating Set 2 .................................................110

Figure 4.34 Five States in Operating Set 3..............................................................114

Figure 4.35 Equivalent Primary Circuit with a Voltage Clamped Capacitor..........118

Figure 4.36 Surface Vd in Region 1.........................................................................123

Figure 4.37 Surfaces ),(,1 kh dαα and ),(,2 kh dαα in Region 1 ...............................124

Figure 4.38 Control Function )( dααM ...................................................................126

Figure 4.39 Surface Vd in Region 2.........................................................................127

Figure 4.40 Surfaces ),( 1,1 kh ∆∆ and ),( 1,2 kh ∆∆ in Region 2 ................................128

Figure 4.41 Control Function )( 1∆∆M ...................................................................129

Figure 4.42 Theoretical Waveforms of Operating Point 1 ......................................133

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Figure 4.43 Simulation Waveforms of Operating Point 1.......................................134









Figure 4.52 Output Voltage under Each Operating Point .......................................143

Figure 4.53 Power Loss in the MOSFETs in Region 2...........................................152

Figure 4.54 Power Loss in the Resonant Inductor in Region 2...............................153

Figure 4.55 Power Loss in the Resonant Capacitors in Region 2 ...........................153

Figure 4.56 Total Variable Power Loss in Region 2 ...............................................154

Figure 4.57 Power Loss in the MOSFETs in Region 1...........................................155

Figure 4.58 Power Loss in the Resonant Inductor in Region 1...............................156

Figure 4.59 Power Loss in the Resonant Capacitors in Region 1 ...........................156

Figure 4.60 Total Variable Power Loss in Region 1 ...............................................157

Figure 4.61 Peak Switch Voltage in Region 1 ........................................................159

Figure 5.1 Hard-Switched Two-Inductor Boost Converter .....................................163

Figure 5.2 Four States of the Hard-Switched Two-Inductor Boost Converter........164

Figure 5.3 Equivalent Transformer Model ..............................................................166

Figure 5.4 Current Waveforms in the Hard-Switched Two-Inductor Boost Converter

...............................................................................................................169

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Figure 5.5 Two-Inductor Boost Converter with Structure A Magnetic Integration 170

Figure 5.6 Structure A Magnetic Circuits ...............................................................175

Figure 5.7 Flux Waveforms in Structure A Core ....................................................183

Figure 5.8 Four Ways to Wind the Two Combined Windings................................187

Figure 5.9 Two-Inductor Boost Converter with Structure B Magnetic Integration 189

Figure 5.10 Structure B Magnetic Circuits..............................................................189

Figure 5.11 Two-Inductor Boost Converter with Structure C Magnetic Integration

.............................................................................................................192

Figure 5.12 Structure C Magnetic Circuits..............................................................192

Figure 5.13 Two-Inductor Boost Converter with Structure D Magnetic Integration

.............................................................................................................198

Figure 5.14 Structure D Magnetic Circuits .............................................................198

Figure 5.15 Flux and the Current Waveforms in Structure B .................................208

Figure 5.16 Flux and the Current Waveforms in Structure C .................................213

Figure 5.17 AC Flux and Current Waveforms in the Hard-Switched Two-Inductor

Boost Converter with Structure A Magnetic Integration.....................222


Boost Converter with Structure C Magnetic Integration.....................223

Figure 5.19 ZVS Two-Inductor Boost Converter with a Voltage-Doubler Rectifier

.............................................................................................................225

Figure 5.20 ZVS Two-Inductor Boost Converter with Structure B Magnetic

Integration............................................................................................225

Figure 5.21 ZVS Two-Inductor Boost Converter with the Resonant Inductance in the

Transformer Secondary Side ...............................................................227

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Figure 5.22 Magnetic Circuit of Structure B in the ZVS Two-Inductor Boost

Converter .............................................................................................230

Figure 5.23 Structure B Magnetic Circuit with the Leakage Flux Path ..................240

Figure 5.24 Theoretical Waveforms........................................................................242

Figure 5.25 Experimental Voltage and Current Waveforms...................................243

Figure 5.26 Experimental AC Flux, Voltage and Current Waveforms...................244

Figure 6.1 Hard-Switched Two-Inductor Boost Converter with a Two-Phase Buck

Converter ...............................................................................................248

Figure 6.2 Soft-Switched Two-Inductor Boost Converter with a Two-Phase Buck

Converter ...............................................................................................248

Figure 6.3 Hard-Switched Two-Inductor Boost Converter with a Two-Phase

Synchronous Buck Converter................................................................250

Figure 6.4 Theoretical Switching Waveforms in the Buck and the Boost Stages...252

Figure 6.5 Passive Non-Dissipative Snubbers Proposed in [112]...........................253

Figure 6.6 Hard-Switched Current Fed Two-Inductor Boost Converter with Non-

Dissipative Snubbers .............................................................................254

Figure 6.7 Equivalent Snubber Circuit ....................................................................255

Figure 6.8 Six States in Mode 1 Operation .............................................................258

Figure 6.9 Snubber Voltage and Current Waveforms in Mode 1 Operation...........259

Figure 6.10 Six States in Mode 2 Operation ...........................................................265

Figure 6.11 Snubber Voltage and Current Waveforms in Mode 2 Operation.........266

Figure 6.12 Six States in Mode 3 Operation ...........................................................270

Figure 6.13 Snubber Voltage and Current Waveforms in Mode 3 Operation.........271

Figure 6.14 Theoretical Waveforms in Mode 1 Snubber Operation .......................282

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Figure 6.17 Experimental Waveforms in Mode 1 Snubber Operation....................285



Figure 6.20 Experimental Waveforms in the Two-Phase Buck Converter .............292

Figure 6.21 Experimental Waveforms of the Sinusoidal Modulation.....................293

Figure 6.22 Experimental Waveforms in the Unfolder ...........................................293

Figure 6.23 Experimental Waveforms in the Two-Inductor Boost Cell .................294

Figure 6.24 Experimental Waveforms in the Snubber ............................................294

Figure 6.25 Photo of the Hard-Switched Current Fed Two-Inductor Boost Converter

.............................................................................................................295

Figure 6.26 Soft-Switched Two-Inductor Boost Converter with a Two-Phase

Synchronous Buck Converter ..............................................................296

Figure 6.27 Average Variable Power Loss in Region 1..........................................297

Figure 6.28 Average Variable Power Loss in Region 2..........................................298

Figure 6.29 Conventional MOSFET Gate Drive Circuit.........................................299

Figure 6.30 Resonant Transition Gate Drive Proposed in [147] and [181].............301

Figure 6.31 Resonant Transition Gate Drive for the Two-Inductor Boost Cell ......302

Figure 6.32 Theoretical Waveforms in the Resonant Transition Gate Drive..........303

Figure 6.33 Simulation Waveforms of the Resonant Transition Gate Drive ..........311

Figure 6.34 Experimental Waveforms of the Resonant Transition Gate Drive ......312

Figure 6.35 Experimental Waveforms in the Two-Phase Buck Converter .............319

Figure 6.36 Experimental Waveforms of the Sinusoidal Modulation.....................320

xvi

Figure 6.37 Experimental Waveforms in the Unfolder ...........................................320

Figure 6.38 Experimental Waveforms in the Two-Inductor Boost Cell .................321

Figure 6.39 Experimental Waveform of the Diode Voltage ...................................321

Figure 6.40 Photo of the Soft-Switched Current Fed Two-Inductor Boost Converter

.............................................................................................................322

Figure 7.1 Two-Inductor Boost Converter with a Frequency Changer...................327

Figure 7.2 Demanded Low Frequency Switch Currents .........................................334

Figure 7.3 Switching Sequence in One Switching Period.......................................334

Figure 7.4 Feedback Control Circuit .......................................................................337

Figure 7.5 Simulation Circuit Model.......................................................................338

Figure 7.6 Simulation Waveforms of the Two-Phase Output Voltages ..................340

Figure 7.7 Simulation Waveforms of the High Frequency Capacitor Voltages......341

Figure 7.8 Simulation Waveforms of the Secondary Switch Currents ...................342

Figure 7.9 Simulation Waveforms of the MOSFET and Transformer Primary

Voltages .................................................................................................343

xvii

LIST OF TABLES

Table 4.1 Three Operating Regions...........................................................................65

Table 4.2 Equations in Regions 1 and 2 ....................................................................72

Table 4.3 Maximum and Minimum Values of Vd in Region 1 .................................78

Table 4.4 Initial Calculation Results in Region 1......................................................80

Table 4.5 Numerical Relationship of αd and k ..........................................................81

Table 4.6 Numerical Relationship of ∆1 and k ..........................................................85

Table 4.7 Final Calculation Results of the ZVS Two-Inductor Boost Converter .....87

Table 4.8 Selected Operating Points .........................................................................88

Table 4.9 Output Voltage under Each Operating Point...........................................105

Table 4.10 Possible Operating Sets .........................................................................109

Table 4.11 Design Equations in the Two Converters..............................................121

Table 4.12 Maximum and Minimum Values of Vd.................................................123

Table 4.13 Initial Calculation Results in Region 1..................................................123

Table 4.14 Numerical Relationship of αd and k ......................................................125

Table 4.15 Numerical Relationship of ∆1 and k ......................................................128

Table 4.16 Final Calculation Results in the ZVS Two-Inductor Boost Converter with

the Voltage Clamp.................................................................................131

Table 4.17 Selected Operating Points .....................................................................131

Table 4.18 Output Voltage under Each Operating Point.........................................143

Table 5.1 Comparisons of the Four Integrated Magnetic Structures.......................220

Table 6.1 Border Conditions for Four Operation Modes of the Snubber Circuit....281

Table 6.2 Power Consumptions in Two Gate Drive Circuits ..................................314

xviii

Table 6.3 Resonant Transition Gate Drive Power Loss Breakdown.......................314

xix

LIST OF SYMBOLS

Ac Cross section area of the centre core leg

ACb Amplitude of the power balancing capacitor voltage

AO Amplitude of the resistive load voltage

B1,max, B2,max Peak flux densities in the two outer core legs

Bc,max Peak flux density in the centre outer core leg

C1, C2, Cr Effective resonant capacitance

Cb Power balancing capacitance

Ciss Power MOSFET input capacitance

Ciss,t, Ciss,b Input capacitances of the top and bottom control transistors in

the gate drive circuit

Coss, Coss,Q3, Coss,Q4 MOSFET output capacitances

Cs, Cs1, Cs2 Snubber capacitances

Ctj (j = 1, 2, 3) High frequency path capacitance

CO, CO1, CO2 Converter output capacitances

Dboost Boost stage switch duty ratio

Dbuck Buck stage switch duty ratio

Dj (j = 1, 2, 3, 4) Ratio of the duration of each state to the switching period

Ds Switch duty ratio

Ds,min Minimum switch duty ratio

DQ1, DQ2 Instantaneous MOSFET duty ratios

DSj+ (j = 1, 2, 3) Switch duty ratio with positive transformer secondary current

DSj- (j = 1, 2, 3) Switch duty ratio with negative transformer secondary current

xx

DF Dissipation factor of the capacitor

E Input voltage

fboost Boost stage switching frequency

fbuck Buck stage MOSFET switching frequency

fgrid Grid frequency

fs Switching frequency

ĝα(αd), ĝ∆(∆1) Ratios of the average of the absolute value of the transformer

primary current to the average input inductor current in

Regions 1 and 2 containing the independent variable only

ĝα(αd, k), ĝ∆(∆1, k) Ratios of the average of the absolute value of the transformer

primary current to the average input inductor current in

Regions 1 and 2 containing both the dependent and the

independent variables

ĝα,c(αd, k), ĝ∆,c(∆1, k) Ratios of the average resonant inductor current to the average

input inductor current in Regions 1 and 2 over the duration

when the resonant capacitor voltage is clamped

h1,α(αd, k), h2,α(αd, k) Supplemental functions defined in the circuit constraint in

Region 1

h1,∆(αd, k), h2,∆(∆1, k) Supplemental functions defined in the circuit constraint in

Region 2

i0 Average input inductor current over one high frequency

switching period

i1, i2 Instantaneous input inductor currents

ile Transformer leakage inductance current

xxi

ip Transformer primary current

is Transformer secondary current

is1 Ideal secondary winding current in the equivalent transformer

model

is2 Magnetising current reflected to the transformer secondary

iC1, iC2 Resonant capacitor currents

iCb Power balancing capacitor current

iDc Coupled inductor clamp winding current reflected to the main

winding

iG3, iG4 Instantaneous MOSFET gate charging or discharging currents

iIN Instantaneous input current

iL1p Coupled inductor main winding L1p current

iL1s Coupled inductor clamp winding L1s current

iL2 Coupled inductor L2p, L2s current

iLr Resonant inductor current

iLsr Snubber inductor current

iLG Instantaneous inductor current in the gate drive circuit

iO Instantaneous output current

iQ1, iQ2 MOSFET drain source currents

iQ3t, iQ4t Instantaneous drain source currents in the top control

transistors in the gate drive circuit

iQ3b, iQ4b Instantaneous drain source currents in the bottom control


iSj,LF (j = 1, 2, 3) Low frequency term of the switch current

xxii

∆i1, ∆i2 Current ripples in the two input inductors

∆i1,j (j = 1, 2, 3, 4) Current ripple in one input inductor in each state

∆i2,j (j = 1, 2, 3, 4) Current ripple in one input inductor in each state

∆ip,j (j = 1, 2, 3, 4) Transformer primary current ripple in each state

∆is Transformer secondary current ripple

∆is,j (j = 1, 2, 3, 4) Transformer secondary current ripple in each state

∆is1,j (j = 1, 2, 3, 4) Ideal secondary winding current ripple in the equivalent

transformer model in each state

∆is2,j (j = 1, 2, 3, 4) Magnetising current ripple in the equivalent transformer

model in each state

∆iIN Input current ripple

∆iIN,j (j = 1, 2, 3, 4) Input current ripple in each state

I0, I1, I2 Average input inductor currents

I1,j (j = 1, 2, 3, 4) Average input inductor current in each state

I2,j (j = 1, 2, 3, 4) Average input inductor current in each state

Is Transformer secondary current amplitude when only one

MOSFET is on in the two-inductor boost converter

Is,j (j = 1, 2, 3, 4) Average transformer secondary current in each state

ICr,rms Effective forward current in the resonant capacitor

ID MOSFET drain current rating

IF Diode forward current rating

IG Average MOSFET gate charging or discharging current

IG3,rms Effective charging or discharging current in the power

xxiii

MOSFET gate

IIN Average input current

IIN,c Average input current over the duration when the resonant

capacitor voltage is clamped

IIN,nc Average input current over the duration when the voltage

clamping circuit is not active

ILr,rms Effective forward current in the resonant inductor

ILGp Peak inductor current in the gate drive circuit

ILG,rms Effective inductor current in the gate drive circuit

ILG’ Absolute inductor current at the end of its linear charging or

discharging interval in the gate drive circuit

IO Average output current

IQ3t,rms, IQ3b,rms Effective drain source currents in the top and bottom control


IQ,avg Average reverse current in the MOSFET

IQ,rms Effective forward current in the MOSFET

IS Average transformer secondary current

k Load factor

L, L1, L2 Input inductances

L1p, L2p Coupled inductor main winding inductances

L1s, L2s Coupled inductor clamp winding inductances

Lj (j = a, b, c, d, e) Inductance used in the analysis of the integrated magnetics

Lle Leakage inductance reflected to the transformer primary

Lles Leakage inductance reflected to the transformer secondary

xxiv

Lms Magnetising inductance reflected to the transformer

secondary

Lr Effective resonant inductance in series with the transformer

primary winding

Lrs Effective resonant inductance in series with the transformer

secondary winding

Lsr, Lsr1, Lsr2 Snubber inductances

LG Inductance in the gate drive circuit

Mα(αd), M∆(∆1) Control functions in Regions 1 and 2

n Transformer T turns ratio

nL Coupled inductor turns ratio

nT2 Transformer T2 turns ratio

Nc Number of turns of the centre core leg winding in Structure D

Magnetic Integration

Np, Np2 Numbers of turns of the transformer primary winding

Ns, Ns2 Numbers of turns of the transformer secondary winding

NL Number of turns of the input inductor winding

NLr Number of turns of the resonant inductor winding

NLG Number of turns of the inductor winding in the gate drive

circuit

p Instantaneous output power

pripple Ripple load power

ptotal,var Total variable power loss

pCb Instantaneous power of the power balancing capacitor

xxv

pCr Power loss in the resonant capacitors

pLr Power loss in the resonant inductors

pO Instantaneous load power

pQ Power loss in the MOSFETs

Pavg Average output power

Pdrive Total power loss in the gate drive circuit

Ploss,avg Average power loss of the total variable power loss

components in the two-inductor boost cell

PIN Average input power

PIN,c Average input power over the duration when the resonant

capacitor voltage is clamped

PIN,nc Average input power over the duration when the voltage

clamping circuit is not active

PLG Power loss in the inductor in the gate drive circuit

PQ34 Conduction power loss in the power MOSFET gate

PQ34tb,cond Conduction power loss in the control transistors in the gate

drive circuit

PQ34tb,drive CV2 loss in the control transistors in the gate drive circuit

Q Quality factor of the inductor

QG Total gate charge of the power MOSFET

QG,t Total gate charge of the top transistor in the gate drive circuit

QG,b Total gate charge of the bottom transistor in the gate drive

circuit

rα(αd, k), r∆(∆1, k) Functions used to calculate the average input power in

xxvi

Regions 1 and 2 of the ZVS two-inductor boost converter

with the voltage clamp

R Load resistance

Rg MOSFET internal gate resistance

RCr ESR of the resonant capacitor

RDS(on) MOSFET drain source on resistance

RDS(on),t , RDS(on),b Drain source on resistances of the top and bottom transistors

in the gate drive circuit

RLr Series dc plus ac resistance of the resonant inductor

RLG Series dc plus ac resistance of the inductor in the gate drive

circuit

ℜa Reluctance of the transformer leakage flux path in the air

ℜo Reluctance of the outer core leg

ℜc Reluctance of the centre core leg

tc Duration when the resonant capacitor voltage is clamped

tnc Duration when the voltage clamping circuit is not active

trr Diode reverse recovery time

Tboost Boost stage switching period

Tbuck Buck stage MOSFET switching period

Td1 Power MOSFET gate charging or discharging interval in the

gate drive circuit

Td2 Inductor linear charging or discharging interval in the gate

drive circuit

Tgrid Grid voltage period

xxvii

Ts Switching period

T Half switching period

v1, v2 Two-phase buck converter output voltages

vd Output capacitor voltage over one high frequency switching

period reflected to the transformer primary winding

vp, vT2p Transformer primary voltages

vp,avg Average transformer primary voltage

vs Transformer secondary voltage

vs1, vs2 Snubber diode anode voltages

vs,j (j = 1, 2, 3, 4) Transformer secondary voltage in each state

vC Boost stage converter output voltage

vC1, vC2 Resonant capacitor voltages

vCb Power balancing capacitor voltage

vCs1, vCs2 Snubber capacitor voltages

vCtj (j = 1, 2, 3) High frequency path capacitor voltage

vH Boost stage converter input voltage

vH,avg Boost stage converter average input voltage over one

equivalent buck stage switching period

vL1, vL2 Input inductor voltages

vLG Inductor voltage in the gate drive circuit

vO Instantaneous output voltage

vQ1,avg, vQ2,avg Average MOSFET drain source voltages

vQj (j = 1, 2, 3, 4) MOSFET drain source voltage

vQjG (j = 1, 2, 3, 4) MOSFET gate voltage

xxviii

Vc MOSFET or resonant capacitor clamping voltage

Vd Output capacitor voltage reflected to the transformer primary

winding

Vdc Capacitor rated dc voltage

VDD Gate drive circuit supply voltage

VDS MOSFET drain source voltage rating

VF Diode forward voltage drop

VO Average output voltage

VQ,peak MOSFET peak voltage

VQ,rating MOSFET rated voltage

VRRM Diode repetitive peak reverse voltage rating

Zj (j = 0, 1, 2, 3) Characteristic impedance

αd Delay angle

γ Circuit variable

θCb Power balancing capacitor voltage phase angle

ρ Dead time ratio in the gate drive circuit

φ1, φ2 Instantaneous fluxes in the two outer core legs

φ2,max Maximum flux in one outer core leg

φ2,min Minimum flux in one outer core leg

φc Instantaneous flux in the centre core leg

φle Leakage flux in the magnetic core

∆φ1, ∆φ2 Total changes of the fluxes in the two outer core legs

∆φ1,j (j = 1, 2, 3, 4) Change of flux in one outer core leg in each state

xxix

∆φ2,j (j = 1, 2, 3, 4) Change of flux in one outer core leg in each state

∆φc AC flux in the centre core leg

∆φc,j (j = 1, 2, 3, 4) Change of flux in the centre core leg in each state

(∆φ1)Q1,off Change of the flux in one outer core leg when Q1 is off

(∆φ1)Q1,on Change of the flux in one outer core leg when Q1 is on

(∆φ1)Q2,off Change of the flux in one outer core leg when Q2 is off

(∆φ1)Q2,on Change of the flux in one outer core leg when Q2 is on

Φ1, Φ2 DC fluxes in the two outer core legs

Φ20 Initial flux in one outer core leg

Φc DC flux in the centre core leg

∆1 Timing factor

ωgrid Grid angular frequency

ωj (j = 0, 1, 2, 3) Angular resonance frequency

ωCb Power balancing capacitor voltage angular frequency

xxx

LIST OF ACRONYMS

CSI Current Source Inverter

DF Dissipation Factor

DG Distributed Generation

EMI Electromagnetic Interference

EREC European Renewable Energy Council

ESR Equivalent Series Resistance

IEA International Energy Agency

IPT Interphase Transformer

KCL Kirchhoff’s Current Law

KVL Kirchhoff’s Voltage Law

LRC Load Resonant Converter

MIC Module Integrated Converter

MPPT Maximum Power Point Tracking

MRC Multi-Resonant Converters

MTBF Mean Time Between Failures

MTFF Mean Time to First Failure

NREL National Renewable Energy Laboratory

PCB Printed Circuit Board

PDM Pulse-Density Modulation

PFM Pulse-Frequency Modulation

PID Proportional-Integral-Derivative

PV Photovoltaic

xxxi

PVPS Photovoltaic Power Systems

PWM Pulse-Width Modulation

QRC Quasi-Resonant Converter

QSC Quasi-Square-Wave Converter

VSI Voltage Source Inverter

ZCS Zero-Current Switching

ZCT Zero-Current-Transition

ZVS Zero-Voltage Switching

ZVT Zero-Voltage-Transition

xxxii

ACKNOWLEDGEMENTS

I would like to express my thanks to the many people who have helped me to make

the completion of this thesis possible.

I wish to thank my supervisor, Professor Peter Wolfs, who has been my mentor and

role model for the past five years. His professionalism has made me a more mature

researcher over the years of my study.

Many thanks to my associate supervisor, Dr Steven Senini, who shares with me his

knowledge and personal experience in his doctoral study and offers me

encouragement.

Thanks also go to other staff members in the Faculty of Engineering and Physical

Systems at Central Queensland University. Numerous people have offered me their

generous help.

Finally, I would like to say a big thank you to my family members, who always

stand behind me and provide their best support.

xxxiii

DECLARATION

I hereby declare that the main text in this thesis is an original work of the author and

no part has been used in the award of another degree.

___________________

Quan Li

xxxiv

PUBLICATIONS

The following publications have been produced during the course of this thesis.

[i] P. Wolfs and Q. Li, “An Analysis of a Resonant Half Bridge Dual Converter

Operating in Continuous and Discontinuous Modes,” in Proceedings of 33rd

IEEE Power Electronics Specialists Conference, Cairns, Australia, June

2002, pp.1313-1318.

[ii] Q. Li, P. Wolfs and S. Senini, “A Hard Switched High Frequency Link

Converter with Constant Power Output for Photovoltaic Applications,” in

Proceedings of 29 Australasian Universities Power Engineering

Conference, Melbourne, Australia, September 2002.

th

[iii] Q. Li and P. Wolfs, “The Resonant Half Bridge Dual Converter with a

Resonant Gate Drive,” in Proceedings of 30th Australasian Universities

Power Engineering Conference, Christchurch, New Zealand, September

2003.

[iv] Q. Li and P. Wolfs, “Variable Frequency Control of the Resonant Half

Bridge Dual Converter,” in Proceedings of 30th Australasian Universities

Power Engineering Conference, Christchurch, New Zealand, September

2003.

[v] Q. Li and P. Wolfs, “The Resonant Half Bridge Dual Converter with a

Resonant Gate Drive,” Australian Journal of Electrical & Electronic

Engineering, Vol. 1, No. 3, pp.163-170, 2004.

xxxv

[vi] Q. Li and P. Wolfs, “The Optimization of a Resonant Two-Inductor Boost

Cell for a Photovoltaic Module Integrated Converter,” in Proceedings of 31st

Australasian Universities Power Engineering Conference, Brisbane,

Australia, September 2004.

[vii] Q. Li and P. Wolfs, “A Current Fed Two-Inductor Boost Converter for Grid

Interactive Photovoltaic Applications,” in Proceedings of 31st Australasian

Universities Power Engineering Conference, Brisbane, Australia, September

2004.

[viii] Q. Li and P. Wolfs, “The Analysis of the Power Loss in a Zero-Voltage

Switching Two-Inductor Boost Cell Operating under Different Circuit

Parameters,” in Proceedings of 20th IEEE Applied Power Electronics

Conference and Exposition, Austin, U.S.A., March 2005, pp.1851-1857.

[ix] Q. Li and P. Wolfs, “Variable Frequency Control of the Zero-Voltage

Switching Two-Inductor Boost Converter,” in Proceedings of 36th IEEE

Power Electronics Specialists Conference, Recife, Brazil, June 2005, pp.

667-673.

[x] Q. Li and P. Wolfs, “A Current Fed Two-Inductor Boost Converter with

Lossless Snubbing for Photovoltaic Module Integrated Converter

Applications,” in Proceedings of 36th IEEE Power Electronics Specialists

Conference, Recife, Brazil, June 2005, pp. 2111-2117.

[xi] Q. Li and P. Wolfs, “A Leakage-Inductance-Based ZVS Two-Inductor Boost

Converter with Integrated Magnetics,” IEEE Power Electronics Letters, Vol.

3, No. 2, pp. 67-71, June 2005.

xxxvi

[xii] Q. Li and P. Wolfs, “Analysis and Design of a Passive Lossless Snubber in

the Two-Inductor Boost Converter with a Variable Input Voltage,” in

Proceedings of 32nd Australasian Universities Power Engineering

Conference, Hobart, Australia, September 2005, pp. 521-526.

[xiii] Q. Li and P. Wolfs, “A Comparison of Three Magnetics Integration

Solutions for the Two-Inductor Boost Converter,” in Proceedings of 32nd

Australasian Universities Power Engineering Conference, Hobart, Australia,

September 2005, pp. 629-634.

[xiv] Q. Li and P. Wolfs, “Analysis, Design and Experimentation of a Zero-

Voltage Switching Two-Inductor Boost Converter with Integrated

Magnetics,” Proceedings of 37th IEEE Power Electronics Specialists

Conference, Jeju, Korea, June 2006, pp. 985-990.

[xv] Q. Li and P. Wolfs, “Recent Development in the Topologies for Photovoltaic

Module Integrated Converters,” Proceedings of 37th IEEE Power Electronics

Specialists Conference, Jeju, Korea, June 2006, pp. 3086-3093.

[xvi] Q. Li and P. Wolfs, “The Power Loss Optimisation of a Current Fed ZVS

Two-Inductor Boost Converter with a Resonant Transition Gate Drive,”

IEEE Transactions on Power Electronics, Vol. 21, No. 5, Sept. 2006.

[xvii] Q. Li and P. Wolfs, “A Current Fed Two-Inductor Boost Converter with an

Integrated Magnetic Structure and Passive Lossless Snubbers for

Photovoltaic Module Integrated Converter Applications,” IEEE Transactions

on Power Electronics, accepted.

xxxvii

[xviii] Q. Li and P. Wolfs, “An Analysis of the ZVS Two-Inductor Boost Converter

under Variable Frequency Operation,” IEEE Transactions on Power

Electronics, accepted.

1

1. INTRODUCTION

Photovoltaic (PV) sources are well established in the alternative energy market and

the total capacity of PV arrays each year is growing at an average rate of 26% per

annum [1]. Photovoltaics are still relatively expensive and continuing efforts are

required to drive down the costs of the solar cells and the support equipment. Power

conditioning elements such as inverters constitute a reasonable proportion of the

system cost. The inverter costs close to 20% of the total cost in a standard grid

interactive system [2]. As solar cell prices fall the balance of system costs become

more significant. This thesis attempts to make a contribution to the development of

the grid interactive inverter technology. Globally, the percentage of the grid

interactive PV systems has increased from 29% in 1992 to 83% in 2004 of the total

PV capacity installed among the 19 countries participating the International Energy

Agency Photovoltaic Power Systems Program (IEA PVPS) [2]. This thesis

concentrates on the study of the possible topologies based on the two-inductor boost

converter, that suit the applications in the Module Integrated Converter (MIC)

technology, one of the main streams in the grid interactive PV implementations.

It should be mentioned that the author had previously completed a Master of

Engineering thesis dealing with the two-inductor boost converter [3]. During that

study the basic resonant two-inductor boost converter topology was developed. It

became clear during that study that much more could be done to develop the

2

topology, our understanding of the topology and its application base. The thesis

content is briefly reviewed below.

Chapter 2 provides the literature survey. First the advantages of the grid interactive

PV systems over the stand alone PV systems are listed. Then, three popular

arrangements for grid interactive PV systems are briefly discussed. Among these, it

is shown that the MIC technology has the greatest potential in PV applications and

figures of merits of the state-of-the-art MICs are presented. It is shown that MIC

implementations with high frequency transformers can be classified into three

topologies and their main advantages and disadvantages are briefly explained. A

comprehensive set of the proposed converters are also listed for each MIC topology.

Chapter 3 presents the research opportunities for the two-inductor boost converter.

First, the power balance issue in the MIC implementations is discussed. In order to

deal with the 100-Hz power ripple in the MICs, three possible solutions for

capacitive energy storage are considered in the MIC design. Then recent research

interests in the two-inductor boost converter are summarised and possible variations

of the two-inductor boost converter for the three MIC topologies are provided at the

end of the chapter.

Chapter 4 concentrates on the study of the soft-switched two-inductor boost

converter as a dc-dc conversion stage in a MIC with an intermediate constant dc

link. By varying the three circuit parameters in the resonant two-inductor boost

converter, a wide load range can be achieved under the variable frequency control

3

while the resonant condition can be maintained. In order to obtain a wider load

range without the penalty of the high switch voltage stress, a soft-switched two-

inductor boost converter with the voltage clamp is also developed. In both of the

converters, the sets of the design equations and the control functions are explicitly

established. Finally in the chapter, the power loss components in the soft-switched

two-inductor boost converter are investigated. Under a specified load condition, the

power loss in the converter varies with different circuit parameters and the set of the

variable loss components are identified. In order to minimise the power loss in the

soft-switched two-inductor boost converter, an optimised operating point can be

numerically established.

Although the two-inductor boost topology has many advantages over other boost

topologies, one significant disadvantage of this topology is the requirement of the

three separate magnetic devices. Therefore, Chapter 5 studies the magnetic

integration solutions in the two-inductor boost converter. Four integrated magnetic

structures can be developed using both of the magnetic core integration and the

winding integration methods. All four integrated magnetic structures are thoroughly

investigated in the hard-switched two-inductor boost converter applications and the

equivalent input and transformer magnetising inductances, the dc gain, the dc and ac

flux densities and the current ripples in the individual windings are solved. One

specific integrated magnetic structure, which presents a potential high transformer

leakage inductance, is applied to the soft-switched two-inductor boost converter and

the converter operation is also discussed in detail.

4

Chapter 6 presents the current fed two-inductor boost converter as the dc-dc

conversion stage in the MIC topologies with an unfolding stage. In both of the hard-

switched and the soft-switched arrangements, a sinusoidally modulated two-phase

synchronous buck converter functions as the current source to the two-inductor

boost cell. The hard-switched current fed two-inductor boost converter features the

integrated magnetics, the non-dissipative snubbers, the silicon carbide rectifiers and

the electrically isolated optical MOSFET drivers to achieve an overall compact

design with a high efficiency. Among these technologies, a detailed analysis is

provided for different operation modes of the non-dissipative snubbers. In the soft-

switched arrangement, the buck conversion and unfolding stages are the same as

those in the hard-switched arrangement. In the two-inductor boost cell, an optimised

operating point is employed to minimise the power loss in the boost stage converter.

In order to reduce the drive power loss with the conventional gate drive circuit, a

resonant transition gate drive circuit is developed for the two-inductor boost cell and

a detailed analysis is also provided.

Chapter 7 develops the two-inductor boost converter with a frequency changer for

the third MIC topology. In this arrangement, the rectification stage of the original

two-inductor boost converter is removed and a frequency changer is utilised to

convert the high frequency ac current directly to the ac voltage of the grid frequency.

Besides the simplicity of the circuit arrangement and the reduced component count,

a significant advantage of this converter is the constant power output achieved by a

small non-polarised capacitor used in the load.

5

Chapter 8 provides the conclusions for the thesis. The thesis has made a significant

contribution to the understanding of the two-inductor boost converter. Original

contributions have been made in the analysis of the resonant version of the converter

that was first proposed by the author during his Master of Engineering studies. A

new resonant transition gate drive circuit is presented for this topology. An

extensive study has been made of loss optimised current fed resonant converter cells

and of current fed hard-switched cells with non-dissipative snubbers. Novel

contributions have also been made in the integrated magnetics of the converter and

in the development of a frequency-changer-based MIC topology.

The conclusion also points out that the resonant converter approaches can be readily

extended to variations of the two-inductor boost converter proposed by other

researchers. This is a promising area of future research.

6

2. LITERATURE SURVEY

Humans first drew upon the natural world for their supply of energy by utilising

largely renewable sources. Fire, fuelled by biomass, water and wind mills and solar

heat for drying were key resources for the ancient world. Since the industrial

revolution fossil fuels have become key energy sources. We have come to learn that

these sources are finite and that the impacts on the environment are, at the very least,

troublesome. Internationally there has been significant interest in revisiting the use

of renewable resources. Assuming that the significant favourable measures are

adopted internationally and unanimously, the European Renewable Energy Council

(EREC) has projected a best scenario where 47.7% of the total energy consumption

worldwide in 2040 will come from the renewable energy resources [4].

Distributed Generation (DG) has been a focus in the current electric power system

research and the applications of the renewable energy resources are well suited to

this concept [5]. Among a variety of the renewable energy resources, PV energy has

no source limitations and thus has received more and more attention since the first

solar cell was developed at Bell Laboratories in 1954 and patented in 1957 [6]. The

efficiency of the solar cells has also greatly improved over many years of research.

For example, the efficiency of the triple junction GaInP/GaAs/Ge solar cells for

space applications has reached 28.0% [7]. A record-breaking 20.3% efficiency has

also been claimed for multicrystalline silicon solar cells, which account for 55% of

all solar cell production worldwide [8], [9]. The annual world PV cell/module

7

production between 1988 and 2005 is shown in Figure 2.1 and it has reached 1727

MW in 2005, representing a growth of 45% over 2004 [10]. According to the EREC

report, PV energy will generate 25.1% of the total electricity consumption in 2040

and become the biggest contributor among all renewable energy candidates [4].

0

200

400

600

800

1000

1200

1400

1600

1800

1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005Year

Wor

ld P

V C

ell/M

odul

e P

rodu

ctio

n (M

W)

Figure 2.1 World PV Cell/Module Production (1988-2005)

2.1 Stand Alone versus Grid Interactive Systems

PV systems can be classified as two different categories – the stand alone system

and the grid interactive system. Compared with the stand alone system, the grid

interactive system has the following three advantages due to the absence of the

storage battery [11]:

• Reduced cost,

8

• Improved efficiency, and

• Extended lifetime.

Grid interactive PV, while being proposed at least as early as 1974 [12], only now

has the fastest growing rate in the world PV market and has started to play the

dominant role. In 2004, the cumulative installed capacity of grid interactive PV

systems has reached 2155 MW among the 19 countries participating the IEA PVPS,

who account for over three quarters of the global PV production [2].

2.2 Possible Arrangements for Grid Interactive Systems

To date, there are three widely used arrangements for grid interactive PV systems –

the central converter technology, the string converter technology and the MIC

technology [13]-[17].

Figure 2.2 shows the grid interactive PV system with a central converter. Multiple

PV modules are connected in parallel and/or in series and they feed the dc power to

a central inverter. This technology is plant-oriented and the power rating of the

central converter can be up to several Megawatts [14]. However, the central

converter technology has the following main disadvantages:

• The dc cabling design is complex [18],

• The central converter must be individually designed [17],

9

• Maximum Power Point Tracking (MPPT) cannot be applied to individual PV

modules [18],

• The output power decreases due to module mismatching and partial shading

conditions [16], [19], and

• The reliability of the PV plant is limited due to the dependence of one single

converter [16].

Three Phase Mains

DC-ACInverter

PVModule

Figure 2.2 Central Converter Technology

Figure 2.3 shows the grid interactive PV system with string converters. PV modules

are connected only in series to provide a high dc voltage to the string converter and

multiple string converters can be connected in parallel on the ac side. This

technology is module-oriented and the power rating of the string converter can be up

to 2 kW [14]. Although MPPT is relatively flexible and can be applied to each

string converter, high dc voltage is still present in this technology [17].

10

DC-ACInverter

PVModule

Three Phase Mains

Figure 2.3 String Converter Technology

Figure 2.4 shows the grid interactive PV system with MICs. MIC, together with the

PV module, is called ‘AC Module’. Although the first ac module inverter was only

developed by the Centre for Solar Energy and Hydrogen Research (ZSW) in

Germany in 1992 [20], this concept was proposed as early as in 1970’s at Caltech’s

Jet Propulsion Laboratory [21]. The AC Module can be defined as below [22]:

An AC Module is an electrical product and is the combination of a single module

and a single power electronic inverter that converts light into electrical alternating

(ac) power when it is connected in parallel to the network. The inverter is mounted

11

on the rear side of the module or is mounted on the support structure and connected

to the module with a single point to point dc-cable. Protection functions for the ac

side (e.g. voltage and frequency) are integrated in the electronic control of the

inverter.

Mains

DC-ACInverter

PVModule

Figure 2.4 MIC Technology

The definition of AC Module implies that there is only one PV module per dc-ac

converter. Therefore MICs have small power ratings, typically less than 500 watts-

peak [15], depending on the size of the PV modules. Compared with the centre and

the string converter technologies, the MIC technology has the following main

advantages:

• DC cabling can be avoided [13],

12

• The system size can be minimised [21],

• MPPT can be applied to each PV module [23],

• The PV system can be easily expanded [24], and

• ‘Plug and Play’ concept can be realised [25].

Although the cost of the MICs on a per watt basis maybe higher than that of the

other two existing technologies, MIC technology is believed to have a brighter

future considering the system installation cost, performance and reliability and lead

to a grid interactive PV system with the minimum cost and the maximum efficiency

[26]. AC Module is a universal building block in grid interactive PV applications

[27], especially in Building Integrated Photovoltaics (BIPV), which has become a

popular way to use PV energy recently [28]-[30], and requires easy and safe

installation, as well as easy expandability [31].

2.3 Figures of Merits of State-of-the-Art MICs

All power electronic designs are governed by the following goal [32]:

The goal of power electronics is to control the flow of energy from an electrical

source to an electrical load with high efficiency, high availability, high reliability,

small size, light weight, and low cost.

The performance of the grid interactive PV systems heavily relies on the

performance of the MIC. To be consistent with the goal of power electronics, it is

13

required that the MICs have the following characteristics:

• Compactness,

• High efficiency,

• High reliability or long lifetime, and

• Reasonable cost.

Some of the parameters of the commercially available MICs are listed in Appendix.

The following sections will provide some of the figures of merits that the state-of-

the-art MICs have achieved.

2.3.1 Power Density

The compactness of a MIC can be determined by its power density. The density is

the rated power related to the volume of the converter [33]. Although the power

densities of the commercially available ac module inverters are still relatively low, a

prototype MIC with an output power of 110 W has been reported to achieve a power

density of 0.6 W/cm3, with the windings of all magnetic components integrated into

the Printed Circuit Board (PCB) [34]. In addition to the high power density, “low

profile” is also preferable in the MIC design as some MIC installations cannot

accomodate the increase of the height of the solar module frame [35]. With the

emerging technologies of integrating passive components, power semiconductors,

driver circuits and signal processing devices into the PCB, the power density of

MICs will be further improved in the future [36]. The prediction of the size of a

14

reported next generation inverter of 300 W is 2070220 ×× mm [31]. This gives an

equivalent power density of 0.97 W/cm3.

2.3.2 Efficiency

In a highly compact MIC, a high efficiency allows the bulky heat sinks to be

removed from the system. However, compared with larger inverters, MICs have

smaller power ratings and tend to have lower efficiencies [37]. In 1997, a

commercially available MIC of 100 watts-peak, OK4-100, manufactured by NKF

Electronics in the Netherlands, was reported to achieve an efficiency of 94% at 40%

of the maximum input power [38]. This figure is still the best of what has been

commercially achieved today [15]. The efficiencies of the future MICs target at the

range above 95% to further decrease the temperature stress and increase the lifetime

of the devices [31].

2.3.3 Mean Time Between Failures and Mean Time to First Failure

Because MICs are mounted on the PV module, it is important that the lifetime of the

MIC is comparable to that of the PV module, which lasts more than 20 years [27].

However, inverters are still shown to be the most vulnerable component in PV

systems [39]. At least two parameters can be used in measuring the MIC’s

reliability. One parameter is Mean Time Between Failures (MTBF). While the

average of MTBF of the inverters surveyed among the 11 of the IEA member

countries is 10 years [39], the second prototype PV2GO inverter is estimated to have

15

an MTBF of about 25 years [40]. The other parameter is Mean Time to First Failure

(MTFF). Currently, most of PV converters which have been reviewed in US have

an MTFF of less than five years [41], although some PV converters are claimed to

have over 20 years of lifetime [42], [43]. An MTFF of 10 years has been proposed

for the next generation PV inverters by employing the potential new technologies

[44]. It is worth mentioning that in improving the MIC reliability, “low profile” is

also a very desirable feature as it results in a lower operating temperature of the

converter and every 10 K temperature decrease leads to a lifetime increase of 100%

[34]. An experiment has shown that the internal temperature of the MIC can be

reduced up to 10.5 K by reducing the height of the MIC from 30 mm to 15 mm [35].

2.3.4 Balance of System Cost

Balance of System (BOS) is defined as the parts of the photovoltaic system other

than the PV array including switches, controls, meters, power conditioning

equipment, supporting structure for the array and storage components, if any [45].

BOS cost is another important figure of merit for the MIC Technology and its major

component is the cost of MICs due to the absence of the storage batteries. Over a

decade, the cost of crystalline PV modules has declined from $4.23 US per watt to

$1.72 US per watt in 2002, according to the latest survey of the US Department of

Energy’s National Renewable Energy Laboratory (NREL) [46]. This significant

drop in PV modules has made the cost of the MICs more visible in the total system

cost [25]. Generally MICs with higher power ratings are less expensive in their unit

price per watt than those with lower power ratings. In 1997 it was reported that

16

OK4-100 had achieved a price below $1 US per watt-peak [38]. This price seems to

be the lowest achievable for MICs over many years [14]. A recent estimation of the

PV2GO inverter based on the annual production of 10,000 units shows that €0.5 per

watt-peak is possible, representing a significant price drop [40]. Although the price

of the MICs are still uncompetitive with that of the central converters, the cost of the

PV systems with MICs may be not significantly higher than that with the central

converters considering the additional cables and the installation cost [47].

Moreover, MICs can take the advantages of small-scale converters and have a

greater potential in cost reduction when mass produced [36]. The objective of

dropping the cost of the MICs to below $0.5 US per watt-peak, which was set more

than a decade ago, is still to be achieved [13].

2.4 Possible MIC Topologies

Because the most common individual PV module nowadays supplies low dc

voltages [48], a MIC is required to provide two functions – boosting the input

voltage to a higher voltage level, which needs to be compatible with the grid

voltage, and transforming the input voltage to an ac waveform of the grid frequency,

which is ideally sinusoidal.

In the MIC implementations, transformers are preferred for the voltage amplification

and as well the electrical isolation between the PV module and the grid. The

presence of the transformer results in a multiple-stage power conversion process.

Generally, a multiple-stage MIC with a transformer can be implemented in two

17

ways, which are respectively shown in Figures 2.5 and 2.6.

Line Frequency Transformer

DC-ACInverter

Figure 2.5 MIC with a Line Frequency Transformer

Converter 1 Converter 2High Frequency Transformer

Figure 2.6 MIC with a High Frequency Transformer

In Figure 2.5, the dc-ac inversion is implemented first, followed by the voltage

boosting. An inverter transforms the dc voltage to the ac voltage and then a line

frequency transformer is used to boost the output of the inverter to a grid compatible

level. The advantage of using a low frequency transformer is that MOSFETs with

low voltage ratings can be used for the inverter [15]. However, one major

disadvantage is that the line frequency transformer is always large in volume and

heavy in weight and this is not consistent with the target of the MIC’s compactness.

The other disadvantage is that a low-power line-frequency transformer of is not very

efficient [49]. Therefore, this solution is regarded as a poor solution and will not be

18

further discussed in the thesis [25].

In Figure 2.6, the voltage boosting is implemented first, followed by the dc-ac

inversion. The dc voltage is first transformed to a high frequency ac voltage and

boosted by a high frequency transformer to a higher level. Then the high frequency

ac voltage is converted to the low frequency grid compatible ac voltage. Compared

with the low frequency transformer in Figure 2.5, the high frequency transformer is

much smaller in volume and lighter in weight. Along with the development of

semiconductor technologies, MOSFETs with higher ratings are more easily

available [50]. This allows the arrangement with high frequency transformers to

become a trend for MIC implementations.

Theoretically, a variety of the isolated dc-dc converter topologies can be used in

boosting the voltage level including the half bridge converter, the full bridge

converter, the forward converter, the flyback converter, the push-pull converter and

the two-inductor boost converter, as shown in Figure 2.7. Practically, the

rectification stage in these dc-dc converters may not be needed when an intermediate

dc link is removed from the power conversion process. In the MIC implementations

with more than two stages of the power conversion, a cascade of one of these

converters and a non-isolated dc-dc converter such as a buck or a boost converter

can be used in the voltage boosting stage.

MICs with high frequency transformers can be technically categorised into three

topologies and they will be discussed in the following sections.

19

E

Q1

Q2

C1

C2

R VO

D2

D3 D4

D1

L

−

+T T

(a) (b)

E

Q1

Q4

TQ2

Q3

R VO

D2

D3 D4

D1

L

−

+T

(c)

E

Q1

RD2

D1 L

D3 CO

T

(d)

E

Q1

R

D1

CO

T

Lm

VO

−

+VO

−

+

(e)

EQ1 Q2 R

L

D1

D4D3

D2

T T

TVO

−

+

(f)

D4D3

CO

T T

L1 L2

Q1 Q2

D1D2

R VO

−

+

E

Figure 2.7 Isolated DC-DC Converters

(a) Half Bridge Converter (b) Full Bridge Converter (c) Forward Converter

(d) Flyback Converter (e) Push-Pull Converter (f) Two-Inductor Boost Converter

2.4.1 MIC with an Intermediate Constant DC Link

Figure 2.8 shows the MIC with an intermediate constant dc link. In this topology,

the low input dc voltage from the PV module is first translated to a dc voltage of the

ac grid level on the dc link by an isolated dc-dc converter and then fed to a self-

commutated dc-ac inverter, which is normally a pulse-width modulated full bridge

20

inverter, to produce the ac voltage. Several topologies with an intermediate constant

dc link have been proposed [51], [52].

DC-ACInverter

High Frequency Transformer

DCLink

DC-DCConverter

Figure 2.8 MIC with an Intermediate Constant DC Link

The topology proposed in [51] is shown in Figure 2.9, where the exact dc-dc

converter topology was not mentioned. A Zero-Voltage-Transition (ZVT) pulse-

width modulated inverter is employed in this topology. The soft-switched inverter

removes the switching losses which would otherwise be inherent with the

conventional hard-switching Pulse-Width Modulation (PWM).

ELa

Q1

Q2

Q3

Q4

Lb

Qa Qb DC-DCConverter

Figure 2.9 Topology Proposed in [51]

21

The topology proposed in [52] is shown in Figure 2.10. The dc-dc conversion stage

employs the series resonant half bridge topology to remove the switching losses.

The dc-ac inverter is a modified full bridge inverter, with two additional diodes.

The left leg switches operate at high frequencies to control the current injected to the

grid while the right leg switches are controlled by the polarity of the grid voltage and

switch synchronously with the zero crossings of the grid voltage. This control

approach might allow the switching loss in the inverter to be reduced compared with

that in the conventional hard-switched PWM inverter. However, this bridge does

have less modulation range opportunities. A conventional bridge can achieve

frequency doubling by applying phase shifted switching control between the bridge

legs.

E

Q1

Q2

Q5

Q6

Q3

Q4

Lf

Cf

Cr T T

D1

D4D3

D2


In order to meet the requirements of the MIC, a never-ending effort has been made

to minimise the size of the dc-dc converter and increasing the switching frequency

has been proved to be one of the solutions. However, an obvious penalty of the

increased switching frequency is the reduced efficiency due to the increased

switching loss. Over the years, many soft-switching technologies including the

22

snubber circuits, the resonant converters and the soft-switching PWM converters

have evolved to combat high switching loss at high switching frequencies.

Two classes of the snubber circuits – the dissipative snubbers and the non-

dissipative or lossless snubbers – have been well developed since the concept was

reported in 1976 [53]. While the dissipative snubbers are able to reduce the

switching loss, their major role is to reduce the voltage and the current stresses by

reshaping the switching loci of the semiconductor switches [54]. The lossless

snubbers are capable of recovering the switching energy to the converter input or

output and they can be implemented by either the passive or the active methods. In

the passive method, additional components such as inductors and capacitors are

added to the snubber circuit of the hard-switched converter and the soft-switching

can be achieved. In the active method, an extra semiconductor switch is required in

addition to the inductors and the capacitors to achieve the soft-switching. Recently,

the passive lossless snubbers have been recognised as better alternatives to the active

lossless snubbers as they are less expensive and have higher reliability [55].

Resonant converter technology alters the PWM technique in the conventional hard-

switched dc-dc converter by placing resonant inductors and capacitors in the circuit.

The main categories of the resonant converters are Load Resonant Converters

(LRCs), Quasi-Resonant Converters (QRCs) and Multi-Resonant Converters

(MRCs). The current and the voltage waveforms in the resonant converters are in

either sinusoidal or quasi-sinusoidal form, allowing the switching semiconductors to

turn on or off at zero current or zero voltage. According to different switching

23

conditions, resonant converters can be classified as Zero-Voltage Switching (ZVS)

converters and Zero-Current Switching (ZCS) converters [56]. Minor modifications

of the converter topologies shown in Figure 2.7 can lead to the corresponding

resonant converter topologies, which result in reduced switching losses and higher

overall converter efficiencies when applied in PV applications [57].

The soft-switching PWM converters are defined here as the converters that combine

both of the PWM and the resonant principles. The driving force to develop this new

technology is that all resonant converters suffer from inherent drawbacks due to the

resonant nature of the current and the voltage waveforms – higher current and

voltage stresses in the switches, which lead to higher conduction losses. In this

technology, the converter operates as a resonant converter only during the switching

transitions and operates as a normal PWM converter during the rest of the time.

Therefore, the resonant components hardly participate in the primary power

processing and the high switch current or voltage stress is absent in this type of

converter. Topologically, the soft-switching PWM technology can be classified as

an active lossless snubber technology. But the operating principle during the switch

transition period is based on the resonant technology therefore it is best classified as

a separate approach. The main categories of the soft-switching PWM technology

are ZVS or ZCS Quasi-Square-Wave Converters (QSCs), ZVS-PWM Converters or

ZCS-PWM Converters and Zero-Voltage-Transition (ZVT) or Zero-Current-

Transition (ZCT) Converters. However, the converters of each category have their

own disadvantages such as high current or voltage stress across the switches,

inability to absorb the transformer leakage inductance into the resonant tank and

24

hard-switching condition of the additional switch [58]. Continuous efforts have

been reported to overcome some of these disadvantages. For example, variations of

ZVT converters have been developed to realise soft-switching conditions for the

additional switch to improve the overall efficiency [59]-[61].

The main advantage of this two-stage PV energy conversion system is the ease in

the design of the control scheme. The dc-dc converter may be controlled to track the

maximum power point of the PV module and the dc-ac inverter may be controlled to

produce ac power of the unity power factor. Because the controllers of the

individual stages have independent goals and architectures, they are relatively easy

to design [62]. However, when only the hard-switching technique is used, a major

drawback of this arrangement is the high switching losses as the switching devices

in both conversion stages switch at high frequencies.

2.4.2 MIC with an Unfolding Stage

Figure 2.11 shows the MIC with an unfolding stage. In this topology, the link

between the dc-dc conversion stage and the unfolding stage may be called a pseudo

dc link as it no longer provides a constant dc voltage. The dc-dc converter in this

system is able to produce the output voltage in a wide range and a rectified

sinusoidal waveform is formed as the input to the grid-commutated dc-ac inverter.

The square-wave control technique is applied to the dc-ac inverter and the inverter is

reduced to an unfolder to generate the sinusoidal waveform. As this arrangement

does not suffer the penalty of the high switching losses in the dc-ac inversion stage,

25

many topologies have been proposed [63]-[67].

Mains FrequencyUnfolder


Figure 2.11 MIC with an Unfolding Stage

The topology proposed in [63] is shown in Figure 2.12. In this topology, the dc-dc

conversion is implemented by the cascade of a boost converter and a push-pull

converter. The boost converter is used to boost the low input voltage to a higher

level and the push-pull converter is modulated to provide a rectified sinusoidal

current. The following Current Source Inverter (CSI) switches at the line frequency

to generate the sinusoidal current.

E Q1

Q5

Q7

Q4

Q6

T

D2

D5D4

D3

Q2 Q3

T TD1L1 L2


The topology proposed in [64] includes three stages and is shown in Figure 2.13.

26

The first stage is a current fed push-pull converter, which boosts the dc voltage. In

the second stage, a buck converter is used to generate a rectified sinusoidal

waveform and transform the voltage source to the current source. The last stage is

still a CSI, which unfolds the rectified sinusoidal current.

E

Q5

Q7

Q4

Q6

D1 L2Q1

Lf

Q2

L1

D2

Q3

D3

D4

D7

D5

D6

T

Cf


The topology proposed in [65] is based on the topology in [57] and shown in Figure

2.14. The dc-dc conversion stage employs the series-parallel resonant full bridge

converter equipped with lossless snubbers and generates the rectified sinusoidal

waveform. This arrangement combines the load-dependent characteristic of the

series resonant converter and the capability of operating at very light load of the

parallel resonant converter. A CSI follows to function as an unfolder.

A topology based on the cascade of the buck-boost and the flyback converter is

proposed in [66] and further improved in [67]. The topologies are respectively

shown in Figures 2.15 and 2.16. In both topologies, the energy is first transferred to

27

the transformer magnetising inductance through the buck-boost switch and then

transferred to the intermediate capacitor through the flyback switch. Finally, the

energy in the transformer magnetising inductance and the intermediate capacitor is

transferred to the output grid through the centre-tapped transformer and the two ac

switches. The improved version in [67] is able to recover the energy stored in the

transformer leakage inductance into the intermediate capacitor. The major

advantage of this topology is claimed to be the requirement of a small intermediate

capacitance.

E

Q1

Q3

Q6

Q8

Q5

Q7

Cr T T

D1

D4D3

D2

Lr

Ct

Q2

Q4Cs1 Cs2


E

Qflyback

Qbuck-boost

Lf

Cf

QAC1

QAC2

T


28

E

Qflyback1

Qflyback2

Lf

Cf

QAC1

QAC2

Qsynchronous

Qbuck-boost

T


A topology based on the ZVT flyback converter is proposed in [68] and shown in

Figure 2.17. This topology is similar to that in [66] but the auxiliary switch is used

to achieve the ZVT.

E

Qa

Qm

Lf

Cf

Qp

Qn

T

Cr

Cm


29

Some inverter topologies with an unfolding stage are originally proposed for PV

applications with higher power ratings but could be possibly applied to the MIC

implementations [69], [70].

The topology proposed in [69] is shown in Figure 2.18. It consists of a high

frequency full bridge dc-dc converter and a line frequency full bridge dc-ac inverter.

The dc-dc converter is modulated to generate the rectified sinusoidal waveform and

this is unfolded by the following CSI.

E

Q1

Q3

Q6

Q8

Q5

Q7

T T

D1

D4D3

D2Q2

Q4

D5


The topology proposed in [70] is based on the flyback converter and shown in

Figure 2.19. A rectified sinusoidal current is generated after the dc-dc conversion

stage and a CSI follows.

A multiple-stage MIC topology with an unfolding stage can be also implemented

without a transformer. This arrangement undoubtedly offers space and cost saving

designs compared with their counterparts utilising transformers [71]. The

transformerless topologies normally consist of the cascade of a non-isolated dc-dc

30

converter with the voltage boosting characteristic and a dc-ac inverter. Several

proposed transformerless topologies are invariably based on the buck boost

converter, which is modulated to generate the rectified sinusoidal current [70], [72]-

[75]. A CSI follows, operating at the line frequency, to generate the grid frequency

sinusoidal current waveform. These topologies are respectively shown in Figures

2.20 to 2.23.

E

Q3

Q5

Q2

Q4D1

L2Q1


E

Q4

Q6

Q3

Q5

D2

D1 Q2

L2

Q1

L1

Figure 2.20 Topology Proposed in [70] and [72]

31

E

Q1

Q3

Q5

Q2

Q4

Lf

Cf2Cf1L


E

Q1

Q4

Q6

Q3

Q5

L2

Q2

L1


E

Q5

Q7

Q4

Q6

L2

L1

Q1

Q2

Q3

Cf

ZL


32

Further pursuance in the size reduction of the MICs leads to the single-stage

converter topologies, which are able to accomplish the power conversion in one

single stage. These single-stage topologies generally consist of two relatively

independent converters, with some passive components shared if possible, and the

individual converters produce half cycle sinusoidal waveforms 180° out of phase.

The topologies proposed in [76]-[80] are based on the buck-boost converter and

respectively shown in Figures 2.24 to 2.26.

E Cf

LQ1

Q2

Q3

Q4

Q6

Lf

n2L

Q5

C ZL


E Cf

Q1

Q2

Q3

Q4 Q6

LfQ5

ZLL

Figure 2.25 Topology Proposed in [77] and [78]

33

E1

Q1

Q3 Q4

L1

E2

Q2

L2

C

Figure 2.26 The Topology Proposed in [79] and [80]

The topologies proposed in [81]-[84] are based on the Cuk converter, the Zeta

converter or the D2 converter and are shown in Figure 2.27. The first two

topologies can be easily transformed to the isolated versions based on the isolated

Cuk and Zeta converters. Practically, only one of the output filter inductors L2 and

L4 is needed.

The topology proposed in [85] is based on the combination of the Cuk converter and

the Zeta converter and shown in Figure 2.28.

The topology proposed in [86] is based on the flyback converter and shown in

Figure 2.29.

34

Q1 Q2 Q3Q4

L3L4

L1L2

(a)

E

Q1

Q2

Q3

Q4 L3

L4

L1

L2

(b)

E

Q1

Q2 Q4

L3

L4

L1

L2

(c)

E

Q3

Figure 2.27 Topologies Proposed in [81]-[84]

(a) Cuk-Based Converter (b) Zeta-Based Converter (c) D2-Based Converter

35

E

Q1

L1

L2

Q4Q2

Q3

Q5

Q6

Q7

Q8


E

L

Q1 Q2 Q3Q4

T1 T2


Some inverter topologies with the voltage boosting feature also have potential

applications in the single-stage MIC implementations although they are not

originally proposed for PV inverter applications [87]-[89]. The boost inverter

proposed in [87] is shown in Figure 2.30. The buck boost inverter proposed in [88]

is shown in Figure 2.31. The ZCS buck boost inverter proposed in [89] is shown

Figure 2.32.

36

Q2

Q4

Q1

Q3E

L1 L2

+ −

R

vO

C1 C2


Q2

Q4

Q1

Q3

E

L1 L2

+ −

R

vO

C1 C2


Q2

Q4

Q1

Q3

Lr1 Lr2

E

Cr Cf

+

−R vO

Lf


37

Although the single-stage inverters are claimed to be suitable for MIC applications,

as these topologies have to accomplish the two functions including the voltage

amplification and the dc-ac inversion in one single stage, their minimum component

counts and power losses are obtained at the cost of the limited power capacity, the

compromised output quality and the limited operation range imposed to dc sources

[90], [91]. The transformerless topologies also suffer a limited voltage gain due to

the absence of the transformer and are unlikely to convert the voltage of a 36-cell

PV module to the voltage compatible with the grid voltage higher than 200 V.

Another issue related to the transformerless topologies is the dual grounding, which

can be easily dealt with in the topologies galvanically isolated with a high frequency

transformer. Therefore, a multiple-stage topology with the electrical isolation

through a high frequency transformer is often deemed as a better solution.

In the topology with an unfolding stage, special attention has to be paid if the quasi-

resonant or multi-resonant dc-dc converters are modulated to generate the rectified

sinusoidal waveform. As the switch on or off time in these resonant dc-dc

converters is completely determined by the resonant elements and the input and the

load conditions, they usually cannot maintain the soft-switching condition over a

wide load range. In order to maintain the resonant condition under a wide load

range, two modulation techniques can be used:

• Pulse-Frequency Modulation (PFM), and

• Pulse-Density Modulation (PDM).

38

In PFM, the variable frequency control is used and the switching frequency must be

adjusted to cater for different load conditions. This control technique makes the

optimal design of the input or the output filter, the control circuit and the magnetic

components in the converter very difficult [92]. The other option is the constant

frequency control [93]. In order to achieve the constant switching frequency

operation, the characteristic frequency of the resonant tank in the converter must be

varied according to different load conditions. A popular solution is to embed

additional switches in the resonant tank to achieve the switch-controlled inductor or

capacitor [94].

PDM can also be used to maintain the resonant condition over a wide load range. In

particular, Area-Comparison PDM has been used to synthesise low frequency and dc

voltage and current outputs from high frequency link [95], [96]. In this method, the

density of the high frequency pulses is proportional to the amplitude of the output

voltage or current and the resonant converter can always operate under ZVS or ZCS

condition.

Soft-switching PWM converters combining the PWM and the resonant principles

are capable of maintaining the soft-switching condition over a wide load range [97].

Constant frequency control can be applied as an extra switch is used in the converter

to offer another degree of freedom. ZVS QSCs replace the diode rectifier in their

QRC counterparts with the controllable rectifier to achieve the constant frequency

operation [98]. ZVS-PWM converters add an additional switch to their QRC

counterparts to introduce a freewheeling stage in the operation of the converter [99].

39

The output power of the resonant converter can then be controlled by adjusting the

length of this freewheeling period. ZVT converters use a parallel resonant network

across the switch and the constant frequency operation can be realised by only

activating this network during the switch transition period [59].

The major advantage of the MIC implementations with an unfolding stage is that the

dc-ac inverter operates at the line frequency and the switching loss in the inversion

stage is minimised. A high overall conversion efficiency is likely to be achieved in

this arrangement even with a hard-switched dc-ac inversion stage.

2.4.3 MIC with a Frequency Changer

Figure 2.33 shows the MIC with a frequency changer. This topology can be

obtained by eliminating the rectification stage and the intermediate dc link of the

topology shown in Figure 2.8. The low dc input voltage from the PV module is first

translated to a high frequency ac voltage or current and then boosted and converted

to the ac voltage or current of the grid frequency directly through a frequency

changer. Any kinds of the intermediate power storage stage between the high

frequency pulse and the grid ac voltage are absent in this topology.

The frequency changer used here can be classified as one type of ac-ac converters –

the ac-ac converters with direct link [100], as it has no energy storage devices in

between the two ac ports. In the PV applications, the frequency changer is required

to transform the ac power of the high frequency down to that of the grid frequency.

40

The possible solutions of the ac-ac converters with direct link are the

cycloconverters and the matrix converters [101], [102]. Generally, these converters

require bi-directional switches capable of blocking voltage and conducting current in

both directions. However, the bi-directional switches are not commercially

available currently and must be constructed with the uni-directional switches. An

example using IGBTs in three arrangements is shown in Figure 2.34 [103].

Frequency Changer


Figure 2.33 MIC with a Frequency Changer

(a) (b) (c)

Figure 2.34 Bi-Directional Switches

(a) Diode Bridge (b) Common Emitter Back to Back

(c) Common Collector Back to Back

41

Two topologies of the MIC with a frequency changer have been proposed [104],

[105].

The topology proposed in [104] is shown in Figure 2.35. The first stage is a Voltage

Source Inverter (VSI), which transforms the dc voltage to the high frequency ac

voltage. Then an impedance-admittance conversion circuit is used to convert the

voltage source to the current source. In the third stage, a cycloconverter, modulated

by the line frequency sinusoidal waveform, injects the sinusoidal current into the

grid.

E

Q23

Q13

Q14

Q11

Q12

Lf

Cf

Q21

Q24 Q22


The topology proposed in [105] includes two stages and is shown in Figure 2.36.

The first stage is a push-pull converter and generates high frequency ac waveforms

in the transformer. A cycloconverter made up of bi-directional switches then

transforms this high frequency ac voltage to the ac voltage of the grid frequency.

42

Q23 Lf3

Cf

Q21

Q24 Q22

E

Q1

Q2

Lf2

Lf1


Two other topologies with a frequency changer have been proposed for the PV

inverters with power ratings in the kilowatt range and they are shown in Figures 2.37

and 2.38 [106], [107]. They both include two stages – a full bridge inverter

followed by a cycloconverter. Theoretically, these topologies can be also applied to

the MIC implementations, where the standard power rating is less than 500 W.

E

Q2

Q4

Q1

Q3

Q7

Q8

Q5

Q6

Ds

Cs

Rs

Q10

Q9


43

E

Q2

Q4

Q1

Q3

Q21Q11

Q31 Q41

Q12Q22

Q42Q32

ZL


The main advantage of a frequency-changer-based MIC is the reduction in the

number of power conversion stages to two. This opens the possibility of higher

efficiency and lower part count. These are obtained at the cost of more sophisticated

and higher bandwidth controls. The need for bi-directional switches is a

complication that can undermine the possible efficiency and part count gains. This

remains a challenge.

2.5 Summary

The following two closing remarks can be made:

• A large number of topologies have been proposed for inverter and MIC

applications.

• MICs have been classified into three basic topological groups.

44

Chapter 3 will examine the possibilities of applying the two-inductor boost converter

to this application area. This converter has received much less attention

internationally than many of the older well established converters. It has features

which indicate that it should be a good candidate for the application. The focus of

the thesis will be primarily on developing our understanding of the two-inductor

boost converter and further developing that topology. The MIC application is a

target area in which this technology can be applied.

45

3. RESEARCH OPPORTUNITIES

This chapter reviews the existing literature on the two-inductor boost converter and

demonstrates possible variations of the converter for the three different MIC

topologies discussed in Chapter 2. Firstly the power balance issue in the single

phase MIC implementations should be considered.

3.1 Power Balance in the MICs

As the MIC concept is proposed for single phase applications, a well known 100-Hz

power ripple issue exists. This section discusses the power balance issue and

provides three possible solutions.

3.1.1 Power Balance Issue in the Single Phase Converters

The MICs, like other single phase converters, have the inherent power balance issue,

which needs to be considered in the converter design. Figure 3.1 shows the

simulation waveforms of the load voltage, current and power of the single phase

resistive load, which is supplied by a voltage of 240 V rms and 50 Hz and has a

rated average power of 100 W. A power ripple at 100 Hz can be seen in Figure 3.1.

The instantaneous power varies from zero to 200% of the average power. Therefore,

in the design of the single phase MICs, an energy storage element must be provided

46

to absorb the ripple power component over different intervals of the voltage or

current cycle.

The energy storage in the MICs is most often provided by an electrolytic capacitor.

There are three possible locations for the power balancing capacitor in the MIC

implementations.

The power balancing capacitor can be placed at the converter input, where the dc

voltage is low. The advantage of this approach is that the intermediate dc link

between the dc-dc conversion and the dc-ac inversion is free of any large capacitors

and is able to offer a wide voltage control range. However, as the energy stored in a

capacitor is proportional to CV2 and the volume of a capacitor is proportional to CV,

where C is the capacitance and V is the voltage across the capacitor, the energy

stored by the capacitor per unit volume is low in this solution as the input dc voltage

is low.

The power balancing capacitor can be also placed at the intermediate dc link

between the dc-dc conversion and the dc-ac inversion. As the dc link voltage is

much higher than the dc input voltage, the energy stored by the capacitor per unit

volume will be high in this solution and this is favourable in achieving an overall

compact converter design. However, as the capacitance on the dc link is large, the

dc link cannot provide a wide voltage control range.

47

0 5 10 15 200

100

200

300

400

0 5 10 15 20-1

-0.5

0

0.5

1

0 5 10 15 20-400

-300

-200

-100

0

100

200

300

400

Load

Pow

erp O

(W)

t (ms)

Load

Cur

rent

i O(A

)

t (ms)

Load

Vol

tage

v O(V

)

t (ms)

Figure 3.1 Simulation Waveforms of the Single Phase Resistive Load

48

The third location of the power balancing capacitor is with a second phase

associated with the load. In this case the second independently controlled phase

adjusts the capacitor voltage to cancel the power ripple. Therefore, the sum of the

instantaneous powers of the capacitor and the resistive load is a constant. As the

capacitor experiences an ac voltage, the voltage swing on the capacitor is even larger

than that in the second solution. Therefore, the capacitor can be easily implemented

by a small non-polarised capacitor and the volume and the lifetime issues of the

large electrolytic capacitors can be avoided.

3.1.2 Three-Phase PV Converters

Figure 3.2 shows the block diagram of a three-phase PV converter. Multiple PV

modules are used as the dc power source and an inverter transforms the dc voltage to

the three-phase ac voltage. Unlike the single phase converters, the three-phase

converters have a constant instantaneous load power under the balanced load

condition and the power balance issue does not exist. This can be shown by the

simulation waveforms in Figure 3.3.

Three-Phase Mains

DC-ACInverter

PVModule

Figure 3.2 Three-Phase Photovoltaic Converter

49

Load

Pow

ersp

O1,p

O2 a

ndp O

3(W

)

t (ms)

Load

Cur

rent

siO1

,iO2

and

i O3

(A)

t (ms)

Load

Vol

tage

svO1

,vO2

and

v O3

(V)

t (ms)

Figure 3.3 Simulation Waveforms of the Three-Phase Resistive Load

50

The simulation is performed with SIMULINK under a resistive balanced three-phase

load with a phase voltage of 240 V rms, a frequency of 50 Hz and an average power

of 100 W in each phase. Figure 3.3 shows the load voltage, current and power

waveforms in the individual phases over one cycle. The load voltage, current and

power waveforms in Phase 1 are drawn with the solid lines, those in Phase 2 are

drawn with the dotted lines and those in Phase 3 are drawn with the dashed lines. It

can be observed that the sum of the instantaneous load powers in the three phases,

which is drawn with the dashed-dotted line in Figure 3.3, is a constant over the

entire cycle. Therefore, the energy storage element is not required under the

balanced load conditions. However, control techniques need to be established to

deal with the three-phase unbalanced load conditions.

The easiest approach to develop the three-phase PV converter based on the two-

inductor boost topology is to employ a three-phase PWM inverter after the dc-dc

conversion stage, as shown in Figure 3.4.

S6

E

D4

D1T T

D3

D2

CO

L1 L2

Q1 Q2

S1

S4

S3

+ vO3 −

R 1

R3

R2+

v O1− + v

O2 −

S2

S5

Figure 3.4 Two-Inductor Boost Converter with a Three-Phase PWM Inverter

51

Figure 3.5 shows the topology derived by applying the bilateral inversion theory to

the current-tripler rectifier [108]. The gate signals of the MOSFETs Q1, Q2 and Q3

are phase-shifted with 120º and the MOSFET duty ratio must be greater than 31 to

ensure at least one MOSFET is on.

D1

S6

E

D4

T

D5D3

CO

L1 L3

Q1 Q3

S1

S4

S3

+ vO3 −

R 1

R3

R2+

v O1− + v

O2 −

S2

S5L2

Q2 D2D6

T

Figure 3.5 Three-Phase PV Converter Derived from the Current-Tripler Rectifier

Another possible three-phase PV converter based on the two-inductor boost

converter is shown in Figure 3.6. The output topology has been earlier proposed for

a dc to three-phase converter [109].

Based on the two-inductor boost converter, many other possible three-phase

converter topologies exist [110]. However, these will not be further studied in this

thesis as the thesis concentrates only on the MIC implementations for single phase

applications.

52

+ vO3

E

L1 L2

T

Q1 Q2

Q11

Q12

Q21

Q22

Q31

Q32

C3C1 C2

−

R 1

R3

R2+

v O1− + v

O2 −

Figure 3.6 Three Phase Two-Inductor Boost Converter

3.2 Two-Inductor Boost Converter

Common to the three MIC topologies discussed in Chapter 2 is the demand for a

high output/input voltage gain. Therefore, an isolated converter topology with the

boost feature may be a better solution as a high output/input voltage gain is likely to

be achieved. Amongst a variety of the isolated dc-dc converters with the boost

feature, the two-inductor boost converter shown in Figure 2.7(f) has been developed

by applying the duality principle [111] to the conventional voltage fed half bridge

converter shown in Figure 2.7(a) [112]. Compared with other current fed converters

such as the current fed full bridge converter and the current fed push-pull converter,

the two-inductor boost converter has the lowest switch voltage stress and switch

53

conduction loss and the highest transformer utilization [113]-[115]. These

advantages make the two-inductor boost converter topology an attractive candidate

in the MIC applications, where the PV module functions as the dc source of a low

input voltage and a high input current.

A ZCS resonant two-inductor boost converter employing IGBTs as the switching

devices has been proposed in [113] to remove the switching loss and improve the

converter overall efficiency.

A topology based on the two phase-shifted two-inductor boost converters has been

developed and it is particularly favourable in the high power applications [116]-

[121]. The inputs of the two sub-converters are parallel connected to reduce the

current stresses of the semiconductor devices at the converter input side and the

outputs are series connected to reduce the voltage stresses of the semiconductor

devices at the output side [122], [123]. An auxiliary circuit with only the passive

components is also employed in the converter so that another degree of freedom can

be obtained to control the output voltage.

Recently, two variations of the two-inductor boost converter have been proposed

[124]-[126]. Both of the two new topologies include additional magnetic

components and enable the converter to operate under different operating conditions

such as a light load or a duty ratio of less than 50%, which cannot be achieved by the

original converter. An active snubber circuit has also been proposed for the non-

isolated converter in [124] and [125], aiming to reduce the reverse recovery losses in

54

the diodes and the switching losses in the MOSFETs [127]. It has also been

proposed that the operation of the two-inductor boost converter under the light load

condition and ZVS of the main switching devices can be also achieved under the

critical conduction mode with the variable frequency control [128].

Two-inductor boost converters cascaded with a three-level parallel boost converter

and a buck converter have been respectively proposed in [129] and [130].

Topologically, the two-inductor boost converter can be also derived from the

current-doubler rectifier by applying the theory of the bilateral inversion or the time

reversal duality [131]. In these theories, a dual network is established with the time-

reversed voltage and current waveforms in the original network and the power flow

is reversed [132]-[134]. These theories are different from the conventional duality

principle, where the voltage current transformation is employed [111].

The current-doubler rectifier was widely used in the early 1900’s [135]. This

topology was then reinvented, with the mercury arc rectifiers replaced by the

semiconductor diode rectifiers in the modern technology as shown in Figure 3.7

[136]-[140].

While the current-doubler rectifier has significant advantages in the applications

where the output voltage is low and the output current is high [141], the topology

requires three magnetic components, which contribute to the weight and the cost in

the switch mode power converter designs. Several magnetic integration mechanisms

55

have been proposed for the current-doubler rectifier and one particular scheme

employs two primary and two secondary windings on the magnetic core to perform

as the transformer and the two inductors in the circuit [142], [143]. Most recently

this magnetic integration scheme has been applied to the two-inductor boost

converter [130], [144], [145] and this is supported by the bilateral inversion theory.

L1 CT

L2

R

D1

D2

Figure 3.7 Current-Doubler Rectifier

In the PV MIC applications, the two-inductor boost converter can be configured into

the three topologies discussed in Section 2.4 and these will be individually shown in

the following sections.

3.2.1 Two-Inductor Boost Converter with an Intermediate Constant DC Link

The two-inductor boost converter with a PWM inverter is shown in Figure 3.8. In

this topology, the two-inductor boost converter first converts the low dc voltage

from the PV module to a constant dc voltage compatible with the grid voltage level.

The voltage on the dc link is then fed to a PWM inverter, which transforms the dc

voltage to the ac voltage of the grid frequency. In order to apply MPPT in this

56

converter, the duty cycle of the switches in the two-inductor boost converter can be

adjusted so that the converter offers a variable input to output voltage ratio.

S3

E

D4

D1

T T

D3

+ −

D2

CO

L1 L2

Q1 Q2

S1

S4

S2

vO

Figure 3.8 Hard-Switched Two-Inductor Boost Converter with a PWM Inverter

To combat the high switching losses in the hard-switched two-inductor boost

converter under high switching frequency operation, a ZVS resonant two-inductor

boost converter can be used as shown in Figure 3.9. In order to apply MPPT in this

converter, the variable frequency control can be used to allow the converter to

generate a variable input to output voltage ratio while maintaining the ZVS

condition.

S3

E

D4

D1

T T

D3

+ −

D2

CO

L1 L2

Q1 Q2

S1

S4

S2

C1 C2

Lr

vO

Figure 3.9 Soft-Switched Two-Inductor Boost Converter with a PWM Inverter

57

3.2.2 Two-Inductor Boost Converter with an Unfolding Stage

In this topology, a rectified sinusoidal voltage must be generated after the dc-dc

conversion stage. However, the two-inductor boost converter is a boost derived

converter and a wide output voltage range including zero is not possible. Therefore,

a buck conversion stage must be cascaded with the two-inductor boost converter and

it functions as a variable current source input. The buck converter switch duty cycle

is sinusoidally modulated and the two-inductor boost converter simply operates with

a fixed duty ratio and a fixed voltage gain. The rectified sinusoidal voltage

waveform is produced at the output of the current fed two-inductor boost converter

and transformed to the ac voltage by the following unfolder. The hard-switched and

the soft-switched current fed two-inductor boost converters with the unfolders are

respectively shown in Figures 3.10 and 3.11.

3.2.3 Two-Inductor Boost Converter with a Frequency Changer

The two-inductor boost converter with a frequency changer is shown in Figure 3.12.

In this topology, the intermediate dc link is completely removed and the high

frequency ac waveform in the high frequency transformer is directly transformed to

the ac voltage of the grid frequency through the frequency changer. Another

important feature of this topology is that the output power balance can be achieved

by the addition of a relatively small capacitor Cb at the converter output. Therefore,

the bulky electrolytic capacitors, which are normally required at the converter input

or the dc link to deal with the 100-Hz power ripple in the single phase applications,

58

can be eliminated. It is worth mentioning that the converter shown in Figure 3.12 is

a simplified form of the three-phase converter shown in Figure 3.6. Only two

phases are used and a capacitor is used in one phase to provide the power balance.

E

L1 L2

D3

D1

T T

D4

Dbuck+ −

D2

Q1 Q2

Qbuck

S3

S1

S4

S2

vO

Figure 3.10 Hard-Switched Two-Inductor Boost Converter with an Unfolder

C2 Q2

E

L2

D3

D1T T

Dbuck+ −

Q1

Qbuck

S3

S1

S4

S2

C1 D4

D2Lr

vO

L1

Figure 3.11 Soft-Switched Two-Inductor Boost Converter with an Unfolder

E

L1 L2

T

Q1 Q2

Q11

Q12

Q21

Q22

+ −

R

vO

Q31

Q32Cb

Ct3Ct1 Ct2

Figure 3.12 Two-Inductor Boost Converter with a Frequency Changer

59

3.3 Summary

This chapter presents the research opportunities for the two-inductor boost

converter. First, the power balance issue in the MICs is discussed. As the MIC

design needs to deal with the 100-Hz power ripple, a capacitor is required to absorb

this power ripple and it can be located at the low voltage input, the high voltage dc

link or with a second phase associated with the load. The current international

research interest in the two-inductor boost converter is also summarised in the

chapter and the potential MIC topologies based on the two-inductor boost converter

are demonstrated.

The following chapters will examine:

• The application of the soft-switched two-inductor boost converter in the DC-

link-based MICs.

• The current fed two-inductor boost converters in the MICs with unfolding

stages.

• A frequency-changer-based MIC using the two-inductor boost converter.

• Magnetic core and winding integration developments for the two-inductor

boost converter topology.

60

4. ZERO-VOLTAGE SWITCHING TWO-INDUCTOR BOOST

CONVERTER

Parts of this chapter have been published in the Proceedings of AUPEC 2003, PESC

2002 and 2005. A full list of publications arising from this thesis can be found on

pages xxxiv to xxxvii.

The hard-switched two-inductor boost converter has been thoroughly studied as a

dc-dc conversion stage in the MIC implementations [3]. However, under high

switching frequency operation, the hard-switched converter is unlikely to maintain a

reasonable efficiency due to the worsening switching losses. This chapter will

concentrate on the analysis of the ZVS two-inductor boost converter and establish

the critical circuit parameters and the variable power loss components under

different operating conditions.

4.1 Introduction

Figure 4.1 shows the ZVS two-inductor boost converter, which has been previously

developed by the author during his Master of Engineering study by introducing a

resonant tank including one resonant inductor and two resonant capacitors to the

hard-switched converter proposed in [112]. The resonant two-inductor boost

converter is able to actively utilise the transformer leakage inductance and the

MOSFET output capacitance as part of the resonant components. In this respect,

61

the ZVS is a better soft-switching solution than the ZCS as the MOSFET output

capacitance in the latter cannot be absorbed into the resonant tank [146]. The

resonant arrangement allows the switches to turn on at zero voltage and theoretically

the turn-on switching losses are completely removed.

E

L1 L2

D3

D2

CO

C1C2

Lr

Q1 Q2

VO

+

−

RT T

DQ2DQ1 D4

D1

Figure 4.1 ZVS Two-Inductor Boost Converter

4.1.1 Three Circuit Parameters

Before the design and the control of the ZVS two-inductor boost converter are

discussed in detail, the resonant waveforms in one discontinuous mode are given to

introduce the three important circuit parameters.

The resonance of the converter can be analysed using the equivalent circuit shown in

Figure 4.2. Lr is the effective resonant inductor and rCCC == 21 are the effective

resonant capacitors. DQ1 and DQ2 are the embedded reverse body diodes of the

MOSFETs. The current source I0 models the input inductor L1 or L2. The voltage

source Vd is the output capacitor CO voltage reflected to the transformer primary

62

winding and the diode D corresponds to the diodes in the output full bridge rectifier.

The arrangement for Vd and D assumes a positive resonant inductor current iLr as

illustrated and their polarities reverse when the resonant inductor current becomes

negative.

iLr+

− −

DC1 vC1

I0Vd

DQ1Q1

iQ1

vC2+ I0C2

DQ2 Q2

iQ2Lr

Figure 4.2 Equivalent Resonant Circuit

The analysis of the resonant circuit in Figure 4.2 will establish the equations of the

resonant voltage and current in the converter. The resonant waveforms of a

discontinuous current mode, in which the MOSFET turns off with a non-zero time

delay after the resonant inductor current reaches zero, are shown in Figure 4.3.

In the analysis of the converter operation, there are three important circuit

parameters and they are listed below:

• The load factor k, defined by the equation dkVZI =00 , where r

r

CLZ =0 is

the characteristic impedance of the resonant tank made up of the resonant

inductor and capacitors. It is normally required that k be greater than or

equal to one in order to maintain the ZVS condition.

63

(c)

(b)

(a)

vC1 vC2

iLr

iQ1

Vd

Vd+I0Z0

I0

-I0

I4

I0-I4

2I0

vC1 vC2

2I0

I0

3I0

0 t1t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t

0 t1t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t

0 t1t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t

Figure 4.3 Resonant Waveforms of One Discontinuous Mode

(a) Capacitor Voltage (b) Inductor Current (c) MOSFET Current

• The timing factor ∆1, which determines the initial resonant inductor current

01)0( IiLr ∆−= when Q1 turns off or 017 )( ItiLr ∆= when Q2 turns off. It can

64

be observed that 01 =∆ in the operation mode shown in Figure 4.3.

• The delay angle αd, defined as the angle between the instant when the

inductor current falls to zero and the instant when the corresponding

MOSFET turns off. It can be observed that )( 670 ttd −=ωα in the

waveforms shown in Figure 4.3, where rrCL

10 =ω is the angular

resonance frequency of the resonant tank.

4.1.2 Wide Load Range Operation

The three circuit parameters including the load factor k, the timing factor ∆1 and the

delay angle αd determine the resonant operation of the ZVS two-inductor boost

converter. Variations of these circuit parameters may result in either the continuous

or the discontinuous operation modes of the converter. Different operation modes

lead to different average values of the absolute resonant inductor current, which

controls the rectifier average current on the secondary side and determines the

output power of the converter. Therefore, the wide load range operation of the

resonant two-inductor boost converter can be realised by varying the three circuit

parameters.

The resonant two-inductor boost converter discussed here has an input of 20 V, a

maximum output of 340 V and 200 W. The analysis of the wide load range

operation of this converter is based on varying the three circuit parameters. A

65

variation of the two-inductor boost converter with the voltage clamp is also studied.

The theoretical and the simulation waveforms are provided for both converters and

the experimental results are also provided for the ZVS two-inductor boost converter

without the voltage clamp.

4.2 Design Method and Control Function

According to different values of the load factor k, the timing factor ∆1 and the delay

angle αd, the operation of the ZVS two-inductor boost converter can be classified

into three operating regions as shown in Table 4.1. It is obvious that the resonant

waveforms shown in Figure 4.3 belong to the converter operating in Region 1.

Region 1 2 3

Load Factor k ≥ 1 ≥ 1 < 1

Timing Factor ∆1 = 0 > 0 > 0

Delay Angle αd > 0 = 0 = 0

Possible Operation Modes Discontinuous Continuous and

Discontinuous Continuous and Discontinuous

Table 4.1 Three Operating Regions

In Region 3, k is less than 1 but close to 1 and the converter still maintains the ZVS

condition. However, in this operating region, the range of the values of k is very

limited and the output voltage of the converter varies only slightly. In studying the

wide load range operation of this converter, the operation in this region may be

66

safely neglected. The discussion of the design method and the control function is

given below for the converter operations in Regions 1 and 2. The discussion can be

started with the operation in Region 2 first.

4.2.1 Design Method

The converter design normally involves the determination of the component values

and the selection of the components with the proper electrical ratings. This section

discusses the circuit equations that determine the component values, which are

considered as the key design parameters. The key design parameters of the resonant

two-inductor boost converter are the resonant inductance Lr, the resonant

capacitance Cr and the transformer turns ratio n. Once the key design parameters are

known, the current and the voltage terms in the circuit can be explicitly established

and they are used as the references in the component selection process.

In order to find the key design parameters in Region 2, the circuit parameters

including the timing factor ∆1 and the load factor k must be given initially. The

design equations are:

• The balance of power at the input supply and the output load:

RV

IE O2

02 =⋅ (4.1)

67

where E is the dc input source voltage, VO is the output load voltage and R is the

load resistance.

• The balance of power at the transformer primary and the output load:

RV

IkgV Od

2

01 ),(ˆ =∆∆ (4.2)

where the function ),(ˆ 1 kg ∆∆ is the ratio of the average of the absolute value of

the transformer primary current, that is the resonant inductor current, to the

average input inductor current, I0. The function ),(ˆ 1 kg ∆∆ is determined by two

independent variables, ∆1 and k and can be obtained through the state analysis.

• The load condition:

dkVZI =00 (4.3)

• The transformer turns ratio:

dO nVV = (4.4)

From Equations (4.1) to (4.4), once E, VO, R, ∆1 and k are known, four unknown

variables, I0, Vd, Z0 and n can be solved. In order to further find the resonant

68

inductance and capacitance, a circuit variable γ must be defined in Equation (4.5)

and it is a direct result of the state analysis:

sf0ω

γ = (4.5)

where fs is the switching frequency. If fs is selected, the angular resonant frequency

ω0 can then be calculated from Equation (4.5). The resonant inductance Lr and

capacitance Cr can be duly obtained from Equations (4.6) and (4.7):

0

0

ωZLr = (4.6)

00

211Z

CCC r ω=== (4.7)

4.2.2 Control Function

Once the key design parameters including the resonant inductance and capacitance

and the transformer turns ratio are fixed, the load factor k is no longer an

independent variable. The operation of the ZVS two-inductor boost converter is

completely determined by the magnitude of the initial resonant inductor current,

∆1I0, when the MOSFET turns off. This means that the output voltage or power is

solely dependent on the timing factor ∆1. This section aims to establish the

relationship between Vd, the output capacitor voltage reflected to the transformer

69

primary winding, and ∆1, the timing factor. First, the dependent variable k must be

removed from function ),(ˆ 1 kg ∆∆ in Equation (4.2). Equation (4.2) can be rewritten

as:

RV

IgV Od

2

01 )( =∆∆ (4.8)

Using Equation (4.1), Equation (4.8) can be written as:

)(2

1∆=

∆gEVd (4.9)

Equation (4.9) is of the format of the control function however the function )( 1∆∆g

cannot be solved directly. An indirect method is to add the dependant variable k and

replace with in Equation (4.9): )( 1∆∆g ),(ˆ 1 kg ∆∆

),(ˆ2

1 kgEVd ∆

=∆

(4.10)

From Equation (4.10), Vd can be solved indirectly by calculating the possible values

of against a range of the values of ∆),(ˆ 1 kg ∆∆ 1 and k first and then choosing the

sets of the values of ∆1 and k that fulfil the circuit constraints inherently imposed by

Equations (4.1) to (4.4). As the analytical solution of the function ),(ˆ 1 kg ∆∆

contains inverse trigonometric functions and presents a significant level of

70

complexity, the understanding of the physical implication of the function is greatly

hindered. Therefore, the function is solved numerically by MATLAB program in

the analysis. The qualified sets of ∆1 and k values that obey the circuit constraints

are also obtained numerically and can be found through the following process.

Manipulations of Equations (4.1) to (4.4) yield:

),(ˆ1

1

02

kgRZn

k∆

⋅=∆

(4.11)

This is the circuit constraint which is used to find the qualified sets of ∆1 and k

values and then the numerical relationship between ∆1 and k. Two supplemental

functions can be defined as:

kkh =∆∆ ),( 1,1 (4.12)

),(ˆ1),(

1

02

1,2 kgRZn

kh∆

⋅=∆∆

∆ (4.13)

Equations (4.12) and (4.13) respectively represents a surface in a three-dimensional

space with ∆1 and k as two axes. Then the circuit constraint given in Equation

(4.11) simply means that the relationship between ∆1 and k can be found

numerically by solving the intersection curve of the surfaces and

. Once the relationship between ∆

),( 1,1 kh ∆∆

),( 1,2 kh ∆∆ 1 and k is established, it can be

71

substituted to Equation (4.10) to remove the dependent variable k and the numerical

relationship between Vd and ∆1 can be found. Therefore the final control function in

Region 2 can be derived by the polynomial fitting and expressed as:

)( 1∆= ∆MVd (4.14)

In Region 1, the timing factor is zero and the delay angle is greater than zero. The

analysis of the design method and the control function in this region is similar to that

in Region 2 and will not be repeated. The equations in Region 1 share the same

format with those in Region 2 but the variable ∆1 needs to be replaced with αd and

the subscript ∆ with α to maintain the nomenclatural clarity and consistency. Table

4.2 lists the equations in Region 2 and their counterparts in Region 1. As Equations

(4.1), (4.3) to (4.7) are the same in both operating regions, they are not listed here.

4.3 Wide Load Range Operation of the ZVS Two-Inductor Boost Converter

This section applies the theoretical analysis in Section 4.2 to the ZVS two-inductor

boost converter which has an input voltage of 20 V, a maximum output of 340 V

and 200 W and establishes the possible output voltage range.

4.3.1 State Analysis

This section provides the state analysis of the ZVS two-inductor boost converter.

72

Before Q1 turns off, both Q1 and Q2 are on. At time 0=t , Q1 turns off and the

converter will move up to four possible states before Q2 turns off as shown in Figure

4.4. The resonant capacitor voltage and inductor current waveforms are shown in

Figure 4.5.

Equations in Region 2 Operation Equations in Region 1 Operation

RV

IkgV Od

2

01 ),(ˆ =∆∆ (4.2)R

VIkgV O

dd

2

0),(ˆ =αα (4.15)

RV

IgV Od

2

01 )( =∆∆ (4.8)R

VIgV O

dd

2

0)( =αα (4.16)

)(2

1∆=

∆gEVd (4.9)

)(2

dd g

EVαα

= (4.17)

),(ˆ2

1 kgEVd ∆

=∆

(4.10)),(ˆ

2kg

EVd

d αα

= (4.18)

),(ˆ1

1

02

kgRZn

k∆

⋅=∆

(4.11)),(ˆ

102

kgRZn

kdαα

⋅= (4.19)

kkh =∆∆ ),( 1,1 (4.12) kkh d =),(,1 αα (4.20)

),(ˆ1),(

1

02

1,2 kgRZn

kh∆

⋅=∆∆

∆ (4.13)),(ˆ

1),( 02

,2 kgRZn

khd

d αα

αα ⋅= (4.21)

)( 1∆= ∆MVd (4.14) )( dd MV αα= (4.22)

Table 4.2 Equations in Regions 1 and 2

The initial conditions in State (a) are 01)0( IiLr ∆−= and . The analysis of

each state is given below.

0)0(1 =Cv

73

• State (a) ( ) 10 tt ≤≤

This state starts when Q1 turns off. In this state, the current in the resonant

inductor is still negative. This current and the current source I0 charge the

capacitor and the resonant inductor current decreases. The capacitor voltage vC1

and the inductor current iLr are respectively:

ddC VtVtZItv −+∆+= 000011 cossin)1()( ωω (4.23)

000100

cos)1(sin)( ItItZV

ti dLr +∆+−= ωω (4.24)

LrI0

Vd

State (a) State (b)

I0VdiLr iLr

I0Vd

State (c)

I0Vd

State (d)

iLr iLr

+

−vC1C1

+

−vC1C1

+

−vC1C1

+

−vC1C1

Lr

Lr

Lr

Figure 4.4 Four Possible States

74

0 t

0 t

0 t

t1 t2 t3 t4

vGQ1

vC1

iLr

Vd

∆1I0

−∆1I0

Figure 4.5 Resonant Capacitor Voltage and Inductor Current Waveforms

If , this state will be bypassed and 01 =∆ 01 =t under this condition.

75

• State (b) ( ) 21 ttt ≤≤

This state starts when the current in the resonant inductor reaches zero and Vd

reverses its polarity. If the capacitor voltage vC1 is still lower than Vd, the diode

D is reverse biased and the current source I0 linearly charges the capacitor. The

capacitor voltage vC1 and the inductor current iLr are respectively:

)()()( 1111

01 tvtt

CI

tv CC +−= (4.25)

0)( =tiLr (4.26)

Substituting Equation (4.7) to (4.25) yields:

)()()( 1110001 tvttZItv CC +−= ω (4.27)

If the initial resonant inductor current in State (a) is sufficiently high to cause vC1

to exceed Vd at the end of State (a), this state will be bypassed and under

this condition.

12 tt =

• State (c) ( ) 32 ttt ≤≤

This state starts when vC1 reaches Vd at the end of State (b) or iLr reaches zero if

State (b) is bypassed. In this state, the capacitor resonates with the inductor.

The capacitor voltage vC1 and the inductor current iLr are respectively:

76

[ ] ddCC VttVtvttZItv +−−+−= )(cos)()(sin)( 202120001 ωω (4.28)

0200200

21 )(cos)(sin)(

)( IttIttZ

Vtvti dC

Lr +−−−−

= ωω (4.29)

• State (d) ( ) 43 ttt ≤≤

This state starts when vC1 reaches zero. In this state, the resonant inductor is

linearly discharged by Vd. The capacitor voltage vC1 and the inductor current iLr

are respectively:

0)(1 =tvC (4.30)

)()()( 33 ttLV

titir

dLrLr −−= (4.31)


)()()( 300

3 ttZV

titi dLrLr −−= ω (4.32)

After Q2 turns off, the above states repeat.

4.3.2 Design Process

The output voltage of the resonant converter is higher when it operates in Region 1

77

while the output voltage of the converter is lower when it operates in Region 2.

Therefore, the maximum output voltage, 340 V, must be designed in Region 1 with

a non-zero delay angle αd. The other parameters used in the converter design are

and . VE 20= Ω= 576R

From Equation (4.18), the surface Vd can be drawn against αd and k in Figure 4.6,

where 100 ≤≤ dα and 101 ≤≤ k . Table 4.3 shows the maximum and the

minimum values of Vd on the surface and the relevant circuit parameters.

kαd (radians)

Vd

(V)

Figure 4.6 Surface Vd in Region 1

In the design of the ZVS two-inductor boost converter with a wide load range,

special attention must be paid to the peak MOSFET voltage because the MOSFET

78

with a higher voltage rating normally has a higher drain source on resistance, which

leads to a higher conduction loss. If a lower drain source on resistance is required

under higher voltage ratings, the MOSFET input capacitance will increase

considerably as the product of the input capacitance and drain source on resistance

increases with the drain-source voltage rating [147]. This leads to a higher drive

power and a lower converter overall efficiency. From Equations (4.3) and (4.28),

the peak MOSFET voltage can be calculated as:

dd

CpeakQ V

Vtv

kV⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡−++=

2

212, 1

)(1 (4.33)

As when in Region 1, Equation (4.33) can be simplified to: dC Vtv =)( 21 01 =∆

dpeakQ VkV )1(, += (4.34)

Vd (V) dα (radians) k ),(ˆ kg dαα

107.5 10 1 0.372

40.1 0 10 0.998

Table 4.3 Maximum and Minimum Values of Vd in Region 1

Figure 4.7 shows the surface VQ,peak in Equation (4.34), where 100 ≤≤ dα and

. This surface shows that the peak switch voltage can be extremely high

for certain sets of α

101 ≤≤ k

d and k values. A horizontal surface is also VV ratingQ 200, =

79

drawn in Figure 4.7. In order for the peak MOSFET voltage to be less than 200 V,

the values of αd and k must be selected in the domains where surface VQ,peak is

below surface VQ,rating.

kαd (radians)

VQ

,pea

k(V

)

VQ,peak

VQ,rating

Figure 4.7 Surfaces VQ,peak and VQ,rating in Region 1

An initial set of the circuit parameters 4=dα and 31.2=k is selected. The

justification of the selection will be provided in due course. The peak MOSFET

voltage under this condition is 200 V. The calculation results from Equations (4.1),

(4.3), (4.4) and (4.15) and the state analysis are given in Table 4.4.

The key design parameters including the resonant inductance and capacitance will

be calculated from Equations (4.5) to (4.7) in the due course when the analyses in

80

both Regions 1 and 2 are conducted and the switching frequency is selected.

E (V) I0 (A) ),(ˆ kg dαα Vd (V) n Z0 (Ω) γ (radians)

20 5 0.660 60.6 5.6 27.9 24.8

Table 4.4 Initial Calculation Results in Region 1

The surfaces of the functions described in Equations (4.20) and (4.21) are drawn in

Figure 4.8. The intersection curve uα can be found and the corresponding values of

αd and k of the points on the curve uα are listed in Table 4.5. In this region, the

converter operates in the discontinuous mode only.

kαd (radians)

h 1, α

(αd,

k),h

2,α(α d

,k)

h2,α(αd, k)

h1,α(αd, k)

uα

Figure 4.8 Surfaces ),(,1 kh dαα and ),(,2 kh dαα

81

αd (radians)

k Vd (V)

αd (radians)

k Vd (V)

αd (radians)

k Vd (V)

0.0 1.59 41.8 1.4 1.87 49.0 2.8 2.11 55.5

0.1 1.61 42.3 1.5 1.88 49.5 2.9 2.13 55.9

0.2 1.63 42.9 1.6 1.90 50.0 3.0 2.15 56.3

0.3 1.65 43.4 1.7 1.92 50.4 3.1 2.16 56.8

0.4 1.67 43.9 1.8 1.94 50.9 3.2 2.18 57.2

0.5 1.69 44.5 1.9 1.96 51.4 3.3 2.20 57.6

0.6 1.71 45.0 2.0 1.97 51.8 3.4 2.21 58.1

0.7 1.73 45.5 2.1 1.99 52.3 3.5 2.23 58.5

0.8 1.75 46.0 2.2 2.01 52.8 3.6 2.24 58.9

0.9 1.77 46.5 2.3 2.03 53.2 3.7 2.26 59.3

1.0 1.79 47.0 2.4 2.04 53.7 3.8 2.28 59.7

1.1 1.81 47.5 2.5 2.06 54.1 3.9 2.29 60.2

1.2 1.83 48.0 2.6 2.08 54.6 4.0 2.31 60.5

1.3 1.85 48.5 2.7 2.10 55.0

Table 4.5 Numerical Relationship of αd and k

Through the polynomial fitting, the control function )( dM αα can be found as:

41.79425.41300.21240.0079)( 23 ++−== ddddd MV ααααα (4.35)

The control function )( dM αα can be drawn in Figure 4.9.

82

0 0.5 1 1.5 2 2.5 3 3.5 40

10

20

30

40

50

60

70

αd (radians)

Vd

(V)

Figure 4.9 Control Function )( dM αα

When αd reaches zero, Region 1 operation ends and Region 2 operation starts. At

this point, 0=dα , and 59.1=k VVd 8.41= .

In Region 2, the load factor k continues to decrease from 1.59. From Equation

(4.10), the surface Vd can be drawn against ∆1 and k as shown in Figure 4.10, where

and . 30 1 ≤∆≤ 101 ≤≤ k

In this region, the peak MOSFET voltage can be calculated by Equation (4.33). The

surfaces VQ,peak and VV ratingQ 200, = when 30 1 ≤∆≤ and 101 ≤≤ k are drawn in

Figure 4.11. It can be observed in Figure 4.11 that the peak MOSFET voltage is

83

well below 200 V when . 59.1≤k

k∆1

Vd

(V)


The surfaces of the functions described in Equations (4.12) and (4.13) are drawn in

Figure 4.12. The intersection curve u∆ can be found and the corresponding values of

∆1 and k of the points on the curve u∆ are listed in Table 4.6. Under each set of the

circuit parameters in Table 4.6, the converter operates in the discontinuous mode

when and in the continuous mode when 42.1≥k 39.1≤k .

Through the polynomial fitting, the control function )( 1∆∆M can be found as:

41.7931 9.0395-0.0221.30050)( 121

311 +∆∆+∆=∆= ∆MVd (4.36)

84

The control function can be drawn in Figure 4.13. )( 1∆∆M

When ∆1 reaches 2, k reaches 1 and Region 2 operation ends. At this point,

. VVd 2.26=

k∆1

VQ

,pea

k(V

)

VQ,peak

VQ,rating

Figure 4.11 Surfaces VQ,peak and VQ,rating in Region 2

85

k∆1

h 1, ∆

(∆1,

k),h

2,∆(∆ 1

,k)

h2,∆(∆1, k)

h1,∆(∆1, k)

u∆

Figure 4.12 Surfaces ),( 1,1 kh ∆∆ and ),( 1,2 kh ∆∆ in Region 2

∆1 k Vd (V) ∆1 k Vd (V) ∆1 k Vd (V)

0.0 1.59 41.8 0.7 1.36 35.6 1.4 1.14 30.0

0.1 1.56 40.9 0.8 1.32 34.8 1.5 1.12 29.3

0.2 1.52 40.0 0.9 1.29 33.9 1.6 1.09 28.6

0.3 1.49 39.1 1.0 1.26 33.1 1.7 1.07 27.9

0.4 1.45 38.2 1.1 1.23 32.3 1.8 1.04 27.4

0.5 1.42 37.3 1.2 1.20 31.5 1.9 1.02 26.8

0.6 1.39 36.4 1.3 1.17 30.7 2.0 1.00 26.2

Table 4.6 Numerical Relationship of ∆1 and k

86

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

10

20

30

40

50

60

70

∆1

Vd

(V)

Figure 4.13 Control Function )( 1∆∆M

From the above discussion, it can be summarised that the maximum and the

minimum output voltages by operating the ZVS two-inductor boost converter in

both Regions 1 and 2 are respectively 340 V and 146.7 V, which respectively

correspond to 60.6 V and 26.2 V on the transformer primary winding. The ratio of

the maximum to the minimum voltages is 2.3. This ratio depends on the selection of

the initial set of the values of αd and k. The mathematical manipulation through the

same process shows that the selection of other initial sets of the values of αd and k

results in a similar or smaller ratio of the maximum to the minimum output voltages

if the same restriction of a 200-V peak MOSFET voltage applies.

87

A switching frequency of 500 kHz is selected for the lowest output voltage when

and . Therefore the angular resonance frequency of the resonant

tank and the switching frequency when

0.21 =∆ 00.1=k

0.4=dα and 31.2=k can be calculated

and the results are given in Table 4.7.

∆1 αd (radians) k γ (radians) fs (kHz) ω0 (Mrad/s)

2.0 0 1.00 8.1 500

0 4.0 2.31 24.8 163.9 4.069

Table 4.7 Final Calculation Results of the ZVS Two-Inductor Boost Converter

According to Equations (4.6) and (4.7), HLr µ85.6= and nFCr 82.8= .

4.3.3 Theoretical and Simulation Waveforms

In this section, the theoretical and the simulation waveforms are provided for the

selected operating points listed in Table 4.8. These operating points are selected

from Tables 4.5 and 4.6. The theoretical waveforms are generated by plotting the

device waveforms obtained from Equations (4.23) to (4.32) and the simulation

waveforms are generated in SIMULINK. The converter operates in the

discontinuous mode under points 1 to 3 and in the continuous mode under points 4

to 6.

88

Operating Points ∆1

αd (radians)

k Vd (V)

Theoretical Waveforms

Simulation Waveforms

1 0 4.0 2.31 60.6 Figure 4.14 Figure 4.15

2 0 2.0 1.97 51.8 Figure 4.16 Figure 4.17

3 0 0 1.59 41.8 Figure 4.18 Figure 4.19

4 1.0 0 1.26 33.1 Figure 4.20 Figure 4.21

5 1.6 0 1.09 28.6 Figure 4.22 Figure 4.23

6 2.0 0 1.00 26.2 Figure 4.24 Figure 4.25

Table 4.8 Selected Operating Points

Some important parameters used in the theoretical analysis and the simulation circuit

are summarised below:

• , VE 20=

• HLr µ85.6= ,

• , nFCC 82.821 ==

• , 6.5=n

• . Ω= 576R

It can be observed that the simulation waveforms agree reasonably well with the

theoretical waveforms except that the peak resonant capacitor voltage or the peak

MOSFET drain source voltage in the simulation waveforms is slightly higher than

that in the theoretical waveforms.

89

0 1 2 3 4 5 6 7 8 9 10 11 120

50

100

150

200

250

300

0 1 2 3 4 5 6 7 8 9 10 11 12-20

-15

-10

-5

0

5

10

15

20

0 1 2 3 4 5 6 7 8 9 10 11 12-20

-15

-10

-5

0

5

10

15

20

0 1 2 3 4 5 6 7 8 9 10 11 120

5

10

15

20

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)

Figure 4.14 Theoretical Waveforms of Point 1

90

0 1 2 3 4 5 6 7 8 9 10 11 12-100

-80

-60

-40

-20

0

20

40

60

80

100

0 1 2 3 4 5 6 7 8 9 10 11 120

50

100

150

200

250

300

350

400

0 1 2 3 4 5 6 7 8 9 10 11 120

50

100

150

200

250

300

0 1 2 3 4 5 6 7 8 9 10 11 12-20

-15

-10

-5

0

5

10

15

20

0 1 2 3 4 5 6 7 8 9 10 11 120

5

10

15

20

0 1 2 3 4 5 6 7 8 9 10 11 12-20

-15

-10

-5

0

5

10

15

20

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)

Out

put V

olta

geV

O (V

)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)

t (µs) t (µs)

Figure 4.15 Simulation Waveforms of Point 1

91

0 1 2 3 4 5 6 7 8 90

50

100

150

200

0 1 2 3 4 5 6 7 8 9-15

-10

-5

0

5

10

15

0 1 2 3 4 5 6 7 8 9-15

-10

-5

0

5

10

15

0 1 2 3 4 5 6 7 8 90

5

10

15

20

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)


92

0 1 2 3 4 5 6 7 8 90

5

10

15

20

0 1 2 3 4 5 6 7 8 90

50

100

150

200

0 1 2 3 4 5 6 7 8 90

50

100

150

200

250

300

350

400

0 1 2 3 4 5 6 7 8 9-15

-10

-5

0

5

10

15

0 1 2 3 4 5 6 7 8 9-15

-10

-5

0

5

10

15

0 1 2 3 4 5 6 7 8 9-100

-80

-60

-40

-20

0

20

40

60

80

100

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)

Out

put V

olta

geV

O (V

)

t (µs) t (µs)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)


93

0 1 2 3 4 5 6 7-10

-5

0

5

10

0 1 2 3 4 5 6 7-10

-5

0

5

10

0 1 2 3 4 5 6 70

50

100

150

0 1 2 3 4 5 6 70

5

10

15

20

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)


94

0 1 2 3 4 5 6 70

5

10

15

20

0 1 2 3 4 5 6 70

50

100

150

0 1 2 3 4 5 6 70

50

100

150

200

250

300

350

400

0 1 2 3 4 5 6 7-10

-5

0

5

10

0 1 2 3 4 5 6 7-10

-5

0

5

10

0 1 2 3 4 5 6 7-100

-80

-60

-40

-20

0

20

40

60

80

100

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)

Out

put V

olta

geV

O (V

)

t (µs) t (µs)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)


95

0 1 2 3 4 5-6

-5-4-3-2-10

123456

0 1 2 3 4 5-6

-5-4-3-2-10

123456

0 1 2 3 4 50

20

40

60

80

100

0 1 2 3 4 50

5

10

15

20

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)


96

0 1 2 3 4 50

5

10

15

20

0 1 2 3 4 50

20

40

60

80

100

0 1 2 3 4 50

50

100

150

200

250

300

350

400

0 1 2 3 4 5-6

-5-4-3-2-10

123456

0 1 2 3 4 5-6

-5-4-3-2-10

123456

0 1 2 3 4 5-100

-80

-60

-40

-20

0

20

40

60

80

100

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)

Out

put V

olta

geV

O (V

)

t (µs) t (µs)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)


97

0 1 2 3 40

5

10

15

20

0 1 2 3 40

20

40

60

80

100

0 1 2 3 4-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4-5

-4

-3

-2

-1

0

1

2

3

4

5

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)


98

0 1 2 3 40

5

10

15

20

0 1 2 3 40

20

40

60

80

100

0 1 2 3 40

50

100

150

200

250

300

350

400

0 1 2 3 4-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4-100

-80

-60

-40

-20

0

20

40

60

80

100

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)

Out

put V

olta

geV

O (V

)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)

t (µs) t (µs)


99

0 1 2 3 40

5

10

15

20

0 1 2 3 40

20

40

60

80

100

0 1 2 3 4-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4-5

-4

-3

-2

-1

0

1

2

3

4

5

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)


100

0 1 2 3 40

5

10

15

20

0 1 2 3 40

20

40

60

80

100

0 1 2 3 40

50

100

150

200

250

300

350

400

0 1 2 3 4-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4-100

-80

-60

-40

-20

0

20

40

60

80

100

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)In

duct

orL r

Cur

rent

i Lr (

A)

t (µs)

t (µs)

Out

put V

olta

geV

O (V

)

t (µs) t (µs)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)


4.3.4 Experimental Results

The main components used in the ZVS two-inductor boost converter are listed

below:

101

• Inductors L1 and L2 – Core type Siemens RM10 with 0.21-mm air gap in the

centre pole, ferrite grade Siemens N48, inductor winding turns. 13=LN

• Transformer T – Core type Ferroxube ETD29, ferrite grade Ferroxube 3F3,

primary and secondary wires: Litz wires respectively made up of 28 and 6

strands of 0.11-mm (0.135-mm overall diameter) wire, primary winding

turns, secondary winding 6=pN 34=sN turns, leakage inductance

reflected to the transformer primary HLle µ25.0= .

• Additional Resonant Inductor – Core type Ferroxube ETD44 with 1.6-mm

air gap in the centre core leg, ferrite grade Ferroxube 3F3, Litz wire made up

of 34 strands of 0.11-mm (0.135-mm overall diameter) wire, inductor

winding turns, 6.34 µH inductance. 6=LrN

• Additional Resonant Capacitors – Cornell Dubilier surface mount mica

capacitor MC22FD102J, 1 nF, VVdc 500= , 8.5 nF capacitance used.

• MOSFETs Q1 and Q2 – ST STB22NS25Z, VVDS 250= , ,

,

AI D 22=

Ω= 15.0)(onDSR nFCoss 34.0= .

• Diodes D1 to D4 – ST STTA106U, AI F 0.1= , VVRRM 600= , ,

.

VVF 5.1=

nstrr 20=

• Capacitor CO – Philips MKP capacitor, 1 µF, VVdc 350= .

The experimental waveforms of the converter operating at different points are

respectively shown in Figures 4.26 to 4.30. It is worth mentioning that the converter

operation at Point 6 is only theoretically achievable as the switch duty ratio under

102

this operating point is 50%. This is not practically possible considering the delays

over the MOSFET turn-on and turn-off transitions and the experimental waveforms

will not be shown for this operating point. Therefore, the lowest output voltage is

obtained when the converter operates at Point 5 instead and the practical output

voltage range, 160.7 V to 340 V, is slightly narrower than the theoretical one.

Figures 4.26 to 4.30 respectively shows the MOSFET Q1 gate voltage, the resonant

capacitor voltage and the resonant inductor current from top to bottom. It can be

observed that the experimental waveforms agree reasonably well with the theoretical

waveforms except that the peak resonant capacitor voltage or the peak MOSFET

drain source voltage in the experimental waveforms is slightly higher than that in the

theoretical waveforms.

Figure 4.26 Experimental Waveforms of Point 1

103



104



105

The converter output voltages under the individual operating points in the theoretical

analysis, the simulation results and the experimental results are listed in Table 4.9

and drawn in Figure 4.31.

Output Voltage VO (V) Operating Point Theoretical Analysis Simulation Result Experimental Result

1 340.0 347.0 335.0

2 291.1 298.5 278.6

3 234.9 243.1 234.5

4 186.0 193.3 194.4

5 160.7 168.3 174.0

6 147.2 153.2 N/A

Table 4.9 Output Voltage under Each Operating Point

0

100

200

300

400

0 1 2 3 4 5 6Operating Point

VO (V

)

Theoretical Analysis

Simulation Results

Experimental Results

Figure 4.31 Output Voltage under Each Operating Point

106

4.4 ZVS Two-Inductor Boost Converter with the Voltage Clamp

In the design of the ZVS two-inductor boost converter, the range of the load factor k

is required to be less than 2.31 in the selection of the initial set of the circuit

parameters in Region 1 to obtain a peak MOSFET voltage of less than 200 V. This

constraint inherently results in a very limited output voltage range. However, it can

be seen from the surface VQ,peak shown in Figure 4.7 that when k is very large the

voltage stress of the MOSFET will become excessively high. This makes it hard to

find a MOSFET with a low drain source on resistance to minimise the conduction

power loss. In order to operate the converter with a wider output voltage range and

without the penalty of the high MOSFET voltage stress, mechanisms which are able

to control the MOSFET voltage below a certain level are required. Snubber and

voltage clamping circuits are possible solutions and one simple voltage clamping

circuit without any active switches will be introduced in this section.

4.4.1 Topology

Figure 4.32 shows the ZVS two-inductor boost converter with the voltage clamp.

The voltage clamping circuit is made of two coupled inductors L1p, L1s and L2p, L2s

and two additional diodes DL1 and DL2. L1p and L2p are the inductances of the

inductor main windings. L1s and L2s are the inductances of the inductor clamp

windings and are related to the main windings by the square of the turns ratio. The

turns ratio of the coupled inductor main winding to the clamp winding is nL:1.

When the voltage across the main winding of each coupled inductor reaches nLE, dot

107

negative, the diode DL1 or DL2 will conduct and this clamps the voltage across the

MOSFET to Vc, which is defined as:

EnV Lc )1( += (4.37)

DL1 DL2

L1s L2s

1:nL nL:1E

L1p L2p

D4

D1

D3

D2

CO

C1C2

Lr

Q1 Q2

VO

+

−R

T T

DQ2DQ1

Figure 4.32 ZVS Two-Inductor Boost Converter with the Voltage Clamp

In this analysis, a tight coupling between the two coupled inductor windings is

assumed. Although the transfer of the current from one winding to another does not

need to be instantaneous in a hard-switched converter, that in a soft-switched

converter can be considered instantaneous as small leakage inductances of the

coupled inductors have little effect.


This section provides the state analysis of the ZVS two-inductor boost converter

with the voltage clamp. Different combinations of the circuit parameters including

the load factor k and the timing factor ∆1 determine different states in Figure 4.4

when the voltage clamping circuit becomes active while the delay angle αd only

108

affects the length of the switching period and is irrelevant in the discussion. Before

Q1 turns off, both of Q1 and Q2 are on. The number of the possible states after Q1

turns off and before Q2 turns off depends on the combinations of the values of ∆1

and k. According to the specific state in Figure 4.4 when the voltage clamping

circuit becomes active, the converter operation can be classified into three operating

sets. In each operating set, the values of ∆1 and k will only be qualitatively

discussed as the quantitative analysis requires the exact numerical value of nL. In

Operating Set 1, ∆1 and k are both small (∆1 can be zero) or both medium and the

switch voltage does not reach the clamping voltage Vc in the converter operation at

all. The converter will move through up to four states as shown in Figure 4.4 and

the state analysis has been provided in Section 4.3.1. In Operating Set 2, ∆1 is small

and k is medium or ∆1 is zero and k is large and the switch voltage reaches the

clamping voltage Vc in State (c) in Figure 4.4. The converter will move through up

to six states after Q1 turns off and before Q2 turns off. In Operating Set 3, ∆1 is

greater than zero and k is large enough and the switch voltage reaches the clamping

voltage Vc in State (a) in Figure 4.4. The converter will move through five states

after Q1 turns off and before Q2 turns off. The above discussion is summarised

briefly in Table 4.10.

In Operating Set 2, the voltage clamping circuit becomes active in State (c) shown in

Figure 4.4. Six possible states of the converter after Q1 turns off and before Q2 turns

off are shown in Figure 4.33. If the inductance L1p is large enough, I0 is the current

in the main winding of the coupled inductor when the diode DL1 is not conducting

109

and the voltage clamping circuit is not active. The inductor Le, the diode Dc and the

voltage source Vc form the equivalent circuit of the coupled inductor in State (d) and

will be explained in detail in due course. The initial conditions in State (a) are

and . The analysis of each state is given below. 01)0( IiLr ∆−= 0)0(1 =Cv

Operating Set

Circuit Parameters

Voltage Clamping Circuit Status

Number of States

1 ∆1 and k are both small or ∆1 and k are both medium

Inactive Up to 4

2 ∆1 is small and k medium or ∆1 = 0 and k is large

Active Up to 6

3 ∆1 > 0 and k is large Active 5

Table 4.10 Possible Operating Sets

• State (a) ( ) 1 0 tt ≤≤

This state is similar to State (a) in Section 4.3.1. The capacitor voltage vC1 and

the inductor current iLr are respectively given by Equations (4.23) and (4.24).

• State (b) ( ) 21 ttt ≤≤

This state is similar to State (b) in Section 4.3.1. The capacitor voltage vC1 and


• State (c) ( ) 32 ttt ≤≤

110

This state is similar to State (c) in Section 4.3.1. The capacitor voltage vC1 and


• State (d) ( ) 43 ttt ≤≤

I0

State (a) State (b)

C1

State (c)

State (f)

Vc

State (d)

Dc

iDc

State (e)

E

Le

VdiLrI0

VdiLr+

−vC1C1

I0 C1

VdiLr VdiLr

I0 C1

VdiLrI0 C1

VdiLr

+

−vC1

+

−vC1

+

−vC1

+

−vC1

C1

+

−vC1

Lr

LrLr

LrLr

Lr

Figure 4.33 Six Possible States in Operating Set 2

111

This state starts when the diode DL1 conducts and the resonant capacitor voltage

vC1 is clamped. In this state, the coupled inductor can be replaced by an

equivalent circuit made up of a single-winding inductor Le, a diode Dc and a

voltage source Vc. The inductor Le has the same number of turns as L1p

therefore the inductor Le current must be I0 in order to maintain the flux linkage

or the Ampere-turns balance. Part of I0 feeds the resonant inductor while the rest

of I0 flows through the diode Dc and the voltage source Vc, which represents the

clamping voltage. The resonant inductor current iLr is also the coupled inductor

main winding current and the diode Dc current iDc is the coupled inductor clamp

winding current reflected to the main winding. In this state, the resonant

inductor current is greater than zero therefore the current iDc is smaller than I0.

Vc should be greater than or equal to 2Vd to maintain the ZVS condition and this

will be proved in State (e). The resonant inductor Lr is linearly charged by

. The capacitor voltage vdc VV − C1 and the inductor current iLr are respectively:

cC Vtv =)(1 (4.38)

)()()( 33 ttL

VVtiti

r

dcLrLr −

−+= (4.39)


)()()( 300

3 ttZ

VVtiti dc

LrLr −−

+= ω (4.40)

112

• State (e) ( ) 54 ttt ≤≤

This state starts when the resonant inductor current reaches I0. The diode DL1

becomes reverse biased as the coupled inductor main winding current is I0 and

the clamp winding current is zero. Therefore, the capacitor C1 resonates with the

inductor Lr and this state is similar to State (c) in Section 4.3.1. The capacitor

voltage vC1 and the inductor current iLr are respectively:

ddcC VttVVtv +−−= )(cos)()( 401 ω (4.41)

0400

)(sin)( IttZ

VVti dc

Lr +−−

= ω (4.42)

According to Equation (4.41), it is required that in order to maintain

the ZVS condition.

dc VV 2≥

• State (f) ( ) 65 ttt ≤≤

This state starts when vC1 reaches zero and is similar to State (d) in Section 4.3.1.

The inductor current iLr is:

)()()( 55 ttLV

titir

dLrLr −−= (4.43)

113


)()()( 500

5 ttZV


The capacitor voltage vC1 is given by Equation (4.30).

In Operating Set 3, the voltage clamping circuit becomes active in State (a) shown in

Figure 4.4. Five states of the converter after Q1 turns off and before Q2 turns off are

shown in Figure 4.34. The initial conditions in State (a) are and

. The analysis of each state is given below.

010 )( ItiLr ∆−=

0)( 01 =tvC

• State (a) ( ) 10 tt ≤≤

This state is similar to State (a) in Section 4.3.1. The capacitor voltage vC1 and


• State (b) ( ) 21 ttt ≤≤

This state starts when the diode DL1 conducts and the resonant capacitor voltage

vC1 is clamped. In this state, the resonant inductor current is less than zero

therefore the current iDc is greater than I0. The resonant inductor Lr is linearly

charged by . The inductor current idc VV + Lr is:

114

)()()( 11 ttL

VVtiti

r

dcLrLr −

++= (4.45)

I0

State (a) State (b)

C1

State (c) State (d)

State (e)

VdiLrVc C1

Dc

iDc

E

Le

VdiLr

Vc C1

Dc

iDc

E

Le

VdiLrI0 C1

VdiLr

I0 C1

VdiLr

+

−vC1

+

−vC1

+

−vC1

+

−vC1

+

−vC1

LrLr

LrLr

Lr

Figure 4.34 Five States in Operating Set 3

115


)()()( 100

1 ttZ

VVtiti dc

LrLr −+

+= ω (4.46)


• State (c) ( ) 32 ttt ≤≤

This state starts when the resonant inductor current reaches zero and Vd reverses.

It is similar to State (d) in Operating Set 2. In this state, the resonant inductor

current continues to increase linearly but at a slower rate because the voltage

across Lr in this stage is dc VV − rather than dc VV + in the previous state. As the

resonant inductor current is greater than zero, the current iDc is less than I0. The

inductor current iLr is:

)()()( 22 ttL

VVtiti

r

dcLrLr −

−+= (4.47)


)()()( 200

2 ttZ

VVtiti dc

LrLr −−

+= ω (4.48)

116


• State (d) ( ) 43 ttt ≤≤

This state starts when the resonant inductor current reaches I0 and is similar to

State (e) in Operating Set 2. The capacitor voltage vC1 and the inductor current

iLr are respectively:

ddcC VttVVtv +−−= )(cos)()( 301 ω (4.49)

0300

)(sin)( IttZ

VVti dc

Lr +−−

= ω (4.50)

According to Equation (4.49), it is still required that to maintain the

ZVS condition.

dc VV 2≥

• State (e) ( ) 54 ttt ≤≤

This state starts when vC1 reaches zero and is similar to State (d) in Section 4.3.1.

The inductor current iLr is:

)()()( 44 ttLV

titir

dLrLr −−= (4.51)

117


)()()( 400

4 ttZV



4.4.3 Design Process

The design process of the ZVS two-inductor boost converter with the voltage clamp

is similar to that of the converter without the voltage clamp. However, some design

equations listed in Section 4.2 are in different forms due to the introduction of the

voltage clamping circuit.

Figure 4.35 shows the equivalent circuit of the primary side of the converter when

the MOSFET Q1 is off and the resonant capacitor C1 voltage is clamped, where iIN is

the input current, iL1p and iL1s are respectively the main and the clamp winding

currents of the coupled inductor in the vicinity of Q1 and iL2 is the current of the

coupled inductor in the vicinity of Q2. During this period, part of the energy stored

in the resonant tank will be fed back to the voltage source E through L1s. Therefore,

the average input power of the converter is not 02IE ⋅ as given in Equation (4.1).

The calculation of the average input power when the voltage clamping circuit is

active is given below. Because the resonant inductor current is half cycle

118

symmetrical, the average current and power can be calculated over a half switching

period. T is defined as the half switching period, tˆ c is defined as the duration when

the resonant capacitor voltage is clamped and tnc is defined as the duration when the

voltage clamping circuit is not active. Then it is easy to derive:

ncc ttT +=ˆ (4.53)

iIN

iL1s iL1p

E

L1p

C2C1

Lr T

DL1

L1s

1:nLiLr

DL2

L2p L2s

iL2

Q1 Q2

Figure 4.35 Equivalent Primary Circuit with a Voltage Clamped Capacitor

Over the duration when the voltage clamping circuit is not active, the average input

current IIN,nc and power PIN,nc are:

02II IN = (4.54)

0, 2IEP ncIN ⋅= (4.55)

119

Over the duration when the resonant capacitor voltage is clamped, the following

equations can be found by applying KCL to the junctions inside the dashed circles

shown in Figure 4.35 and the flux linkage or the Ampere-turns balance of the

coupled inductor:

211 LpLsLIN iiii +=+ (4.56)

LrpL ii =1 (4.57)

011 Inini LpLLsL =+ (4.58)

Manipulating Equations (4.56) to (4.58) yields:

)()1( 020 LrLLIN iIniIi −⋅+−+= (4.59)

Then it is important to derive the counterparts of Equations (4.1), (4.10) and (4.18)

in the ZVS two-inductor boost converter with the voltage clamp and only the

derivation process of the equations in Region 2 operation is given here. Other

design equations of the converter with the voltage clamp are the same as those of the

resonant converter without the voltage clamp.

As the diode DL2 is not conducting, iL2 is the main winding current of the coupled

inductor in the vicinity of Q2 and I0 is the average of iL2 over the duration when the

resonant capacitor C1 voltage is clamped. If the function is defined as

the ratio of the average resonant inductor current against a specific set of ∆

),(ˆ 1, kg c ∆∆

1 and k

120

values to I0 over the duration when the resonant capacitor C1 voltage is clamped, the

average input current IIN,c and power PIN,c during this period can be respectively

derived as:

)],(ˆ1[)1(2 1,00, kgInII cLcIN ∆−+−= ∆ (4.60)

)],(ˆ1)[1(2 1,0, kgnEIP cLcIN ∆−+−= ∆ (4.61)

Therefore according to Equation (4.53), the input power PIN of the converter can be

calculated as:

Ttkgn

EIIET

tPtPP ccLccINncncIN

IN ˆ)],(ˆ1)[1(

2ˆ1,

00,, ∆−+

−⋅=+

= ∆ (4.62)

If is defined as: ),( 1 kr ∆∆

Ttkgn

kr ccL

ˆ)],(ˆ1)[1(

),( 1,1

∆−+=∆ ∆

∆ (4.63)

The counterpart of Equation (4.1) in the resonant converter with the voltage clamp

in Region 2 can be derived as:

RV

krEIIE O2

100 ),(2 =∆−⋅ ∆ (4.64)

121

Using Equation (4.2), Equation (4.64) can be written as:

[ ]),(ˆ),(2

1

1

kgEkrVd ∆

∆−=

∆

∆ (4.65)

Table 4.11 lists Equations (4.1), (4.10) and (4.18) and their counterparts in the

resonant converter with the voltage clamp, where ),( kr dαα is defined as:

Ttkgn

kr cdcLd ˆ

)],(ˆ1)[1(),( , α

α αα

−+= (4.66)

Converter without the Voltage Clamp Converter with the Voltage Clamp

RV

krEIIE O2

100 ),(2 =∆−⋅ ∆ (4.64)

RV

IE O2

02 =⋅ (4.1)

RV

krEIIE Od

2

00 ),(2 =−⋅ αα (4.67)

),(ˆ2

1 kgEVd ∆

=∆

(4.10) [ ]),(ˆ),(2

1

1

kgEkrVd ∆

∆−=

∆

∆ (4.65)

),(ˆ2

kgEVd

d αα

= (4.18) [ ]),(ˆ),(2

kgEkr

Vd

dd α

α

α

α−= (4.68)

Table 4.11 Design Equations in the Two Converters

The other equations given in Section 4.2 can be used in the design of the resonant

converter with the voltage clamp without any change. It is especially worth

mentioning that the circuit constraints in Regions 1 and 2 of the resonant converter

122

with the voltage clamp are respectively the same as those given by Equations (4.19)

and (4.11). These can be confirmed by the manipulations of Equations (4.2) to (4.4),

(4.15), (4.64) and (4.67).

Because the output voltage of the converter is higher when it operates in Region 1,

the maximum output voltage, 340 V, must be designed with a non-zero delay angle

αd. In the design of the converter with the voltage clamp, nL is selected to be 3.5

and the clamping voltage is therefore 90 V for the 20-V input from the voltage

source. In this case, MOSFETs with 100-V drain source voltage ratings can be used

in the converter.

From Equations (4.18) and (4.68), the surface Vd can be drawn against αd and k in

Figure 4.36, where 40 ≤≤ dα and 2510 ≤≤ k . Table 4.12 shows the maximum

and the minimum values of Vd in Figure 4.36.

Because the maximum peak MOSFET voltage is limited to 90 V, an initial set of the

design parameters can be easily selected to be 4=dα and 25=k without causing

an excessive voltage stress across the MOSFETs. The calculation results from

Equations (4.3), (4.4), (4.15) and (4.67) and the state analysis are given in Table

4.13.

The key design parameters including the resonant inductance and capacitance will

be calculated from Equations (4.5) to (4.7) in due course when the analyses in both

123

Regions 1 and 2 are conducted and the switching frequency is selected.

0

1

2

3

4 10

15

20

2540

41

42

43

44

45

kαd (radians)

Vd

(V)


Vd (V) αd (radians) k ),(ˆ kg dαα ),( kr dαα

45.0 4 10 0.489 0.816

40.0 0 25 0.535 0.929

Table 4.12 Maximum and Minimum Values of Vd

E (V) I0 (A) ),(ˆ kg dαα Vd (V) ),( kr dαα n Z0 (Ω) γ (radians)

20 9.39 0.494 43.1 0.934 7.9 114.75 110.4

Table 4.13 Initial Calculation Results in Region 1

124

The surfaces ),(,1 kh dαα and ),(,2 kh dαα described in Equations (4.20) and (4.21)

are drawn in Figure 4.37. The intersection curve uα can be found and the

corresponding values of αd and k of the points on the curve uα are listed in Table

4.14. Under each set of the circuit parameters in Table 4.14, the voltage clamping

circuit becomes active in State (c) in Figure 4.4 and the resonant converter with the

voltage clamp operates in Operating Set 2.

kαd (radians)

h 1, α

(αd,

k),h

2,α(α d

,k)

h1,α(αd, k)

h2,α(αd, k)

uα

Figure 4.37 Surfaces ),(,1 kh dαα and ),(,2 kh dαα in Region 1

Through the polynomial fitting, the control function )( dM αα can be found as:

40.01610.90320.0413-0.0024 )( 23 ++== ddddd MV ααααα (4.69)

125

αd (radians)

k Vd (V)

αd (radians)

k Vd (V)

αd (radians)

k Vd (V)

0.0 23.04 40.0 1.4 23.83 41.2 2.8 24.55 42.3

0.1 23.10 40.1 1.5 23.89 41.3 2.9 24.60 42.3

0.2 23.16 40.2 1.6 23.94 41.4 3.0 24.64 42.4

0.3 23.22 40.3 1.7 23.99 41.4 3.1 24.69 42.5

0.4 23.27 40.4 1.8 24.04 41.5 3.2 24.74 42.6

0.5 23.33 40.5 1.9 24.09 41.6 3.3 24.79 42.6

0.6 23.39 40.5 2.0 24.15 41.7 3.4 24.83 42.7

0.7 23.44 40.6 2.1 24.20 41.8 3.5 24.88 42.8

0.8 23.50 40.7 2.2 24.25 41.8 3.6 24.93 42.8

0.9 23.56 40.8 2.3 24.30 41.9 3.7 24.97 42.9

1.0 23.61 40.9 2.4 24.35 42.0 3.8 25.00 43.0

1.1 23.67 41.0 2.5 24.40 42.1 3.9 25.00 43.1

1.2 23.72 41.0 2.6 24.45 42.1 4.0 25.00 43.1

1.3 23.78 41.1 2.7 24.50 42.2

Table 4.14 Numerical Relationship of αd and k

The control function )( dM αα can be drawn in Figure 4.38.

When αd reaches zero, Region 1 operation ends and Region 2 operation starts. At

this point, 0=dα , and 04.23=k VVd 0.40= .

126

0 0.5 1 1.5 2 2.5 3 3.5 40

10

20

30

40

50

αd (radians)

Vd

(V)

Figure 4.38 Control Function )( dααM

In Region 2, k continues to decrease from 23.04. From Equations (4.10) and (4.65),

the surface Vd can be drawn against ∆1 and k as shown in Figure 4.39, where

and . 20 1 ≤∆≤ 251 ≤≤ k

127

k∆1

Vd

(V)


The surfaces and ),( 1,1 kh ∆∆ ),( 1,2 kh ∆∆ described in Equations (4.12) and (4.13) are

drawn in Figure 4.40. The intersection curve u∆ can be found and the corresponding

values of ∆1 and k of the points on the curve u∆ are listed in Table 4.15. Under each

set of the circuit parameters in Table 4.15, the voltage clamping circuit becomes

active in State (a) in Figure 4.4 and the resonant converter with the voltage clamp

operates in Operating Set 3 when 01 >∆ while the voltage clamping circuit

becomes active in State (c) in Figure 4.4 and the resonant converter with the voltage

clamp operates in Operating Set 2 when 01 =∆ .

128

k∆1

h 1, ∆

(∆1,

k),h

2,∆(∆ 1

,k)

h1,∆(∆1, k)

h2,∆(∆1, k)

u∆

Figure 4.40 Surfaces ),( 1,1 kh ∆∆ and ),( 1,2 kh ∆∆ in Region 2

∆1 k Vd (V) ∆1 k Vd

(V) ∆1 k Vd (V)

0.0 23.04 40.0 0.7 15.61 19.1 1.4 9.81 10.2

0.1 21.98 37.1 0.8 14.57 16.9 1.5 9.27 9.7

0.2 20.94 34.0 0.9 13.59 15.1 1.6 8.82 9.3

0.3 19.89 30.8 1.0 12.70 13.7 1.7 8.30 8.9

0.4 18.82 27.6 1.1 11.86 12.5 1.8 7.89 8.6

0.5 17.75 24.5 1.2 11.14 11.6 1.9 7.56 8.3

0.6 16.66 21.6 1.3 10.41 10.8 2.0 7.19 8.1

Table 4.15 Numerical Relationship of ∆1 and k

129

Through the polynomial fitting, the control function )( 1∆∆M can be found as:

40.245831.6496-6.4097-15.8906-4.4120)( 121

31

411 +∆∆∆+∆=∆= ∆MVd (4.70)

The control function can be drawn in Figure 4.41. )( 1∆∆M

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

10

20

30

40

50

∆1

Vd

(V)

Figure 4.41 Control Function )( 1∆∆M

When ∆1 reaches 2, k reaches 7.2. At this point, VVd 1.8= . It is worth noting that

the voltage Vd will further decrease when 21 >∆ . However, the change of Vd is

very likely to be small according to the tendency shown in Figure 4.41.

130

It can be summarised that a wider load range can be achieved by the ZVS two-

inductor boost converter with the voltage clamp. The maximum and the minimum

output voltages are respectively 340 V and 64.0 V, which respectively correspond to

43.1 V to 8.1 V on the transformer primary winding. Therefore, the ratio of the

maximum to the minimum voltages is 5.3, which is much higher than that achieved

by the resonant converter without the voltage clamp. A higher ratio of the maximum

to the minimum voltages can be obtained by a higher initial value of k in the

converter design.

In the design of the resonant converter with the voltage clamp, when the converter

operates in Region 1 the output voltage range is very limited. Therefore, a relatively

wide output voltage range can be achieved simply by operating the converter in

Region 2, where 0=dα . Of course, a higher k is required in this case to obtain the

same ratio of the maximum to the minimum voltages when the converter operates in

both Regions 1 and 2.

A switching frequency of 500 kHz is selected when 0.21 =∆ and .

Therefore the angular resonance frequency of the resonant tank and the switching

frequency when

19.7=k

0.4=dα and 25=k can be calculated and the results are given in

Table 4.16.

According to Equations (4.6) and (4.7), HLr µ19.17= and . nFCC 31.121 ==

131

∆1 αd (radians) k γ (radians) fs (kHz) ω0 (Mrad/s)

2.0 0 7.19 13.4 500

0 4.0 25.00 110.4 60.5 6.676

Table 4.16 Final Calculation Results in the ZVS Two-Inductor Boost Converter with

the Voltage Clamp

4.4.4 Theoretical and Simulation Waveforms

In this section, the theoretical and the simulation waveforms are provided for the

selected operating points listed in Table 4.17. These operating points are selected

from Tables 4.14 and 4.15. The theoretical waveforms are generated by plotting the

device waveforms obtained from Equations (4.23) to (4.29) and (4.38) to (4.52) and

the simulation waveforms are generated in SIMULINK. The converter operates in

Operating Set 2 under Points 1 to 3 and in Operating Set 3 under Points 4 and 5.

Operating Point ∆1

αd (radians)

k Vd (V)

Theoretical Waveforms

Simulation Waveforms

1 0 4.0 25.00 43.1 Figure 4.42 Figure 4.43

2 0 2.0 24.15 41.7 Figure 4.44 Figure 4.45

3 0 0 23.04 40.0 Figure 4.46 Figure 4.47

4 1.0 0 12.70 13.7 Figure 4.48 Figure 4.49

5 2.0 0 7.19 8.1 Figure 4.50 Figure 4.51

Table 4.17 Selected Operating Points

132

Some important parameters used in the theoretical analysis and the simulation circuit

are summarised below:

• , VE 20=

• HLr µ19.17= ,

• , nFCC 31.121 ==

• , 9.7=n

• , 5.3=Ln

• . Ω= 576R

It is worth noting that a 1 µF capacitor is connected in series with the high frequency

transformer in the simulation circuit to prevent the dc current from flowing in the

transformer. The capacitor reactance is selected to be low enough not to affect the

normal circuit operation although this arrangement will affect the transformer

primary voltage waveform. When there is an extended period of the zero resonant

inductor current and both MOSFETs are on, the dc voltage across this dc balancing

capacitor will appear in the transformer primary voltage waveform. However, the

power in the transformer during this period is still zero as the transformer current is

zero.

133

0 3 6 9 12 15 18 21 24 27 30 33-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30 33-40

-30

-20

-10

0

10

20

30

40

0 3 6 9 12 15 18 21 24 27 30 330

20

40

60

80

100

0 3 6 9 12 15 18 21 24 27 30 33-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30 33-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30 330

5

10

15

20

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)

Indu

ctor

L r C

urre

nti L

r (A

)

t (µs)

t (µs)

Indu

ctor

L 1p C

urre

nti L

1p(A

)In

duct

orL 1

s Cur

rent

i L1s

(A)

t (µs) t (µs)

Figure 4.42 Theoretical Waveforms of Operating Point 1

134

0 3 6 9 12 15 18 21 24 27 30 33-60

-40

-20

0

20

40

60

0 3 6 9 12 15 18 21 24 27 30 330

50

100

150

200

250

300

350

400

0 3 6 9 12 15 18 21 24 27 30 33-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30 33-40

-30

-20

-10

0

10

20

30

40

0 3 6 9 12 15 18 21 24 27 30 33-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30 33-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30 330

20

40

60

80

100

0 3 6 9 12 15 18 21 24 27 30 330

5

10

15

20

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)

Indu

ctor

L r C

urre

nti L

r (A

)

t (µs)

t (µs)

Indu

ctor

L 1p C

urre

nti L

1p(A

)In

duct

orL 1

s Cur

rent

i L1s

(A)

t (µs) t (µs)

Out

put V

olta

geV

O (V

)

t (µs) t (µs)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)

Figure 4.43 Simulation Waveforms of Operating Point 1

135

0 3 6 9 12 15 18 21 24 27 300

5

10

15

20

0 3 6 9 12 15 18 21 24 27 300

20

40

60

80

100

0 3 6 9 12 15 18 21 24 27 30-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30-40

-30

-20

-10

0

10

20

30

40

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)

Indu

ctor

L r C

urre

nti L

r (A

)

t (µs)

t (µs)

Indu

ctor

L 1p C

urre

nti L

1p(A

)In

duct

orL 1

s Cur

rent

i L1s

(A)

t (µs) t (µs)


136

0 3 6 9 12 15 18 21 24 27 300

5

10

15

20

0 3 6 9 12 15 18 21 24 27 300

20

40

60

80

100

0 3 6 9 12 15 18 21 24 27 30-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30-60

-40

-20

0

20

40

60

0 3 6 9 12 15 18 21 24 27 30-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30-30

-20

-10

0

10

20

30

0 3 6 9 12 15 18 21 24 27 30-40

-30

-20

-10

0

10

20

30

40

0 3 6 9 12 15 18 21 24 27 300

50

100

150

200

250

300

350

400

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)

Indu

ctor

L r C

urre

nti L

r (A

)

t (µs)

t (µs)

Indu

ctor

L 1p C

urre

nti L

1p(A

)In

duct

orL 1

s Cur

rent

i L1s

(A)

t (µs) t (µs)

Out

put V

olta

geV

O (V

)

t (µs) t (µs)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)


137

0 3 6 9 12 15 18 21 240

5

10

15

20

0 3 6 9 12 15 18 21 240

20

40

60

80

100

0 3 6 9 12 15 18 21 24-20

-15

-10

-5

0

5

10

15

20

0 3 6 9 12 15 18 21 24-20

-15

-10

-5

0

5

10

15

20

0 3 6 9 12 15 18 21 24-20

-15

-10

-5

0

5

10

15

20

0 3 6 9 12 15 18 21 24-40

-30

-20

-10

0

10

20

30

40

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)

Indu

ctor

L r C

urre

nti L

r (A

)

t (µs)

t (µs)

Indu

ctor

L 1p C

urre

nti L

1p(A

)In

duct

orL 1

s Cur

rent

i L1s

(A)

t (µs) t (µs)


138

0 3 6 9 12 15 18 21 240

5

10

15

20

0 3 6 9 12 15 18 21 240

20

40

60

80

100

0 3 6 9 12 15 18 21 24-20

-15

-10

-5

0

5

10

15

20

0 3 6 9 12 15 18 21 24-60

-40

-20

0

20

40

60

0 3 6 9 12 15 18 21 24-20

-15

-10

-5

0

5

10

15

20

0 3 6 9 12 15 18 21 24-20

-15

-10

-5

0

5

10

15

20

0 3 6 9 12 15 18 21 24-40

-30

-20

-10

0

10

20

30

40

0 3 6 9 12 15 18 21 240

50

100

150

200

250

300

350

400

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)

Indu

ctor

L r C

urre

nti L

r (A

)

t (µs)

t (µs)

Indu

ctor

L 1p C

urre

nti L

1p(A

)In

duct

orL 1

s Cur

rent

i L1s

(A)

t (µs) t (µs)

Out

put V

olta

geV

O (V

)

t (µs) t (µs)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)


139

0 1 2 3 4 5 60

5

10

15

20

0 1 2 3 4 5 60

20

40

60

80

100

0 1 2 3 4 5 6-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4 5 6-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4 5 6-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4 5 6-15

-10

-5

0

5

10

15

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)

Indu

ctor

L r C

urre

nti L

r (A

)

t (µs)

t (µs)

Indu

ctor

L 1p C

urre

nti L

1p(A

)In

duct

orL 1

s Cur

rent

i L1s

(A)

t (µs) t (µs)


140

0 1 2 3 4 5 60

5

10

15

20

0 1 2 3 4 5 60

20

40

60

80

100

0 1 2 3 4 5 6-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4 5 6-60

-40

-20

0

20

40

60

0 1 2 3 4 5 6-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4 5 6-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 4 5 6-15

-10

-5

0

5

10

15

0 1 2 3 4 5 60

50

100

150

200

250

300

350

400

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)

Indu

ctor

L r C

urre

nti L

r (A

)

t (µs)

t (µs)

Indu

ctor

L 1p C

urre

nti L

1p(A

)In

duct

orL 1

s Cur

rent

i L1s

(A)

t (µs) t (µs)

Out

put V

olta

geV

O (V

)

t (µs) t (µs)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)


141

0 1 2 3 40

5

10

15

20

0 1 2 3 40

20

40

60

80

100

0 1 2 3 4-2

-1

0

1

2

0 1 2 3 4-2

-1

0

1

2

0 1 2 3 4-2

-1

0

1

2

0 1 2 3 4-5

-4

-3

-2

-1

0

1

2

3

4

5

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)

Indu

ctor

L r C

urre

nti L

r (A

)

t (µs)

t (µs)

Indu

ctor

L 1p C

urre

nti L

1p(A

)In

duct

orL 1

s Cur

rent

i L1s

(A)

t (µs) t (µs)


142

0 1 2 3 40

5

10

15

20

0 1 2 3 40

20

40

60

80

100

0 1 2 3 4-2

-1

0

1

2

0 1 2 3 4-60

-40

-20

0

20

40

60

0 1 2 3 4-2

-1

0

1

2

0 1 2 3 4-2

-1

0

1

2

0 1 2 3 4-5

-4

-3

-2

-1

0

1

2

3

4

5

0 1 2 3 40

50

100

150

200

250

300

350

400

MO

SFET

Q1 G

ate

Vol

tage

v GQ

1 (V

)C

apac

itorC

1 Vol

tage

v C1 (

V)

t (µs)

t (µs)

MO

SFET

Q1 C

urre

nti Q

1(A

)

Indu

ctor

L r C

urre

nti L

r (A

)

t (µs)

t (µs)

Indu

ctor

L 1p C

urre

nti L

1p(A

)In

duct

orL 1

s Cur

rent

i L1s

(A)

t (µs) t (µs)

Out

put V

olta

geV

O (V

)

t (µs) t (µs)

Tran

sfor

mer

T Pr

imar

y V

olta

gev p

(V)


143

The converter output voltages under the individual operating points in the theoretical

analysis and the simulation results are listed in Table 4.18 and drawn in Figure 4.52.

Output Voltage VO (V) Operating Point Theoretical Analysis Simulation Results

1 340.0 369.4

2 329.0 352.9

3 315.5 329.7

4 105.7 109.6

5 63.9 65.0

Table 4.18 Output Voltage under Each Operating Point

0

100

200

300

400

0 1 2 3 4 5Operating Point

VO (V

)

Theoretical Analysis

Simulation Results

Figure 4.52 Output Voltage under Each Operating Point

144

4.5 Comparisons of the Two ZVS Two-Inductor Boost Converters

Comparisons on the advantages and disadvantages of the two ZVS two-inductor

boost converters are given briefly in the following sections.

4.5.1 Output Voltage Range

The converter without the voltage clamp is able to achieve a theoretical maximum to

minimum output voltage ratio of 2.3 while the converter with the voltage clamp is

able to achieve a ratio of 5.3. Therefore the maximum to minimum output voltage

ratio of the converter with the voltage clamp is significantly higher than that of the

converter without the voltage clamp. To further increase the maximum to minimum

output voltage ratio is possible with either a higher switch voltage stress in the

converter without the voltage clamp or a higher load factor in the converter with the

voltage clamp.

4.5.2 Switching Frequency Range

In order to produce a variable output voltage, the switching frequency needs to vary

from 163.9 kHz to 500 kHz in the converter without the voltage clamp or from 60.5

kHz to 500 kHz in the converter with the voltage clamp. The wide switching

frequency range is a significant disadvantage for the converter operation as this

makes it difficult to optimise the design of the magnetic components, the control

circuit and the input and the output filters.

145

4.5.3 Resonant Inductor

The resonant inductor used in the converter with the voltage clamp is 17.19 µH,

which is much larger than the resonant inductor of 6.85 µH in the converter without

the voltage clamp. The problem with the large inductor is that it has a larger power

rating and given a fixed upper limit for the quality factor, it has higher power losses.

4.5.4 Switch Voltage Stress

The above maximum to minimum output voltage ratios are achieved with a

maximum switch voltage of 200 V in the converter without the voltage clamp and

90 V in the converter with the voltage clamp. The maximum switch voltage is

significantly higher in the converter without the voltage clamp and this requires

MOSFETs with higher voltage ratings, which may lead to higher conduction loss or

drive power.

4.5.5 Soft-Switching Condition

Theoretically the ZVS condition is maintained for both resonant converters under

the variable frequency operation. However, in the ZVS converter with the voltage

clamp, the load factor is very large and the soft-switching condition is almost lost as

dv/dt at the switch turn-on or turn-off is very large. This can be seen from the

simulation waveforms of the resonant capacitor voltage in Figures 4.43, 4.45 and

146

4.47. The voltage waveforms across the resonant capacitor, also the MOSFET, are

very similar to those in the hard-switched converters. Only when the output voltage

becomes lower, dv/dt at the turn-on or the turn-off transitions becomes smaller,

offering the ZVS condition as shown in Figures 4.49 and 4.51. Therefore, the

resonant converter with the voltage clamp could suffer from high switching losses

under medium to high output voltages.

4.5.6 Efficiency

Besides the conduction and the switching losses, the high circulating energy in the

two resonant converters could also result in significant power losses. This is

especially true in the resonant converter with the voltage clamp, where part of the

energy stored in the resonant tank will be returned to the input voltage source when

the voltage across the resonant capacitor is clamped. The additional power flow

introduced by the voltage clamp causes high current circulating in the converter and

contributes to the total power loss in a practical converter with non-ideal

components. Therefore, the efficiency of the converter with the voltage clamp is

likely to be lower than the converter without the voltage clamp, if no further

measures are taken.

4.6 Power Loss Analysis

It has been discussed in the previous sections that for the ZVS two-inductor boost

converter with a fixed set of the key design parameters including the resonant

147

inductance and capacitance and the transformer turns ratio, the variations of the

circuit parameters such as the load factor, the timing factor and the delay angle allow

the converter to generate a variable output voltage, which results in a variable load

condition. However, under a fixed load condition, variations of the three circuit

parameters lead to the requirement of different sets of the key design parameters to

maintain the ZVS condition. As the circuit parameters determine the resonant

condition of the converter, the power loss components in the converter vary.

4.6.1 Variable Power Loss Terms

The major power loss components in the ZVS two-inductor boost converter shown

in Figure 4.1 are listed below:

• The conduction loss in the two power MOSFETs Q1 and Q2,

• The power loss related to the series dc plus ac resistance of the resonant

inductor Lr,

• The power loss related to the Equivalent Series Resistance (ESR) of the

resonant capacitors C1 and C2,

• The copper and core loss in the two input inductors L1 and L2,

• The copper and core loss in the transformer T, and

• The conduction loss in the four diodes D1 to D4 in the full-bridge rectifier.

In the physical construction of the ZVS two-inductor boost converter, the

148

MOSFETs, the additional resonant inductor and the additional resonant capacitors

are implemented by the components with the pre-determined electrical

characteristics. If the output power is fixed, different resonant inductance and

capacitance are required and different resonant voltage and current waveforms are

established in the converter under different circuit parameters. Therefore the power

losses associated with the MOSFETs, the resonant inductor and capacitors vary.

The input inductors and the transformer can be designed after the circuit parameters

are selected and the inductor and the transformer windings can be configured in a

way to produce a desired total copper and core loss. The power loss in the diodes is

only load sensitive once the diodes are selected and will not vary against different

circuit parameters. Therefore in order to achieve a minimum total power loss in the

ZVS two-inductor boost converter, only the variable power loss components of the

MOSFETs, the resonant inductor and capacitors need to be considered. They are

respectively discussed below.

• The power loss in the two MOSFETs pQ:

)(2 ,)(2

, FavgQonDSrmsQQ VIRIp += (4.71)

where IQ,rms is the effective forward current in the MOSFET, RDS(on) is the

MOSFET drain source on resistance, IQ,avg is the average reverse current in the

MOSFET and VF is the forward voltage drop of the MOSFET body diode.

RDS(on) and VF can be obtained from the component datasheet.

149

• The power loss in the resonant inductor pLr:

LrrmsLrLr RIp 2,= (4.72)

where ILr,rms is the effective current in the resonant inductor and RLr is the series

dc plus ac resistance of the resonant inductor.

• The power loss in the two resonant capacitors pCr:

CrrmsCrCr RIp 2,2= (4.73)

where ICr,rms is the effective current in the resonant capacitor and RCr is the ESR

of the resonant capacitors.

The total power loss ptotal,var which alters with different circuit parameters in the

converter is:

CrLrQtotal pppp ++=var, (4.74)

In order to calculate the variable power loss components in Equations (4.71) to

(4.73), a variety of the current terms and the equivalent series resistances of the

resonant inductor and capacitors must be obtained. The current terms can be

obtained through the state analysis given in Section 4.3.1 while the series resistance

150

of the resonant inductor and the ESR of the resonant capacitors must be further

derived with two other direct results through the state analysis, the circuit variable γ

and the resonant tank characteristic impedance Z0.

The quality factor of the resonant inductor and the dissipation factor (DF) of the

resonant capacitor are respectively defined as:

Lr

rs

RLf

Qπ2

= (4.75)

Crrs RCfDF π2= (4.76)

Manipulations of Equations (4.5) to (4.7), (4.75) and (4.76) yield:

γπQ

ZRLr

02= (4.77)

πγ

20ZDF

RCr = (4.78)

An example of the numerical calculation of the variable power loss components in a

200-W ZVS two-inductor boost converter is given below. The converter has an

input voltage of 20 V and an output voltage of 340 V and the switching frequency is

500 kHz. The following component parameters of the selected MOSFETs, resonant

inductor and capacitors are used [148], [149]:

151

• and Ω= 027.0)(onDSR VVF 5.1= for STB50NE10 MOSFETs,

• at 500 kHz for the air core toroidal inductors, 96=Q

• 60001=DF at 500 kHz for Cornell Dubilier surface mount mica

capacitors.

It is worth noting that the selected MOSFET STB50NE10 has a drain source

breakdown voltage of 100 V. However a certain set of the circuit parameters may

result in a peak MOSFET voltage of more than 100 V and the MOSFET

STB50NE10 cannot be used. As a desired peak MOSFET voltage of 100 V is set to

limit the drive power and the MOSFETs with higher voltage ratings normally have

higher drain source on resistances and similar forward voltage drops of the body

diodes, the use of the component parameters of the selected MOSFET over the

entire range of the circuit parameters can be justified.

It is also worth mentioning that as the transformer leakage inductance and the

MOSFET output capacitance respectively form part of the resonant inductor and

capacitors in the ZVS two-inductor boost converter, the actual power losses of these

components will be different from the results obtained through Equations (4.72) and

(4.73) if the parameters of the selected additional resonant inductor and capacitors

are used. However, under the assumption that the values of the parasitic

components are relatively small compared with the total required resonant

inductance and capacitance values, the errors in the results of Equations (4.72) and

(4.73) are unlikely to be large.

152

When the converter operates in Region 2, the power losses defined in Equations

(4.71) to (4.74) are respectively drawn in Figures 4.53 to 4.56, where 20 1 ≤∆≤

and . In Figures 4.53 to 4.55, the power losses of the MOSFETs, the

resonant inductor and capacitors increase along both the ∆

41 ≤≤ k

1 and k axes and the

lowest power losses are respectively 2.90 W, 1.48 W, 0.04 W when and

. In Figure 4.56, the total variable power loss increases along both the ∆

01 =∆

1=k 1 and k

axes and the lowest total variable power loss is 4.42 W when 01 =∆ and . 1=k

∆1k

p Q (W

)

Figure 4.53 Power Loss in the MOSFETs in Region 2

153

∆1k

p Lr (

W)

Figure 4.54 Power Loss in the Resonant Inductor in Region 2

k

p Cr (

W)

∆1

Figure 4.55 Power Loss in the Resonant Capacitors in Region 2

154

∆1k

p tot

al,v

ar (W

)

Figure 4.56 Total Variable Power Loss in Region 2

When the converter operates in Region 1, the power losses defined in Equations

(4.71) to (4.74) are respectively drawn in Figures 4.57 to 4.60, where 40 ≤≤ dα

and . In Figures 4.57 and 4.58, the power losses of the MOSFETs and the

resonant inductor decrease along the α

41 ≤≤ k

d axis and increase along the k axis and the

lowest power losses shown are respectively 2.07 W, 0.93 W when 4=dα and

. In Figure 4.59, the power loss of the resonant capacitors increases along both

the α

1=k

d and k axes. The lowest power loss is 0.04 W when 0=dα and and this

is the same point in Region 2 where the lowest power loss appears in the resonant

capacitors. In Figure 4.60, the total power loss decreases along the α

1=k

d axis and

increases along the k axis as the power loss in the resonant capacitors is significantly

155

smaller than the power losses in the MOSFETs and the resonant inductor. The

lowest total power loss shown is 3.06 W when 4=dα and . The theoretical

lowest total power loss can be further reduced with a higher value of α

1=k

d.

αd (radians)k

p Q (W

)

Figure 4.57 Power Loss in the MOSFETs in Region 1

156

k

p Lr (

W)

αd (radians)

Figure 4.58 Power Loss in the Resonant Inductor in Region 1

k

p Cr (

W)

αd (radians)

Figure 4.59 Power Loss in the Resonant Capacitors in Region 1

157

k

p tot

al,v

ar (W

)

αd (radians)

Figure 4.60 Total Variable Power Loss in Region 1

4.6.2 Optimised Operating Point

Considering the converter operations in both Regions 1 and 2, a lower total power

loss appears when the converter operates in Region 1. It can be observed from

Figure 4.60 that under the same k value, the greater the αd value, the lower the total

variable power loss. However, a higher peak switch voltage appears while αd

increases as shown by the surface VQ,peak in Figure 4.61.

A peak switch voltage of 100 V is set in the converter operation to obtain a low

MOSFET drain source on resistance as mentioned before. The MOSFET input

capacitance increases for the same value of the drain source on resistance at a higher

158

voltage rating and this demands a higher power from the drive circuit and lowers the

converter overall efficiency. A lower peak switch voltage therefore a lower αd is

preferred. Another reason to choose a lower αd value is that the gradient of the

surface ptotal,var along the αd axis is very small. When 1=k and 40 ≤≤ dα , the

average gradient of the power loss against αd is -0.34 W/radian, while that of the

peak switch voltage against αd is 12.9 V/radian. Figures 4.60 and 4.61 show that the

changes of the total variable power loss and the peak switch voltage along the αd

axis under the same k value are both monotonic. The final circuit parameters for the

optimised power loss in the ZVS two-inductor boost converter are , 1.1=k 01 =∆

and 0=dα . Under this condition, the total power loss is 4.64 W and the peak

switch voltage is 90 V. The safety margin for k to maintain the ZVS condition is

justified by the numerical results from MATLAB, which show that the increase of k

from 1 to 1.1 when and 01 =∆ 0=dα only raises the average power loss by an

insignificant amount of 0.22 W. Once the circuit parameters are determined, the key

design parameters in the converter can be obtained as the following:

• The resonant inductance HLr µ40.1= ,

• The resonant capacitance nFCr 7.15= , and

• The transformer turns ratio 9.7=n .

159

k

VQ

,pea

k (V

)

αd (radians)

Figure 4.61 Peak Switch Voltage in Region 1

4.7 Summary

This chapter examines the operation of the ZVS two-inductor boost converter in

detail. With a fixed set of the key design parameters including the resonant

inductance and capacitance and the transformer turns ratio, variations of the circuit

parameters such as the load factor, the timing factor and the delay angle result in a

variable output to input voltage gain. A set of the explicit control functions is

established under the variable frequency control. In order to obtain a wider output

voltage range without excessive switch voltage stresses, a voltage clamping circuit

can be added to the ZVS two-inductor boost converter. However, the increase of the

output voltage range is obtained at the cost of a higher component count and the

160

potential higher power loss associated with the circulating energy.

If a fixed load condition is desired, the ZVS two-inductor boost converter has the

option to operate under any possible combinations of the three circuit parameters in

Regions 1 and 2. In this case, the power losses in the MOSFETs, the resonant

inductor and capacitors vary against the circuit parameters. An optimised operating

point can be selected based on the numerical analysis of the total variable power

loss. Resonant cells that have been optimised for loss will form an important part of

the current fed MIC solutions presented in the later chapters of this thesis.

161

5. INTEGRATED MAGNETICS

Parts of this chapter have been published in IEEE Power Electronic Letters in 2005

and in the Proceedings of AUPEC 2005.

The two-inductor boost converter has been proven to be favourable in the

applications where low-voltage high-current dc input needs to be transformed to

high-voltage dc output. The high dc voltage gain, the low switch voltage stress, the

full utilisation of the transformer windings, the ease in the transformer volt-second

balance and the relaxed diode reverse recovery requirement are several advantages

of this boost-derived converter. In the effort of reducing the converter size by

increasing the switching frequency, the soft-switching technique is employed and

the ZVS two-inductor boost converter results as shown in Chapter 4. In both the

hard-switched and the soft-switched forms, however, the two-inductor boost

converter requires at least three separate magnetic components including two

inductors and one transformer, which are accounted for the bulk, weight and cost

[150]. This requirement also departs from the philosophy of “more silicon and less

iron” in the design of the modern power electronic converters [91]. If three separate

magnetic components can be merged into a single magnetic structure, not only can

the size of the converter be greatly reduced, but also the converter will be more cost

effective.

The magnetic core integration theory was formally presented more than twenty years

162

ago as a way to assist in reducing the size of the switch mode power converters

[151]-[153], while a simple showcase of the application can be traced back to early

1930’s [154]. Recently, winding integration concept has been proposed as a new

technique in reducing the winding cost and improving the efficiency [155]. Over the

years, these integrated magnetic approaches have been widely applied to the current-

doubler rectifier circuit [138], [142], [143], [156]-[161].

This chapter provides a generic approach to the magnetic integration of the two

inductors and the transformer in the two-inductor boost converter and presents a

detailed analysis of the individual structures. Four integrated magnetic structures

will be discussed in detail which will be referred as Structures A, B, C and D.

Structure A is a new structure and has been independently proposed by Gao and

Ayyannar in [130] and by the author in [162]. This structure first appears in this

thesis in Figure 5.5 on page 170. Structure B is also a new structure and has been

proposed by the author in [163]. This structure first appears in this thesis in Figure

5.9 on page 189. Structure C has been proposed by Gao and Ayyannar in [130] and

by Yan and Lehman in [144] and [145]. This structure first appears in this thesis in

Figure 5.11 on page 192. Structure D has been independently proposed by Gao and

Ayyannar in [130], by Yan and Lehman in [145] and by the author in [164] while a

major contribution of this thesis is a comprehensive analysis of the structure. This

structure first appears in this thesis in Figure 5.13 on page 198.

The equivalent input and magnetising inductance values of the two-inductor boost

converter with integrated magnetics are established and the comparisons of the four

163

different magnetic structures are provided. A soft-switched two-inductor boost

converter with Structure B magnetic integration is also analysed in detail.

5.1 State Analysis of the Hard-Switched Two-Inductor Boost Converter

with Discrete Magnetics

In order to analyse the two-inductor boost converter with the integrated magnetic

structures, state analysis must be first conducted for the converter with discrete

magnetic components. Figure 5.1 shows the hard-switched two-inductor boost

converter with a voltage-doubler rectifier. In the analysis, all the components are

considered to be ideal and the capacitors in the voltage-doubler rectifier are assumed

to be large enough so that the output is a pure dc voltage.

iIN

E

L2

D2

D1

CO2

CO1

R VO

+

−

i1 i2

+ − + −is

IO

a bT T

Q1 Q2

vL1

+

−

vL2

+

−vp vsip

L1

Figure 5.1 Hard-Switched Two-Inductor Boost Converter

Before Q1 turns off, both Q1 and Q2 are on. At time 0=t , Q1 turns off and the

converter will move through four states within a switching period as shown in

Figure 5.2. In order to be different from the state analysis in the ZVS two-inductor

164

boost converter, where States (a) to (d) are used for the individual resonant states

over a half switching period, States (1) to (4) are used here for the individual

switching states over one complete switching period.

i1

i1

E

L2

D2

D1

CO2

CO1

R VO

+

−

i1 i2

+ − + −

IOiIN

a bT T

Q1 Q2

vL1

+

−

vL2

+

−

vp vs

E

L2

D2

D1

CO2

CO1

R VO

+

−

i2

+ − + −

IOiIN

a bT T

Q1 Q2

vL1

+

−

vL2

+

−

vp vsE

L2

D2

D1

CO2

CO1

R VO

+

−

i1 i2

+ − + −

IOiIN

a bT T

Q1 Q2

vL1

+

−

vL2

+

−

vp vs

State (1) State (2)

State (3) State (4)

E

L2

D2

D1

CO2

CO1

R VO

+

−

i2

+ − + −

IOiIN

a bT T

Q1 Q2

vL1

+

−

vL2

+

−

vp vsisip isip

isipisip

L1

L1L1

L1

Figure 5.2 Four States of the Hard-Switched Two-Inductor Boost Converter

The duty ratio of the MOSFETs is Ds and it must be greater than 50% to prevent the

open circuit of the currents in the two inductors from happening. The switching

period is Ts. The input inductance is LLL == 21 . The numbers of turns of the

transformer T primary and secondary windings are respectively Np and Ns. The

voltages of the transformer T primary and secondary are respectively vp and vs. The

transformer magnetising inductance reflected to the secondary side is Lms. In the

analysis of each state, the derivatives of the instantaneous converter input current

and the instantaneous transformer secondary current i21 iiiIN += s are solved. These

equations will be used as the templates to obtain the equivalent circuits of the

165

converter with integrated magnetics later in the chapter.

• State (1) ( ) ss TDt )1(0 −<<

In this state, Q1 is off and Q2 is on. The circuit equations are:

pvEdtdiL −=1 (5.1)

EdtdiL =2 (5.2)

ss

pp v

NN

v = (5.3)


⎟⎟⎠

⎞⎜⎜⎝

⎛−=

+s

s

p vNN

ELdt

iid 21)( 21 (5.4)

The transformer model with the magnetising inductance reflected to the

secondary side is used to derive dtdis , as shown in Figure 5.3. The currents in the

ideal transformer primary and secondary windings are respectively ip and is1, and

the transformer magnetising current reflected to the secondary side is is2.

166

is+

−

+

−

is2is1ipLmsNp Ns

T

vsvp

Figure 5.3 Equivalent Transformer Model

The following equations can be obtained from Figures 5.2 and 5.3:

ps

ps i

NN

i =1 (5.5)

1ii p = (5.6)

Manipulations of Equations (5.1), (5.3), (5.5) and (5.6) yield:

Lv

NN

LE

NN

dtdi s

s

p

s

ps

2

1⎟⎟⎠

⎞⎜⎜⎝

⎛−⋅= (5.7)

The transformer model in Figure 5.3 also gives:

ms

ss

Lv

dtdi

−=2 (5.8)

21 sss iii += (5.9)

167


ss

p

mss

ps vLN

NLL

ENN

dtdi

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅=

112

(5.10)

• State (2) (2

)1( sss

TtTD <<− )

In this state, Q1 and Q2 are both on. Following the process in State (a), the

derivative of the input current can be found as:

ELdt

iid 21)( 21 =+

(5.11)

According to Figure 5.2, the following equation can be obtained:

0=sv (5.12)

As the transformer secondary voltage is zero, both of the diodes D1 and D2 are

reverse biased and the transformer secondary current is zero at all times within

this state. The derivative of the input current is:

0=dtdis (5.13)

168

• State (3) ( sss TDt

T)

23(

2−<< )

In this state, Q1 is on and Q2 is off. The derivatives of the input and the

transformer secondary currents are respectively:

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

+s

s

p vNN

ELdt

iid 21)( 21 (5.14)

ss

p

mss

ps vLN

NLL

ENN

dtdi

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅−=

112

(5.15)

• State (4) ( sss TtTD <<− )23( )

This state repeats State (2) and the derivatives of the input and the transformer

secondary currents are respectively given in Equations (5.11) and (5.13).

The current waveforms in the hard-switched two-inductor boost converter are shown

in Figure 5.4.

5.2 Integrated Magnetics with Magnetic Core Integration

A fundamental magnetic integration solution for the two-inductor boost converter is

to combine the three individual cores to a single core while still maintaining the four

169

individual windings including two for the inductors, one for the transformer primary

and one for the transformer secondary. This approach is named as Structure A as

shown in Figure 5.5 and the analysis is given below.

0 (1-Ds)Ts Ts/2 (3/2-Ds)Ts Ts (2-Ds)Ts 3Ts/2 (5/2-Ds)Ts 2Ts t




vQ1G

vQ2G

i1

i2

iIN


I0/2

I0/2

I0

Figure 5.4 Current Waveforms in the Hard-Switched Two-Inductor Boost Converter

5.2.1 Two-Inductor Boost Converter with Structure A Magnetic Integration

The two-inductor boost converter with Structure A magnetic integration is shown in

170

Figure 5.5.

D2

D1

CO2

CO1

R VO

+

−

vs+

−

isIO

E Q1

Q2

Np

NL

NL

Ns

φ1

φ2

φc

i1

i2

a

bvp+−

vL1+ −

vL2+ −

ip

Figure 5.5 Two-Inductor Boost Converter with Structure A Magnetic Integration

The KVL requires that the voltages across the three windings on the converter

primary side satisfy the following relationship:

12 LLp vvv −= (5.16)

Application of Faraday’s Law yields:

dtdN

dtdN

dtdN LL

cp

12 φφφ−= (5.17)

where NL is the number of turns of the two input inductors L1 and L2, and φ1, φ2, φc

171

are respectively the instantaneous fluxes in the two outer and the centre core legs

and they obey the following equation:

12 φφφ −=c (5.18)

Manipulations of Equations (5.17) and (5.18) yield:

Lp NN = (5.19)

Equation (5.19) is the inherent constraint of Structure A magnetic integration. If this

constraint is not fulfilled, the magnetic integration becomes impossible as Equation

(5.18) cannot be established in the magnetic core.

5.2.2 Equivalent Input and Transformer Magnetising Inductances

In order to obtain the equivalent input and transformer magnetising inductances of

the two-inductor boost converter with Structure A magnetic integration, the

converter must be analysed under three different operating conditions.

• State (1) ( ) 0>sv

In this state, Q1 is off while Q2 is on and i1 flows in the transformer primary

winding. The magnetic circuit is drawn in Figure 5.6(a), where ℜo and ℜc are

172

respectively the reluctances of the outer and the centre core legs. The fluxes in

the two outer core legs are respectively:

o

c

co

p

co

ss

o

c

co

p iNiNiNℜℜ⋅

ℜ+ℜ+

ℜ+ℜ+

ℜℜ⋅

ℜ+ℜ=

22221

1φ (5.20)

⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

+ℜ+ℜ

−⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

=o

c

co

p

co

ss

o

c

co

p iNiNiN1

221

221

2φ (5.21)

According to Figure 5.5, Faraday’s Law gives:

ss

pp v

NN

Edt

dN −=1φ (5.22)

Edt

dN p =2φ (5.23)

Substitution of Equations (5.20) and (5.21) to (5.22) and (5.23) yields:

⎟⎟⎠

⎞⎜⎜⎝

⎛−

ℜ=

+s

s

p

p

o vNN

ENdt

iid2

)(2

21 (5.24)

ss

co

sp

os vN

ENNdt

di2

ℜ+ℜ−

ℜ= (5.25)

By defining La and Lb as:

173

o

pa

NL

ℜ=

2

(5.26)

co

sb

NL

ℜ+ℜ=

22 2

(5.27)

Equations (5.24) and (5.25) can be simplified to:

⎟⎟⎠

⎞⎜⎜⎝

⎛−=

+s

s

p

a

vNN

ELdt

iid21)( 21 (5.28)

sas

p

bas

ps vLN

NLL

ENN

dtdi

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅=

211

2

(5.29)

• State (3) ( ) 0<sv

In this state, Q1 is on while Q2 is off and i2 flows in the transformer primary

winding. The magnetic circuit is drawn in Figure 5.6(b). The fluxes in the two

outer core legs are respectively:

⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

+ℜ+ℜ

+⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

=o

c

co

p

co

ss

o

c

co

p iNiNiN1

221

221

1φ (5.30)

o

c

co

p

co

ss

o

c

co

p iNiNiNℜℜ⋅

ℜ+ℜ+

ℜ+ℜ−

ℜℜ⋅

ℜ+ℜ=

22221

2φ (5.31)

According to Figure 5.5, Faraday’s Law gives:

174

EdtdN p =1φ (5.32)

ss

pp v

NN

Edt

dN +=2φ (5.33)


⎟⎟⎠

⎞⎜⎜⎝

⎛+

ℜ=

+s

s

p

p

o vNN

ENdt

iid2

)(2

21 (5.34)

ss

co

sp

os vN

ENNdt

di2

ℜ+ℜ−

ℜ−= (5.35)

Equations (5.34) and (5.35) can be simplified by the definitions of La and Lb in

Equations (5.26) and (5.27) to:

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

+s

s

p

a

vNN

ELdt

iid21)( 21 (5.36)

sas

p

bas

ps vLN

NLL

ENN

dtdi

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−−=

211

2

(5.37)

• States (2) and (4) ( 0=sv )

In these two states, Q1 and Q2 are both on and the transformer primary current is

175

zero. The magnetic circuit is drawn in Figure 5.6(c). The fluxes in the two outer

core legs are respectively:

o

c

co

p

o

c

co

p iNiNℜℜ⋅

ℜ+ℜ+⎟⎟

⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

=2

12

211φ (5.38)

⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

+ℜℜ⋅

ℜ+ℜ=

o

c

co

p

o

c

co

p iNiN1

2221

2φ (5.39)

Npi1

Npi1 Nsis

Npi2ℜo

ℜo

ℜc

φ1

φc

φ2

Npi1

Npi2 Nsis

Npi2ℜo

ℜo

ℜc

φ1

φc

φ2

Npi1

Npi2ℜo

ℜo

ℜc

φ1

φc

φ2

(a) (c)(b)+−

+−

+− +−

+−

+−+−

+−

+− +−

Figure 5.6 Structure A Magnetic Circuits

(a) State (1) (b) State (3) (c) States (2) and (4)

According to Figure 5.5, Faraday’s Law gives Equations (5.23), (5.32) and

(5.40):

sc

s vdt

dN =

φ (5.40)


176

ENdt

iid

p

o 2)(2

21 ℜ=

+ (5.41)

Equation (5.41) can be simplified by the definition of La in Equation (5.26) to:

ELdt

iid

a

21)( 21 =+

(5.42)

Manipulations of Equations (5.18), (5.23), (5.32) and (5.40) yield Equation

(5.12). Therefore, Equation (5.13) is still valid in this state.

Comparisons of Equations (5.28), (5.29), (5.36), (5.37) and (5.42) respectively with

their discrete magnetic counterparts, Equations (5.4), (5.10), (5.14), (5.15) and

(5.11), yield:

o

pa

NLL

ℜ==

2

(5.43)

c

s

as

p

b

msN

LNN

L

Lℜ

=

⎟⎟⎠

⎞⎜⎜⎝

⎛−

=2

2

211

1 (5.44)

Equations (5.43) and (5.44) imply that other than the number of turns, the input

inductances are inversely proportional to the reluctance of the outer core leg and the

magnetising inductance is inversely proportional to that of the centre core leg. This

normally requires that the outer core legs be gapped to store the energy in the input

177

inductors and prevent the core from saturation. The gapping of the centre core leg is

possible but not indispensable.

5.2.3 DC Gain

As the voltages across the two windings on the outer core legs are finite, the fluxes

in the two outer core legs must be continuous. This corresponds to the more familiar

statement that the current in the inductor must be continuous in the circumstance

with discrete magnetics.

Consider the flux in one outer core leg φ1. According to Figure 5.5, Faraday’s Law

gives Equation (5.22) in State (1) when Q1 is off and Equation (5.32) in States (2) to

(4) when Q1 is on. In State (1), the transformer secondary voltage can be found as:

21,O

ssV

vv == (5.45)

Therefore, Equation (5.22) can be rewritten as:

21 O

s

pp

VNN

EdtdN ⋅−=φ (5.46)

As the derivatives of the flux φ1 in Equations (5.32) and (5.46) are constants, the

change of the flux when Q1 is off, (∆φ1)Q1,off, and that when Q1 is on, (∆φ1)Q1,on, are

respectively:

178

p

ssO

s

p

offQ N

TDV

NN

E )1(2

)( ,11

−⎟⎟⎠

⎞⎜⎜⎝

⎛⋅−

=∆φ (5.47)

p

ssonQ N

TED=∆ ,11 )( φ (5.48)

Due to the continuity of the flux, the following equation can be obtained:

0)()( ,11,11 =∆+∆ onQoffQ φφ (5.49)

Substitution of Equations (5.47) and (5.48) to (5.49) and solving for VO yield:

EDN

NV

sp

sO −

⋅=1

2 (5.50)

Equation (5.50) validates that the two-inductor boost converter with Structure A

magnetic integration has the same dc voltage gain as the converter with discrete

magnetics.

5.2.4 DC and AC Flux Densities

In order to prevent the magnetic core from saturation, the peak flux density in each

core leg must be established. The ac fluxes must be also investigated in order for the

179

core loss analysis to be carried out. The dc and ac fluxes in each core leg will be

analysed separately.

First, the dc fluxes in the individual core legs are discussed. According to Figure

5.6(a), the instantaneous fluxes in the three core legs in State (1) are restricted by

Equations (5.18), (5.51) and (5.52):

INppoo iNiiN =+=ℜ+ℜ )( 2121 φφ (5.51)

sscco iN=ℜ−ℜ φφ1 (5.52)

Assuming that Φ1, Φ2, Φc, IIN and Is,1 are respectively the dc components of φ1, φ2,

φc, iIN and is in State (1), Equations (5.18), (5.51) and (5.52) can be rewritten with

the dc components of the variables as:

INpoo IN=Φℜ+Φℜ 21 (5.53)

1,1 sscco IN=Φℜ−Φℜ (5.54)

12 Φ−Φ=Φ c (5.55)

As the converter operation is half cycle symmetrical, the average powers at the

transformer secondary and the output must be equal over a half switching period that

includes States (1) and (2). The equation of the power balance is:

180

OOs

sssO IVT

TDIV=

−⋅

2)1(

21, (5.56)

Solving for Is,1 yields:

s

Os D

II

−=

11, (5.57)

The power balance at the input and the output gives:

OOIN IVEI = (5.58)

Manipulations of Equations (5.50), (5.57) and (5.58) yields:

21,IN

s

ps

INN

I ⋅= (5.59)

Substitution of Equation (5.59) to (5.54) yields:

21INp

cco

IN=Φℜ−Φℜ (5.60)

As Φ1, Φ2, Φc and IIN are also the dc components of φ1, φ2, φc and iIN over the entire

switching period, Equations (5.53), (5.55) and (5.60) are valid over the entire

switching period and the dc fluxes in the individual core legs can be solved as:

181

o

INp INℜ

=Φ=Φ221 (5.61)

0=Φ c (5.62)

From Equations (5.23) and (5.32), the ac fluxes in the two outer core legs can be

calculated as:

p

ss

NTED

=∆=∆ 21 φφ (5.63)

where ∆φ1 and ∆φ2 are respectively the total changes of the fluxes in the two outer

core legs.

If ∆φ1,1, ∆φ2,1 and ∆φc,1 are respectively defined as the changes of the fluxes in the

individual core legs in State (1) and ∆φ1,2, ∆φ2,2 and ∆φc,2 are respectively defined as

those in State (2), they can be calculated as:

p

ss

NTED

−=∆ 1,1φ (5.64)

p

ss

NTDE )1(

1,2−

=∆φ (5.65)

p

sc N

ET=∆−∆=∆ 1,11,21, φφφ (5.66)

182

p

ss

N

TDE ⎟⎠⎞

⎜⎝⎛ −

=∆=∆ 21

2,22,1 φφ (5.67)

02,12,22, =∆−∆=∆ φφφc (5.68)

As the flux in the centre core leg starts to decrease in State (3) and both the fluxes in

the two outer core legs change monotonically in either States (1) or (2), the total

change of the flux in the centre core leg is:

p

sccc N

ET=∆+∆=∆ 2,1, φφφ (5.69)

Therefore, the ac flux in the centre core leg is:

p

sc N

ET=∆φ (5.70)

From Equations (5.61) to (5.63) and (5.70), the peak flux density in each core leg

can be calculated as:

cp

ss

co

INp

ANTED

AIN

BB +ℜ

== max,2max,1 (5.71)

cp

sc AN

ETB

2max, = (5.72)

183

where Ac is the cross section area of the centre core leg. The cross section area of

the outer core leg is normally made to be half that of the centre core leg in ETD core

types.

The flux waveforms are shown in Figure 5.7. It can be seen that the dc fluxes in the

two outer core legs are cancelled while the ac fluxes are added together in the centre

core leg.

vQ1G

vQ2G

φ1

φ2

φc






Φ1

Φ2

Φc

Figure 5.7 Flux Waveforms in Structure A Core

184

5.2.5 Current Ripples

The current ripples in the MOSFETs and the magnetic windings affect the

conduction losses because under the same level of the dc component, the effective

current increases if the ripple current is higher.

If ∆iIN,1 and ∆is,1 are respectively defined as the changes of the input and the

transformer secondary currents iIN and is in State (1), Equations (5.51) and (5.52) can

be rewritten with the ac components of the variables in State (1) as:

p

ooIN N

i 1,21,11,

φφ ∆ℜ+∆ℜ=∆ (5.73)

s

ccos N

i 1,1,11,

φφ ∆ℜ−∆ℜ=∆ (5.74)

As the input current starts to decrease in State (2) and the transformer secondary

current is zero in State (2), ∆iIN,1 and ∆is,1 are also ∆iIN and ∆is, the total changes of

iIN and is. Substitution of Equations (5.64), (5.65) and (5.66) to (5.73) and (5.74)

yields:

21,)21(

p

sosININ N

ETDii

ℜ−=∆=∆ (5.75)

21,)(

p

scos

s

pss N

ETDNN

iiℜ+ℜ

⋅−=∆=∆ (5.76)

185

If ∆i1,1, ∆ip,1, ∆is1,1 and ∆is2,1 are respectively defined as the changes of the currents

i1, ip, is1 and is2 in State (1), Equations (5.5), (5.6), (5.8) and (5.9) can be rewritten

with the ac variables in State (1) as:

1,1,1 ps

ps i

NN

i ∆=∆ (5.77)

1,11, ii p ∆=∆ (5.78)

ms

ssss L

TDvi

)1(1,1,2

−−=∆ (5.79)

1,21,11, sss iii ∆+∆=∆ (5.80)

Substitution of Equations (5.44), (5.45), (5.50) and (5.76) to (5.77), (5.78), (5.79)

and (5.80) yields:

21,1p

sos

NETD

iℜ

−=∆ (5.81)

As the current i1 starts to increase in State (2) and the converter operation is half

cycle symmetrical, ∆i1,1 is also ∆i1 or ∆i2, the total change of i1 or i2. The current

ripples of iIN, i1, i2 and is are respectively:

2

)12(

p

sosIN N

ETDi

ℜ−=∆ (5.82)

186

221p

sos

NETD

iiℜ

=∆=∆ (5.83)

2

)(

p

scos

s

ps N

ETDNN

iℜ+ℜ

⋅=∆ (5.84)

The current waveforms are the same as those in the converter with discrete

magnetics shown in Figure 5.4.

5.3 Integrated Magnetics with Winding Integration

In order to further reduce the number of interconnections between the individual

windings as well as the copper loss and the winding cost, winding integration is

proposed as a better approach in magnetic integration [155]. This section studies

three magnetic integration solutions with winding integration technique for the two-

inductor boost converter.

5.3.1 Winding Integration Technique

In the two-inductor boost converter, the transformer primary winding can be merged

with the individual inductor windings and the two combined windings must be

located on the two outer legs of a three-leg core to achieve the symmetrical

operation. Each combined winding functions as both the input inductor and the

transformer primary windings in the converter with discrete magnetics.

Topographically, there are four ways to wind the two combined windings onto the

187

two outer core legs and the directions of the induced fluxes φ1 and φ2 have four

different combinations as shown in Figure 5.8.

φ1

φ2

i1

i2

E

φ1

φ2

i1

i2

E

(a) (b)

φ1

φ2

i1

i2

E

φ1

φ2i2

E

(c) (d)

i1

Figure 5.8 Four Ways to Wind the Two Combined Windings

According to the directions of the flux changes in the individual core legs, the

number of the winding structures can be finally reduced to two, as shown in Figures

5.8(a) and (b). The winding structure in Figure 5.8(c) is equivalent to that in Figure

5.8(b) while that in Figure 5.8(d) is equivalent to that in Figure 5.8(a). In Figure

5.8(a), the flux changes generated by the two individual windings are of the same

direction in the two outer core legs and of different directions in the centre core leg.

In Figure 5.8(b), the flux changes generated by the two individual windings are of

188

different directions in the two outer core legs and of the same direction in the centre

core leg.

As the flux in the transformer secondary winding must be alternating, the secondary

winding must be placed on the centre core leg in Figure 5.8(a) and on the two outer

core legs in Figure 5.8(b). In these arrangements, the currents in the two windings

on the outer core legs can be alternatively switched on so that an alternating flux can

be generated in the transformer secondary winding.

5.3.2 Structure B Magnetic Integration

The approach which uses single secondary winding on the centre core leg is named

as Structure B, as shown in Figure 5.9. In Figure 5.9, the locations of the MOSFETs

Q1 and Q2 are changed and Q1 is in series with the bottom combined winding while

Q2 is in series with the top combined winding. This arrangement maintains the

relationship of the closings of the MOSFETs and the direction of the transformer

secondary current. In the two-inductor boost converter with discrete magnetics, the

closing of Q2 results in a positive transformer secondary current as illustrated in

Figure 5.1. In the converter with integrated magnetics, the windings on the outer

core legs integrate the functions of the input inductor and the transformer primary

windings and the closing of Q2 also results in a positive transformer secondary

current as illustrated in Figure 5.9. The magnetic circuits of Structure B in different

states are drawn in Figure 5.10.

189

a

φ1

φ2

i1

i2

E

Q1

Q2

Np

Np

vs+

−

isNs

φc

D2

D1

CO2

CO1

R VO

+

−

IO

b

Figure 5.9 Two-Inductor Boost Converter with Structure B Magnetic Integration

Npi1

Nsis

ℜo

ℜo

ℜc

φ1

φc

φ2

(a)

+−

+−Nsis

Npi2ℜo

ℜo

ℜc

φ1

φc

φ2

+−

+−

Npi1

Npi2ℜo

ℜo

ℜc

φ1

φc

φ2

+−

+−

(c)(b)

Figure 5.10 Structure B Magnetic Circuits


The converter is now analysed under three different operating conditions.

• State (1) ( ) 0>sv

In this state, Q1 is off while Q2 is on and 02 =i . The fluxes in one outer and the

190

centre core legs are respectively:

co

ss

o

c

co

p iNiNℜ+ℜ

−⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

=2

12

11φ (5.85)

co

ss

co

pc

iNiNℜ+ℜ

−ℜ+ℜ

=2

22

1φ (5.86)

According to Figure 5.9, Faraday’s Law gives Equations (5.32) and (5.40).

Substitution of Equations (5.85) and (5.86) to (5.32) and (5.40) yields Equations

(5.28) and (5.29).

• State (3) ( ) 0<sv

In this state, Q1 is on while Q2 is off and 01 =i . The fluxes in one outer and the

centre core legs are respectively:

co

ss

o

c

co

p iNiNℜ+ℜ

+⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

=2

12

22φ (5.87)

co

ss

co

pc

iNiNℜ+ℜ

−ℜ+ℜ

−=2

22

2φ (5.88)


Substitution of Equations (5.87) and (5.88) to (5.23) and (5.40) yields Equations

(5.36) and (5.37).

191

• States (2) and (4) ( 0=sv )

In these two states, Q1 and Q2 are both on. According to Figure 5.9, Faraday’s

Law gives Equations (5.23), (5.32) and (5.40). The fluxes in the individual core

legs also obey the following equation:

cφφφ += 21 (5.89)

The fluxes in the two outer core legs are respectively given in Equations (5.38)

and (5.39) and substitution of Equations (5.38) and (5.39) to (5.23) and (5.32)

yields Equation (5.41). Manipulations of Equations (5.23), (5.32), (5.40) and

(5.89) yield Equation (5.12). Therefore, Equation (5.13) is still valid in this

state.

As the derivatives of the input and the transformer secondary currents in the

individual operating conditions in Structure B are the same as those in Structure A,

the equivalent input inductances and magnetising inductance are the same as those

given in Equations (5.43) and (5.44). Therefore, this magnetic structure also

requires that the outer core legs be gapped to store the energy in the input inductors.

Like the gapping arrangement of the centre core leg in Structure A, the gapping of

the centre core leg is possible but not indispensable in Structure B.

192

5.3.3 Structures C and D Magnetic Integration

The approach which uses two secondary windings on the two outer core legs is

named as Structure C, as shown in Figure 5.11 [130], [144], [145]. In Figure 5.11,

the MOSFETs Q1 and Q2 have the same locations as those in Figure 5.9. The

magnetic circuits of Structure C in different states are drawn in Figure 5.12.

φ1

φ2

i1E

Q1

Q2

Np

Np

+is

Ns

φc−

Ns

i2

D2

D1

CO2

CO1

R VO

+

−

IO

a

bvs

Figure 5.11 Two-Inductor Boost Converter with Structure C Magnetic Integration

Npi1 Nsis

ℜo

ℜo

ℜc

φ1

φc

φ2

(a)

Nsis

+− +−

+−

Nsis

Npi2ℜo

ℜo

ℜc

φ1

φc

φ2

(b)

Nsis

+−

+−+−

Npi1

Npi2ℜo

ℜo

ℜc

φ1

φc

φ2

(c)

+−

+−

Figure 5.12 Structure C Magnetic Circuits


193


• State (1) ( ) 0>sv

In this state, Q1 is off while Q2 is on and 02 =i . The fluxes in the two outer core

legs are respectively:

o

ss

o

c

co

p iNiNℜ

−⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

= 12

11φ (5.90)

o

ss

o

c

co

p iNiNℜ

+ℜℜ⋅

ℜ+ℜ−=

21

2φ (5.91)

According to Figure 5.11, Faraday’s Law gives Equations (5.32) and (5.92):

sss vdt

dN

dtd

N =− 21 φφ (5.92)


⎟⎟⎠

⎞⎜⎜⎝

⎛−

ℜ+ℜ=

+s

s

p

p

co vNN

ENdt

iid2

2)(2

21 (5.93)

ss

co

sp

cos vN

ENNdt

di2

2 ℜ+ℜ−

ℜ+ℜ= (5.94)

194

By defining Lc and Ld as:

co

pc

NL

ℜ+ℜ=

2

2

(5.95)

o

sd

NL

ℜ=

22 (5.96)


⎟⎟⎠

⎞⎜⎜⎝

⎛−=

+s

s

p

c

vNN

ELdt

iid21)( 21 (5.97)

scs

p

dcs

ps vLN

NLL

ENN

dtdi

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅=

211

2

(5.98)

• State (3) ( ) 0<sv

In this state, Q1 is on while Q2 is off and 01 =i . The fluxes in the two outer core

legs are respectively:

o

ss

o

c

co

p iNiNℜ

−ℜℜ⋅

ℜ+ℜ−=

22

1φ (5.99)

o

ss

o

c

co

p iNiNℜ

+⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

= 12

22φ (5.100)

195



⎟⎟⎠

⎞⎜⎜⎝

⎛+

ℜ+ℜ=

+s

s

p

p

co vNN

ENdt

iid2

2)(2

21 (5.101)

ss

co

sp

cos vN

ENNdt

di2

2 ℜ+ℜ−

ℜ+ℜ−= (5.102)

Equations (5.101) and (5.102) can be simplified by the definitions of Lc and Ld

in Equations (5.95) and (5.96) to:

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

+s

s

p

c

vNN

ELdt

iid21)( 21 (5.103)

scs

p

dcs

ps vLN

NLL

ENN

dtdi

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅−=

211

2

(5.104)

• States (2) and (4) ( 0=sv )

In these two states, Q1 and Q2 are both on. The fluxes in the two outer core legs

are respectively:

o

c

co

p

o

c

co

p iNiNℜℜ⋅

ℜ+ℜ−⎟⎟

⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

=2

12

211φ (5.105)

196

⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

+ℜℜ⋅

ℜ+ℜ−=

o

c

co

p

o

c

co

p iNiN1

2221

2φ (5.106)

According to Figure 5.11, Faraday’s Law gives Equations (5.23), (5.32) and

(5.92). The fluxes in the individual core legs also obey the following equation:

21 φφφ +=c (5.107)


ENdt

iid

p

co 22)(2

21 ℜ+ℜ=

+ (5.108)

Equation (5.108) can be simplified by the definition of Lc in Equation (5.95) to:

ELdt

iid

c

21)( 21 =+

(5.109)



Comparisons of Equations (5.97), (5.98), (5.103), (5.104) and (5.109) respectively

with their discrete magnetic counterparts, Equations (5.4), (5.10), (5.14), (5.15) and

(5.11), yield:

197

co

pc

NLL

ℜ+ℜ==

2

2

(5.110)

c

s

cs

p

d

msN

LNN

L

Lℜ

−=

⎟⎟⎠

⎞⎜⎜⎝

⎛−

=2

2

211

1 (5.111)


inductances are related to the reluctances of both the outer and the centre core legs

and the magnetising inductance is inversely proportional to that of the centre core

leg only. In this magnetic structure, the centre core leg can be gapped to store the

energy in the input inductors. The gapping of the outer core legs is possible but not

indispensable. If the centre core leg is the only gapped leg, the input inductances

can be estimated to be inversely proportional to the reluctance of the centre core leg

as in this case. oc ℜ>>ℜ

According to the flux directions specified in Structure C in Figure 5.11, the increase

or the decrease of the flux in the centre core leg results in the increase or the

decrease of both the fluxes in the two outer core legs. Therefore, a variation of this

magnetic structure can be developed by placing another winding in the centre core

leg in series with one of the two combined windings in the converter primary side

when only one MOSFET is on. This approach is named as Structure D. Figure 5.13

shows the circuit diagram of the two-inductor boost converter with Structure D

magnetic integration. The magnetic circuits of Structure D in different states are

drawn in Figure 5.14.

198

φ1

φ2

i1

EQ1

Q2

Np

Np

Ns

φc

Ns

i2

Nc+

is

−D2

D1

CO2

CO1

R VO

+

−

IO

a

bvs

Figure 5.13 Two-Inductor Boost Converter with Structure D Magnetic Integration

Npi1 Nsis

ℜo

ℜo

ℜc

φ1

φc

φ2

(a)

Nsis

Nci1

+− +−

+−

+−

Nsis

Npi2ℜo

ℜo

ℜc

φ1

φc

φ2

(b)

Nsis

Nci2

+−

+−+−

+−

Npi1

Npi2ℜo

ℜo

ℜc

φ1

φc

φ2

(c)

Nc(i1+i2)

+−

+−

+−

Figure 5.14 Structure D Magnetic Circuits



• State (1) ( ) 0>sv

In this state, Q1 is off while Q2 is on and 02 =i . If Nc is the number of the turns

of the centre core leg winding, the fluxes in the three core legs are respectively:

199

o

ssc

o

cp

co

iNNN

iℜ

−⎥⎦

⎤⎢⎣

⎡+⎟⎟

⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

= 12

11φ (5.112)

o

ssc

o

cp

co

iNNN

iℜ

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

ℜℜ

−ℜ+ℜ

=2

12φ (5.113)

co

cpc

iNNℜ+ℜ

+=

2)2( 1φ (5.114)


Edt

dN

dtd

N ccp =+

φφ1 (5.115)

Substitution of Equations (5.112), (5.113) and (5.114) to (5.92) and (5.115)

yields:

⎟⎟⎠

⎞⎜⎜⎝

⎛−

+ℜ+ℜ

=+

ss

p

cp

co vNN

ENNdt

iid2

)2(2)(

221 (5.116)

scp

co

s

p

s

o

cp

co

s

ps vNNN

NN

ENNN

Ndtdi

⎥⎥⎦

⎤

⎢⎢⎣

⎡

+ℜ+ℜ

⎟⎟⎠

⎞⎜⎜⎝

⎛+

ℜ−

+ℜ+ℜ

⋅= 2

2

22 )2(22

2)2(2

(5.117)

With the definition of Ld in Equation (5.96) and by defining Le as:

co

cpe

NNL

ℜ+ℜ

+=

2)2( 2

(5.118)

200


⎟⎟⎠

⎞⎜⎜⎝

⎛−=

+s

s

p

e

vNN

ELdt

iid21)( 21 (5.119)

ses

p

des

ps vLN

NLL

ENN

dtdi

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅=

211

2

(5.120)

• State (3) ( ) 0<sv

In this state, Q1 is on while Q2 is off and 01 =i . The fluxes in the three core legs

are respectively:

o

ssc

o

cp

co

iNNN

iℜ

−⎟⎟⎠

⎞⎜⎜⎝

⎛+

ℜℜ

−ℜ+ℜ

=2

21φ (5.121)

o

ssc

o

cp

co

iNNNi

ℜ+⎥

⎦

⎤⎢⎣

⎡+⎟⎟

⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

= 12

22φ (5.122)

co

cpc

iNNℜ+ℜ

+=

2)2( 2φ (5.123)


Edt

dN

dtd

N ccp =+

φφ2 (5.124)

201

Substitution of Equations (5.121), (5.122) and (5.123) to (5.92) and (5.124)

yields:

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+ℜ+ℜ

=+

ss

p

cp

co vNN

ENNdt

iid2

)2(2)(

221 (5.125)

scp

co

s

p

s

o

cp

co

s

ps vNNN

NN

ENNN

Ndtdi

⎥⎥⎦

⎤

⎢⎢⎣

⎡

+ℜ+ℜ

⎟⎟⎠

⎞⎜⎜⎝

⎛+

ℜ−

+ℜ+ℜ

⋅−= 2

2

22 )2(22

2)2(2

(5.126)

Equations (5.125) and (5.126) can be simplified with the definitions of Ld and Le

in Equations (5.96) and (5.118) to:

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

+s

s

p

e

vNN

ELdt

iid21)( 21 (5.127)

ses

p

des

ps vLN

NLL

ENN

dtdi

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅−=

211

2

(5.128)

• States (2) and (4) ( 0=sv )

In these two states, Q1 and Q2 are both on. The fluxes in the three core legs are

respectively:

⎟⎟⎠

⎞⎜⎜⎝

⎛−

ℜℜ

ℜ+ℜ−⎥

⎦

⎤⎢⎣

⎡+⎟⎟

⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

= co

cp

coc

o

cp

co

NNi

NNi

21

221

1φ (5.129)

202

⎥⎦

⎤⎢⎣

⎡+⎟⎟

⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

ℜℜ

−ℜ+ℜ

= co

cp

coc

o

cp

co

NNi

NNi

122

212φ (5.130)

co

cpc

iiNNℜ+ℜ

++=

2))(2( 21φ (5.131)

According to Figure 5.13, Equations (5.92), (5.107), (5.115) and (5.124) can be

established. Substitution of Equations (5.129), (5.130) and (5.131) to (5.115)

and (5.124) yields:

ENNdt

iid

cp

co 2)2(

2)(2

21

+ℜ+ℜ

=+ (5.132)

Equation (5.132) can be simplified by the definition of Le in Equation (5.118) as:

ELdt

iid

e

21)( 21 =+

(5.133)




with their discrete magnetic counterparts, Equations (5.4), (5.10), (5.14), (5.15) and

(5.11), yield:

203

co

cpe

NNLL

ℜ+ℜ

+==

2)2( 2

(5.134)

)2(2

2

211

12

2

2

cocp

po

s

es

p

d

ms

NNN

N

LNN

L

L

ℜ+ℜ⎟⎟⎠

⎞⎜⎜⎝

⎛

+−ℜ

=

⎟⎟⎠

⎞⎜⎜⎝

⎛−

= (5.135)


and the magnetising inductances are related to the reluctances of both the outer and

the centre core legs. In this magnetic structure, the gapping arrangement is the same

as that in Structure C and the input inductances can be estimated to be inversely

proportional to the reluctance of the centre core leg if only the centre core leg is

gapped. The extra winding on the centre core leg in this magnetic integration

structure provides additional input filtering inductance to the input current and one

winding turn on the centre core leg is effective as two winding turns on the outer

core leg in the contribution to the input inductances according to Equation (5.134).

5.4 Comparisons of the Four Magnetic Integration Structures

In this section, a set of parameters including the dc gain, the dc and ac flux densities

in the three core legs and the current ripples in the individual windings will be

established and comparisons will be made for the four magnetic structures.

204

5.4.1 Structure A Magnetic Integration

The individual parameters have been established in Section 5.2 and will not be

repeated here. The parameters of the remaining three magnetic structures will be

derived with the same approaches.

5.4.2 Structure B Magnetic Integration

According to Figure 5.9, Faraday’s Law gives Equations (5.23) and (5.40) in State

(3) when Q2 is off and Equation (5.32) in States (1), (2) and (4) when Q2 is on.

Manipulations of Equations (5.23), (5.40) and (5.89) yield:

ss

pp v

NN

EdtdN +=1φ (5.136)

In State (3), the transformer secondary voltage can be found as:

23,O

ssV

vv −== (5.137)

Therefore, Equation (5.136) can be rewritten as Equation (5.46). The change of the

flux when Q2 is off, (∆φ1)Q2,off and that when Q2 is on, (∆φ1)Q2,on, are respectively:

205

p

ssO

s

p

offQ N

TDV

NN

E )1(2

)( ,21

−⎟⎟⎠

⎞⎜⎜⎝

⎛⋅−

=∆φ (5.138)

p

ssonQ N

TED=∆ ,21 )( φ (5.139)


0)()( ,21,21 =∆+∆ onQoffQ φφ (5.140)

Substitution of Equations (5.138) and (5.139) to (5.140) and solving for VO yield

Equation (5.50).

According to Figure 5.10(a), the instantaneous fluxes in the three core legs in State

(1) are restricted by Equations (5.89), (5.141) and (5.142):

INppoo iNiN ==ℜ+ℜ 121 φφ (5.141)

sscco iN=ℜ−ℜ φφ2 (5.142)

Equations (5.141), (5.142) and (5.89) can be respectively rewritten with the dc

components of the variables as Equations (5.53), (5.143) and (5.144), which are

valid over the entire switching period:

206

22INp

cco

IN=Φℜ−Φℜ (5.143)

cΦ+Φ=Φ 21 (5.144)

The dc fluxes in the individual core legs can be calculated from Equations (5.53),

(5.143) and (5.144) and they are the same as those in Structure A, which are given in

Equations (5.61) and (5.62).

The ac fluxes in the two outer core legs are the same as those in Structure A, which

are given in (5.63). The changes of the fluxes in the individual core legs in State (1)

∆φ1,1, ∆φ2,1 and ∆φc,1 are respectively:

p

ss

NTDE )1(

1,1−

=∆φ (5.145)

p

ss

NTED

−=∆ 1,2φ (5.146)

p

sc N

ET=∆−∆=∆ 1,21,11, φφφ (5.147)

The changes of the fluxes in the two outer core legs in State (2) ∆φ1,2 and ∆φ2,2 are

the same as those in Structure A, which are given in Equation (5.67). The change of

the flux in the centre core legs in State (2) ∆φc,2 can then be calculated as:

02,22,12, =∆−∆=∆ φφφc (5.148)

207

As the flux in the centre core leg starts to decrease in State (3), the ac flux can be

calculated from Equations (5.147) and (5.148). It can be calculated that the ac flux

in the centre core leg is the same as that in Structure A, which is given in Equation

(5.70). As both the dc and ac fluxes are the same as those in Structure A, the peak

flux densities in the individual core legs are the same as those in Structure A, which

are given in Equations (5.71) and (5.72).

In order to find the input and the transformer secondary current ripples, Equations

(5.141) and (5.142) must be rewritten with the ac components of the variables in

State (1) to Equations (5.73) and (5.149):

s

ccos N

i 1,1,21,

φφ ∆ℜ−∆ℜ=∆ (5.149)

After substitution of Equations (5.145), (5.146) and (5.147) to (5.73) and (5.149),

the current ripples can be found to be the same as those in Structure A, which are

given in Equations (5.82) and (5.84).

The flux and the current waveforms are shown in Figure 5.15. It can be seen that in

Structure B, the dc fluxes in the two outer core legs are cancelled and the ac fluxes

are added together in the centre core leg.

208

vQ1G

vQ2G

φ1

φ2

φc

iIN

i1

i2

IIN

IIN/2

IIN/2

IIN

IIN









Φ1

Φ2

Φc

Figure 5.15 Flux and the Current Waveforms in Structure B

209

5.4.3 Structure C Magnetic Integration

According to Figure 5.11, Faraday’s Law gives Equations (5.23) and (5.92) in State

(3) when Q2 is off and Equation (5.32) in States (1), (2) and (4) when Q2 is on.

Manipulations of Equations (5.23) and (5.92) yield Equation (5.136). The change of

the flux when Q2 is off, (∆φ1)Q2,off and that when Q2 is on, (∆φ1)Q2,on, are respectively

given in Equations (5.138) and (5.139) and the output voltage VO can be calculated

as given in Equation (5.50).


(a) are restricted by Equations (5.107), (5.150) and (5.151):

ssINpsspcco iNiNiNiN −=−=ℜ+ℜ 11 φφ (5.150)

sscco iN=ℜ+ℜ φφ2 (5.151)


components of the variables as Equations (5.152) to (5.154), which are valid over

the entire switching period:

21INp

cco

IN=Φℜ+Φℜ (5.152)

22INp

cco

IN=Φℜ+Φℜ (5.153)

21 Φ+Φ=Φ c (5.154)

210

The dc fluxes in the individual core legs can be solved as:

)2(221co

INp INℜ+ℜ

=Φ=Φ (5.155)

co

INpc

INℜ+ℜ

=Φ2

(5.156)

The ac fluxes in the two outer core legs are the same as those in Structure A, which

are given in (5.63). The changes of the fluxes in the individual core legs in State (1)

∆φ1,1, ∆φ2,1 are the same as those in Structure B, which are given in Equations

(5.145) and (5.146). The change of the flux in the centre core leg in State (1) ∆φc,1

can then be calculated as:

p

ssc N

TDE )21(1,21,11,

−=∆+∆=∆ φφφ (5.157)

As the flux in the centre core leg starts to increase in State (2), the total change of

the flux in the centre core leg is:

p

sscc N

TDE )12(1,

−=∆=∆ φφ (5.158)

The peak flux densities in the individual core legs can be calculated as:

211

cp

ss

cco

INp

ANTED

AIN

BB +ℜ+ℜ

==)2(max,2max,1 (5.159)

cp

ss

cco

INpc AN

TDEA

INB

2)12(

)2(max,−

+ℜ+ℜ

= (5.160)


(5.150) and (5.151) are manipulated and rewritten with the ac components of the

variables in State (1) as:

p

ccooIN N

i 1,1,21,11,

2 φφφ ∆ℜ+∆ℜ+∆ℜ=∆ (5.161)

s

ccos N

i 1,1,21,

φφ ∆ℜ+∆ℜ=∆ (5.162)

As ∆iIN,1 and ∆is,1 are also the total change of the currents iIN and is over the entire

switching period, substitution of Equations (5.145), (5.146) and (5.157) to (5.161)

and (5.162) yields:

2

)2)(21(

p

scosIN N

ETDi

ℜ+ℜ−=∆ (5.163)

[ ]2

)12(

p

scsos

s

ps N

ETDDNN

iℜ−+ℜ

⋅−=∆ (5.164)

The input and transformer secondary current ripples are respectively:

212

2

)2)(12(

p

scosIN N

ETDi

ℜ+ℜ−=∆ (5.165)

[ ]2

)12(

p

scsos

s

ps N

ETDDNN

iℜ−+ℜ

⋅=∆ (5.166)

The flux and the current waveforms are shown in Figure 5.16. It can be seen that in

Structure C, the dc fluxes in the two outer core legs are added together and the ac

fluxes are partially cancelled in the centre core leg. This leads to a much lower core

loss in the centre core leg as the core loss increases at a rate much faster than the

linear relationship of the ac flux density [165]. Structure C therefore becomes a

more attractive design than Structures A and B in terms of the core loss. The core

saturation will not be an issue since the cross section area of the centre core leg is

twice that of the outer core leg. Under the symmetrical operation, the dc flux

density in the centre core leg equals to those in the two outer core legs.

5.4.4 Structure D Magnetic Integration

According to Figure 5.13, Equations (5.92), (5.107) and (5.115) are valid in State (1)

when Q2 is on and Q1 is off. Manipulations of Equations (5.92), (5.107) and (5.115)

yield:

ss

ccp v

NN

Edtd

NN +=+ 1)2(φ

(5.167)

213








vQ1G

vQ2G

φ1

φ2

φc

iIN

i1

i2

IIN

IIN/2

IIN/2

IIN

IIN


Φ1

Φ2

Φc

Figure 5.16 Flux and the Current Waveforms in Structure C

214

Equations (5.107), (5.115) and (5.124) are valid in States (2) and (4) when both Q1

and Q2 are on. Manipulations of Equations (5.107), (5.115) and (5.124) yield:

Edtd

NN cp =+ 1)2(φ

(5.168)

Equations (5.92), (5.107) and (5.124) are valid in State (3) when Q2 is off and Q1 is

on. Manipulations of Equations (5.92), (5.107) and (5.124) yield:

ss

cpcp v

NNN

EdtdNN

++=+ 1)2( φ (5.169)

As Equations (5.45) and (5.138) are respectively valid in States (1) and (3), the

derivatives of the fluxes in Equations (5.167) to (5.169) are constants. If ∆φ1,j is

defined as the change of the flux in one outer core leg in State (j), where

, it can be calculated that: 4,3,2,1=j

)2(

)1(2

1,1cp

ssO

s

c

NN

TDV

NN

E

+

−⎟⎟⎠

⎞⎜⎜⎝

⎛⋅+

=∆φ (5.170)

)2()12(

4,12,1cp

ss

NNTDE

+−

=∆+∆ φφ (5.171)

)2(

)1(2

3,1cp

ssO

s

cp

NN

TDV

NNN

E

+

−⎟⎟⎠

⎞⎜⎜⎝

⎛⋅

+−

=∆φ (5.172)

215


04

1,1 =∆∑

=jjφ (5.173)

Substitution of Equations (5.170), (5.171) and (5.172) to (5.173) and solving for VO

yield Equation (5.50). The number of turns of the extra winding in the centre core

leg Nc does not appear in the output voltage equation. This implies that while the

winding in the centre core leg in Structure D provides additional input inductance, it

does not affect the dc gain of the converter. Therefore, this magnetic integration

structure offers another degree of freedom in controlling the input current ripples.


(1) are restricted by Equations (5.107), (5.174) and (5.175):

ssINcpsscpcco iNiNNiNiNN −+=−+=ℜ+ℜ )()( 11 φφ (5.174)

ssINcssccco iNiNiNiN +=+=ℜ+ℜ 12 φφ (5.175)


components of the variables as Equations (5.154), (5.176) and (5.177), which are

valid over the entire switching period:

INcINp

cco ININ

+=Φℜ+Φℜ21 (5.176)

216

INcINp

cco ININ

+=Φℜ+Φℜ22 (5.177)

From Equations (5.154), (5.176) and (5.177), the dc fluxes in the individual core

legs can be solved as:

)2(2)2(

21co

INcp INNℜ+ℜ

+=Φ=Φ (5.178)

co

INcpc

INNℜ+ℜ

+=Φ

2)2(

(5.179)

As φ1 increases in States (1), (2) and (4) and decreases in State (3), ∆φ1,3 is also the

total change of the flux in each of the two outer core legs. Substitution of Equation

(5.50) to (5.172) yields:

)2(3,121cp

sp

cs

NN

TNN

DE

+

⎟⎟⎠

⎞⎜⎜⎝

⎛+

=∆=∆=∆ φφφ (5.180)

The change of the flux in State (1) ∆φ2,1 is:

)2(

)1(2

1,2cp

ssO

s

cp

NN

TDV

NNN

E

+

−⎥⎦

⎤⎢⎣

⎡⋅

+−

=∆φ (5.181)

217

After substitution of Equation (5.50) to (5.170) and (5.181), the change of the flux in

the centre core leg in State (1) ∆φc,1 can be calculated as:

cp

ssc NN

TDE2

)21(1,21,11, +

−=∆+∆=∆ φφφ (5.182)

As the flux in the centre core leg starts to increase in State (2), the total change of

the flux in the centre core leg is:

cp

sscc NN

TDE2

)12(1, +

−=∆=∆ φφ (5.183)

The peak flux densities in the individual core legs can be calculated as:

ccp

sp

cs

cco

INcp

ANN

TNN

DE

AINN

BB)2()2(

)2(max,2max,1 +

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+ℜ+ℜ

+== (5.184)

ccp

ss

cco

INcpc ANN

TDEAINN

B)2(2

)12()2()2(

max, +−

+ℜ+ℜ

+= (5.185)


(5.174) and (5.175) are rewritten with the ac components of the variables in State (1)

as:

218

1,1,1,1,1 )( ssINcpcco iNiNN ∆−∆+=∆ℜ+∆ℜ φφ (5.186)

1,1,1,1,2 ssINcco iNiN ∆+∆=∆ℜ+∆ℜ φφ (5.187)

As ∆iIN,1 and ∆is,1 are also the total changes of the currents iIN and is over the entire

switching period, manipulations of Equations (5.170), (5.181), (5.182), (5.186) and

(5.187) yield:

21, )2()2)(21(

cp

scosININ NN

ETDii

+ℜ+ℜ−

=∆=∆ (5.188)

2

2

2

1, )2(

)12(22

cp

scsop

c

p

cs

s

pss NN

ETDNN

NN

D

NN

ii+

⎥⎥⎦

⎤

⎢⎢⎣

⎡ℜ−+ℜ⎟

⎟⎠

⎞⎜⎜⎝

⎛++

⋅−=∆=∆ (5.189)

The input and transformer secondary current ripples are respectively:

2)2()2)(12(

cp

scosIN NN

ETDi

+ℜ+ℜ−

=∆ (5.190)

2

2

2

)2(

)12(22

cp

scsop

c

p

cs

s

ps NN

ETDNN

NN

D

NN

i+

⎥⎥⎦

⎤

⎢⎢⎣

⎡ℜ−+ℜ⎟

⎟⎠

⎞⎜⎜⎝

⎛++

⋅=∆ (5.191)

The flux and the current waveforms are the same as shown in Figure 5.16.

219

5.4.5 Comparisons

Some important parameters of the four integrated magnetic structures are compared

in Table 5.1, where fs, NI, NII, NIII, ℜI, ℜII, ℜIII, DI, DII, DIII, DIV and DV are

respectively defined as:

ss T

f 1= (5.192)

pI NN = (5.193)

sII NN = (5.194)

cpIII NNN 2+= (5.195)

oI ℜ=ℜ (5.196)

cII ℜ=ℜ (5.197)

coIII ℜ+ℜ=ℜ 2 (5.198)

sI DD = (5.199)

sII DD −=1 (5.200)

12 −= sIII DD (5.201)

p

csIV N

NDD += (5.202)

2

222

p

c

p

csV N

NNNDD ++= (5.203)

220

Item Structure A Structure B Structure C Structure D

Number of Windings 4 3 4 5

Input Inductance

L I

INℜ

2

I

INℜ

2

III

INℜ

2

III

IIINℜ

2

Magnet-ising

Inductance Lms

II

IINℜ

2

II

IINℜ

2

II

IINℜ

−2

III

III

II

II

NNN

ℜ−ℜ 2

2

22

DC Gain EVO

III

II

DNN 2

⋅ III

II

DNN 2

⋅ III

II

DNN 2

⋅ III

II

DNN 2

⋅

Peak Flux Density B1,max, B2,max

scI

I

cI

INI

fANED

AIN

+ℜ

scI

I

cI

INI

fANED

AIN

+ℜ scI

I

cIII

INI

fANED

AIN

+ℜ

scIII

IV

cIII

INIII

fANED

AIN

+ℜ

Peak Flux Density Bc,max scI fAN

E2

scI fAN

E2

scI

III

cIII

INI

fANED

AIN

2+

ℜ

scIII

III

cIII

INIII

fANED

AIN

2+

ℜ

Current Ripple ∆iIN sI

IIII

fNED

2

ℜ

sI

IIII

fNED

2

ℜ

sI

IIIIII

fNED

2

ℜ

sIII

IIIIII

fNED

2

ℜ

Current Ripple ∆is

EfN

DNN

sI

IIII

II

I2

ℜ+ℜ

EfN

DNN

sI

IIII

II

I2

ℜ+ℜ

EfNDD

NN

sI

IIIIIII

II

I2

ℜ+ℜ EfNDD

NN

sIII

IIIIIIV

II

I2

ℜ+ℜ

Leakage Inductance Low High Medium Medium

Core Loss High High Low Low

Minimum Gapped

Legs

Two outer core legs

Two outer core legs Centre core leg Centre core leg

Table 5.1 Comparisons of the Four Integrated Magnetic Structures

221

5.5 Experimental Waveforms of the Hard-Switched Two-Converter Boost

Converter with Structures A and C Magnetic Integration

In order to validate the theoretical analysis, the hard-switched two-inductor boost

converter with Structures A and C magnetic integration have been constructed.

Structure A is implemented using an ETD39 core with a 0.5-mm air gap in each of

the two outer core legs and Structure C is implemented using an ETD39 core with a

0.5-mm air gap in the centre core leg only. The ETD39 core has a minimum centre

core leg cross section area of 123 mm2 [166]. Other main components used in the

converter shown in Figures 5.5 and 5.11 are listed below:

• MOSFETs Q1 and Q2 – ST STB50NE10, VVDS 100= , ,

.

AI D 50=

Ω= 027.0)(onDSR

• Diodes D1 and D2 – Microsemi UPSC600, AI F 0.1= , ,

.

VVRRM 600=

VVF 6.1=

• Capacitors CO1 and CO2 – Vishay class X7R multilayer ceramic surface

mount capacitor VJ1210Y104KXCAT, FC µ1.0= , . VVdc 200=

The ac flux and the current waveforms are respectively shown in Figures 5.17 and

5.18. The top two waveforms are the ac components of the fluxes φ1 and φc as

recovered by integrating the voltage of a single search turn wound on the

transformer core leg. The bottom two waveforms are the currents i1 and iIN.

222

The experimental waveforms shown in Figure 5.17 agree well with the theoretical

waveforms in Figures 5.4 and 5.7 and those shown in Figure 5.18 agree well with

the theoretical waveforms in Figure 5.16. It can be clearly seen that for the same

amount of flux ripple in the outer core leg, the flux ripple in the centre core leg in

Structure C is much smaller than that in Structure A.

Math1 5.0µVs 4.0µs


Boost Converter with Structure A Magnetic Integration

Channel M1: AC Component of Flux φ1 (5 µWb/div),

Channel M2: AC Component of Flux φc (5 µWb/div),

Channel 3: Current i1 (2 A/div), Channel 4: Current iIN (2 A/div)

223

Math1 5.0µVs 4.0µs


Boost Converter with Structure C Magnetic Integration



Channel 3: Current i1 (2 A/div), Channel 4: Current iIN (2 A/div)

As Structure B has high transformer leakage inductance, it is not suited to the hard-

switched converter operation. A soft-switched two-inductor boost converter with

Structure B magnetic integration will be introduced in the next section.

224

5.6 Soft-Switched Two-Inductor Boost Converter with Structure B

Magnetic Integration

Amongst the four integrated magnetic structures, Structure B presents the highest

transformer leakage inductance as the primary and the secondary windings are

located on different core legs. In the operation of the hard-switched two-inductor

boost converter, the transformer leakage inductance resonates with the MOSFET

output capacitance when the MOSFET turns off and this causes over voltage across

the MOSFETs. This adverse effect prohibits the application of Structure B magnetic

integration in the hard-switched two-inductor boost converter.

In the ZVS two-inductor boost converter, however, the transformer leakage

inductance is actively utilised as part of the resonant inductance and this enables the

employment of Structure B magnetic integration in the converter. This section

provides a detailed analysis of the application of Structure B magnetic integration in

the ZVS two-inductor boost converter with a voltage-doubler rectifier, as shown in

Figure 5.19.

5.6.1 ZVS Two-Inductor Boost Converter with Structure B Magnetic

Integration

Figure 5.20 shows the proposed ZVS two-inductor boost converter with Structure B

magnetic integration.

225

E

L1 L2

D2

D1

T T

CO2

CO1

C1 C2

Lr

Q1 Q2

VO

+

−R

DQ1 DQ2

Figure 5.19 ZVS Two-Inductor Boost Converter with a Voltage-Doubler Rectifier

iC1

iC2 φ1

φ2

i1

i2

E

Np

Np

+

−

isNs

φc

D2

D1

R

+

−

Q2

Q1 C1

C2 vC2

+

vC1

+

vs

Lrs

DQ1

DQ2

VO

CO1

CO2

−−

iQ1

iQ2

Figure 5.20 ZVS Two-Inductor Boost Converter with Structure B Magnetic

Integration

In Figure 5.20, the resonant inductance is placed in series with the transformer

secondary winding for the simplicity of the circuit diagram as the transformer

primary winding is performed by the two separate windings on the two outer core

legs. The resonant inductance in Figure 5.20 can be related to that in Figure 5.19 as:

rp

srs L

NN

L 2

2

= (5.204)

226

The implementation of the resonant inductance normally requires additional high-

quality-factor inductors in series with the existing transformer leakage inductance so

that the characteristic frequency of the resonant tank is comparable to the converter

switching frequency. In Structure B magnetic integration, however, the transformer

leakage inductance is much larger than that of the transformer with tight couplings

between the primary and the secondary windings and is normally large enough to

form the resonant inductance by itself. In this case, the number of magnetic core

and copper winding components can be significantly reduced. The four cores and

five windings required by the two input inductors, the resonant inductor and the

transformer in the ZVS two-inductor boost converter with discrete magnetics are

reduced to a single core with three windings. This results in a more compact design

with a potentially higher power density.

The resonant capacitances are implemented by the MOSFET output capacitances in

parallel with the additional low-dissipation-factor capacitors.

5.6.2 Equivalent Input and Transformer Magnetising Inductances

The equivalent input and magnetising inductances need to be analysed against the

soft-switched two-inductor boost converter. The derivatives of the converter

instantaneous input and transformer secondary currents in the soft-switched

converter with discrete magnetics will be solved first and these will be used as the

templates to obtain the equivalent circuit of the soft-switched converter with

Structure B magnetic integration. In order to be consistent with the converter

227

topology in Figure 5.20, the resonant inductor in Figure 5.19 is moved to the

transformer secondary side and the converter is redrawn in Figure 5.21.

iC2iC1

iIN

E

L2

D2

D1T T

CO2

CO1

C1 C2Q1 Q2

VO

+

−R

DQ1 DQ2

vL1

+

−

vL2

+

− Lrs

+ −vp + −vsip is

i1 i2

iQ1 iQ2

L1

vC2

+

−vC1

+

−

Figure 5.21 ZVS Two-Inductor Boost Converter with the Resonant Inductance in the

Transformer Secondary Side


• State (1) ( ) ss TDt )1(0 −<<

In this state, Q1 is off while Q2 is on and 01 =Qi . The circuit equations are the

same as Equations (5.1) to (5.3) and the derivative of the input current can be

obtained as Equation (5.4). The equivalent transformer model in Figure 5.3 can

still be used as the transformer leakage inductance is classified as part of the

resonant inductance. According to Figure 5.21, the following equations can be

obtained:

11 Cp iii −= (5.205)

228

dtdv

Ci CrC

11 = (5.206)

pC vv =1 (5.207)

Manipulations of Equations (5.1), (5.3), (5.5), (5.8), (5.9), (5.205), (5.206) and

(5.207) yield:

2

22211

dtvd

CNN

vLN

NLL

ENN

dtdi s

rs

ps

s

p

mss

ps⎟⎟⎠

⎞⎜⎜⎝

⎛−

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅= (5.208)


T)

23(

2−<< )

In this state, Q1 is on while Q2 is off and 02 =Qi . The derivative of the input

current can be obtained as Equation (5.14). According to Figure 5.21, the

following equations can be obtained:

22 Cp iii +−= (5.209)

dtdv

Ci CrC

22 = (5.210)

pC vv −=2 (5.211)

The derivative of the transformer secondary current can then be obtained as:

229

2

22211

dtvd

CNN

vLN

NLL

ENN

dtdi s

rs

ps

s

p

mss

ps⎟⎟⎠

⎞⎜⎜⎝

⎛−

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅−= (5.212)

• States (2) and (4) (2

)1( sss

TtTD <<− and sss TtTD <<− )

23( )

In these two states, Q1 and Q2 are both on. The derivative of the input current

can be obtained as Equation (5.11). As the transformer secondary voltage is

zero, the derivative of and the transformer secondary current is only determined

by the converter output voltage and the resonant inductance and no longer

related to the transformer magnetising inductance.

In the hard-switched two-inductor boost converter in Figure 5.9, in State (1)

when Q

02 =i

1 is off, in State (3) when Q01 =i 2 is off and 0=si in States (2) and (4)

when Q1 and Q2 are both on. Due to the introduction of the resonant capacitors in

the soft-switched converter, however, the current in the combined winding is no

longer zero when the corresponding MOSFET is off and the current in the

transformer secondary winding is no longer a constant zero when both the

MOSFETs are on. The magnetic circuit of Structure B is redrawn in Figure 5.22 and

this is valid at all times in States (1) to (4).

According to Figure 5.22, the fluxes in the three core legs are respectively:

230

o

c

co

p

co

ss

o

c

co

p iNiNiNℜℜ⋅

ℜ+ℜ+

ℜ+ℜ−⎟⎟

⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

=22

12

211φ (5.213)

⎟⎟⎠

⎞⎜⎜⎝

⎛ℜℜ

+ℜ+ℜ

+ℜ+ℜ

+ℜℜ⋅

ℜ+ℜ=

o

c

co

p

co

ss

o

c

co

p iNiNiN1

22221

2φ (5.214)

co

p

co

ss

co

pc

iNiNiNℜ+ℜ

−ℜ+ℜ

−ℜ+ℜ

=22

22

21φ (5.215)

Npi1

Nsis

ℜo

ℜo

ℜc

φ1

φc

φ2

+−

+−Npi2

+−

Figure 5.22 Magnetic Circuit of Structure B in the ZVS Two-Inductor Boost

Converter

According to Figure 5.20, Equations (5.40) and (5.216) to (5.219) can be obtained.

21

Cp vEdt

dN −=

φ (5.216)

12

Cp vEdt

dN −=

φ (5.217)

221 CQ iii += (5.218)

112 CQ iii += (5.219)

231

The converter in Figure 5.20 is now analysed under three different operating

conditions.

• State (1) ( ) ss TDt )1(0 −<<

In this state, as Q01 >Cv 1 is off and 02 =Cv as Q2 is on. Equation (5.216) can

be rewritten to Equation (5.32). Manipulations of Equations (5.32), (5.40),

(5.89) and (5.217) yield:

ss

pC v

NN

v =1 (5.220)


ss

pp v

NN

Edt

dN −=2φ (5.221)

As , Equation (5.219) can be rewritten as: 01 =Qi

12 Cii = (5.222)


232

2

22

dtvd

CNN

dtdi s

rs

p= (5.223)

Substitution of Equations (5.213), (5.214) and (5.215) to (5.32), (5.40) and

(5.221) and manipulations the results with Equation (5.223) yield Equations

(5.28) and (5.224):

2

222

211

dtvd

CNN

vLN

NLL

ENN

dtdi s

rs

ps

as

p

bas

ps⎟⎟⎠

⎞⎜⎜⎝

⎛−

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅= (5.224)


T)

23(

2−<< )

In this state, as Q01 =Cv 1 is on and as Q02 >Cv 2 is off. Equation (5.217) can

be rewritten to Equation (5.23). Manipulations of Equations (5.23), (5.40),

(5.89) and (5.216) yield:

ss

pC v

NN

v −=2 (5.225)


ss

pp v

NN

EdtdN +=1φ (5.226)

233

As , Equation (5.218) can be rewritten as: 02 =Qi

21 Cii = (5.227)


2

21

dtvd

CNN

dtdi s

rs

p−= (5.228)

Substitution of Equations (5.213), (5.214) and (5.215) to (5.23), (5.40) and

(5.226) and manipulations the results with Equation (5.228) yield Equations

(5.36) and (5.229):

2

222

211

dtvd

CNN

vLN

NLL

ENN

dtdi s

rs

ps

as

p

bas

ps⎟⎟⎠

⎞⎜⎜⎝

⎛−

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+−⋅−= (5.229)

• States (2) and (4) (2

)1( sss

TtTD <<− and sss TtTD <<− )

23( )

In these two states, Q1 and Q2 are both on. According to Figure 5.20, Faraday’s

Law gives Equations (5.23) and (5.32) and Equation (5.41) can be obtained.


(5.12). Therefore the transformer secondary current is no longer determined by

the transformer magnetising inductance.

234


with their discrete magnetic counterparts, Equations (5.4), (5.208), (5.14), (5.212)

and (5.11), yield Equations (5.43) and (5.44). Equations (5.43) and (5.44) confirm

that the equivalent input and transformer magnetising inductances of Structure B

magnetic integration are the inherent characteristics of the magnetic structure and do

not change with the hard-switched or the soft-switched two-inductor boost converter

topologies.

5.6.3 DC Fluxes

The dc fluxes in Structure B in the ZVS two-inductor boost converter can be

analysed in the same process as in the integrated magnetic structures in the hard-

switched converter. However, the ac fluxes in the ZVS converter must be

established through the state analysis, which will be introduced in the next section.

Assuming that I1, I2, IS are respectively the dc components of i1, i2 and is over the

entire switching period, the following equations can be established as the operation

of the ZVS two-inductor boost converter is half cycle symmetrical:

221INI

II == (5.230)

0=SI (5.231)

Assuming that I1,j, I2,j and Is,j are respectively the dc components of i1, i2 and is in

235

State (j), where , the following equation can be established: 4,3,2,1=j

∑=

=4

1,

jjwjw IDI , sw ,2,1= , 4,3,2,1=j ,

⎪⎩

⎪⎨⎧

=−

=−=

4,2,21

3,1,1

jD

jDD

s

s

j (5.232)

According to Figure 5.22, the instantaneous fluxes in the three core legs are

restricted by Equations (5.51) and (5.233):

sspcco iNiN −=ℜ+ℜ 11 φφ (5.233)

Equations (5.51) and (5.233) can be respectively rewritten to Equations (5.53) and

(5.234) with the dc components of the variables in each state, where Φ1, Φ2, Φc and

IIN are the dc components of φ1, φ2, φc, iIN in each state and as well over the entire

switching period:

jssjpcco ININ ,,11 −=Φℜ+Φℜ , 4,3,2,1=j (5.234)


Sspcco ININ −=Φℜ+Φℜ 11 (5.235)

Substitution of Equations (5.230) and (5.231) to (5.235) yields:

236

21INp

cco

IN=Φℜ+Φℜ (5.236)

Equations (5.53) and (5.236) are valid over the entire switching period and the dc

fluxes in the individual core legs are the same as those in Structure B in the hard-

switched two-inductor boost converter, which are given in Equations (5.61) and

(5.62).


As Structure B magnetic integration can be modeled by the discrete magnetics as

explained in Section 5.6.2, the operation of the ZVS two-inductor boost converter

with integrated magnetics can be analysed based on the converter in Figure 5.19 if

the resonant inductance Lrs in Figure 5.20 is converted to its equivalent value Lr

through Equation (5.204).

After Q1 turns off, the converter will move through up to four possible states, as

shown in Figure 4.4. All symbols have the same physical meanings except that Vd

is now the output capacitor CO1 or CO2 voltage reflected to each of the two combined

windings that perform as both the input inductor and the transformer primary. The

resonant capacitor voltage and the inductor current are the same as those presented

in Section 4.3.1 and the flux in one outer core leg will be analysed here.

• State (a) ( ) 10 tt ≤≤

237

While vC1 increases in this state, φ2 increases but with a reducing rate as long as

. When , φEvC <1 EvC >1 2 decreases with an increasing rate. If the initial flux

202 )0( Φ=φ , the flux φ2 is:

200

0000102

sin)1(cos)1()()( Φ+

−−∆+++=

p

dd

NtVtZItVE

tω

ωωωφ (5.237)

The derivation of Φ20 will be given in due course after the state analysis is

completed.

• State (b) ( ) 21 ttt ≤≤

In this state, the flux φ2 encounters the same situation as in State (a). The flux φ2

is:

[ ])(

)(2

)()()( 12

21

1

0111

2 tN

ttCI

tttvEt

p

C

φφ +−−−−

= (5.238)

• State (c) ( ) 32 ttt ≤≤

In this state, the flux φ2 keeps decreasing with an increasing rate until vC1

reaches its peak and continues to decrease as long as . After vEvC >1 C1 falls

238

below E, φ2 again increases at an increasing rate. The flux φ2 is:

[ ]

[ ])(

)(sin)(

1)(cos)()()(

220

2021

0

2000202

tN

ttVtv

NttZIttVE

t

p

dC

p

d

φω

ω

ωωω

φ

+−−

−

−−+−−=

(5.239)

• State (d) ( ) 43 ttt ≤≤

In this state, the flux φ2 increases linearly as the capacitor voltage vC1 is zero.

The flux φ2 is:

)()(

)( 323

2 tN

ttEt

p

φφ +−

= (5.240)

According to the above state analysis, the flux φ2 reaches its maximum φ2,max when

the capacitor voltage vC1 first reaches E in either States (a) or (b) and reaches its

minimum φ2,min when the capacitor voltage vC1 drops back to E in State (c). The ac

fluxes in the outer core legs 1φ∆ and 2φ∆ can be calculated by integrating

Equation (5.217) between the times when the flux φ2 reaches φ2,max and φ2,min.

Therefore, the peak flux φ2,max can be obtained as:

22

2max,2

φφ

∆+Φ= (5.241)

239

The initial flux Φ20 can then be derived by subtracting the flux increase between the

instant when Q1 turns off and the instant when vC1 first reaches E from the peak flux

φ2,max.

The flux φ1 in the other outer core leg can be analysed in the same way. Under

symmetrical operation, the flux waveforms of the two outer core legs are the same

except that they are phase shifted with 180°.

Because the transformer primary and secondary windings are loosely coupled in

Figure 5.20, the resonant inductance can be purely realised from the transformer

leakage inductance. In this case, the leakage flux in the transformer is significant

and the flux paths are not constrained within the core structure. Considering the

leakage flux, Structure B magnetic circuit shown in Figure 5.22 can be redrawn in

Figure 5.23, where ℜa is the reluctance of the transformer leakage flux path in the

air and φle is the transformer leakage flux, which has the same direction as the flux in

the centre core leg.

The flux in the centre core leg and the leakage flux are respectively:

lec φφφφ −−= 21 (5.242)

s

srsle N

iL=φ (5.243)

240

Npi1

Nsis

ℜa

ℜo

ℜc

φ1

φc

φle

+−

+−

ℜo φ2 Npi2

+−

Figure 5.23 Structure B Magnetic Circuit with the Leakage Flux Path

It is worth mentioning that Equation (5.40) can also be used to solve the flux in the

centre core leg. As the resonant inductance is made up of the transformer leakage

inductance, vs in Equation (5.40) is the positive voltage across the capacitor CO1 or

the negative voltage across the capacitor CO2 in the voltage-doubler rectifier. When

the transformer secondary current is positive, and φ0>sv c linearly increases and

when the transformer secondary current is negative, 0<sv and φc linearly

decreases.

5.6.5 Theoretical and Experimental Waveforms

The proposed topology is validated experimentally by a 40-W converter with 20-V

input. A conversion efficiency of 93% has been recorded by using the mathematics

functions of a Tektronix TDS5034 oscilloscope equipped with the input and output

voltage and current probes. The components used in the converter are listed below:

241

• Inductors L1 and L2 and Transformer T – Core type Philips ETD29 with a

0.5-mm air gap in each of the two outer core legs, minimum centre core leg

cross section area 71 mm2 [167], ferrite grade Philips 3F3, Structure B

magnetic integration, primary and secondary wires: Litz wires made up of 50


turns, secondary winding 10=pN 13=sN turns, leakage inductance

reflected to the transformer secondary HLles µ39.12= .

• Additional Resonant Capacitors – Cornell Dubilier surface mount mica

capacitor MC22FA202J, 2 nF, VVdc 100= , 60001=DF at 500 kHz, 6 nF

capacitance used.


,

AI D 50=

Ω= 027.0)(onDSR nFCoss 675.0= .

• Diodes D1 and D2 – Motorola MBRS1100T3 surface mount diodes,

VVRRM 100= , , AIF 0.1= VVF 75.0= .

• Capacitors CO1 and CO2 – AVX surface mount capacitors 0.47 µF,

. VVdc 50=

The other parameters used in the converter design are listed below:

• The switching frequency kHzf s 500= and the duty ratio . 60.0=sD

• , and 4.1=k 9.11 =∆ 15.1/ =EVd .

• HLr µ33.7= and nFCr 65.6= .

242

The theoretical waveforms of the MOSFET gate voltage, the resonant capacitor

voltage, the resonant inductor or the transformer secondary current and the fluxes in

the two outer and the centre core legs under the above operating conditions are given

in Figure 5.24.

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4-4

-3

-2

-1

0

1

2

3

4

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4-3

-2

-1

0

1

2

3

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4-3

-2

-1

0

1

2

3

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4-3

-2

-1

0

1

2

3

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 40

20

40

60

80

100

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 40

5

10

15

20

Mos

fetQ

1 Gat

e V

olta

gev G

Q1 (

V)

Cap

acito

rC1 V

olta

gev C

1 (V

)

t (µs)

t (µs)

Indu

ctor

L rs C

urre

nt i s

(A)

t (µs)

t (µs)

Out

er C

ore

Leg

Flux

φ 2 (µ

Wb)

t (µs) t (µs)

Out

er C

ore

Leg

Flux

φ 1 (µ

Wb)

Cen

tre C

ore

Leg

Flux

φ c (µ

Wb)

Figure 5.24 Theoretical Waveforms

243

Under the above operating conditions, the dc flux is 0.87 µWb and the ac flux is

2.54 µWb peak to peak in the two outer core legs. The peak flux density in the outer

core leg is 60 mT. The ac flux is 2.30 µWb peak to peak and the peak flux density is

16 mT in the centre core leg.

The experimental waveforms are shown in Figures 5.25 and 5.26. From top to

bottom, Figure 5.25 shows the MOSFET gate voltage, the resonant capacitor voltage

and the transformer secondary current.

Figure 5.25 Experimental Voltage and Current Waveforms

244

The top two waveforms in Figure 5.26 are respectively the ac flux waveforms of φ2

and φc as recovered by integrating the voltage of a single search turn wound on the

transformer core leg. The bottom two waveforms are respectively the resonant

capacitor voltage vC1 and resonant inductor current is and they are repeated here as

the references for the flux waveforms.

Math2 5.0uVs 400ns

Figure 5.26 Experimental AC Flux, Voltage and Current Waveforms



Channel 3: Voltage vC1 (50 V/div), Channel 4: Current is (3 A/div)

245

It can be observed in Figure 5.26 that the flux φ2 decreases when and

increases when . The flux φ

EvC >1

EvC <1 c linearly increases when and linearly

decreases when . The experimental waveforms in Figures 5.25 and 5.26 agree

very well with the theoretical waveforms in Figure 5.24.

0>si

0<si

5.7 Summary

This chapter systematically studies four magnetic integration solutions for the two-

inductor boost converter, which are able to integrate the core and the winding

components required by separate magnetic devices and lead to the converter design

with the minimised size and cost. In the converter with magnetic integration, the


flux densities in the individual core legs and the current ripples in the individual

windings are thoroughly investigated. The theoretical waveforms are provided for

the hard-switched two-inductor boost converter with each of the four integrated

magnetic structures and the experimental waveforms are provided for the hard-

switched two-inductor boost converter with Structures A and C magnetic

integration. The ZVS two-inductor boost converter with Structure B magnetic

integration is also studied in detail and both the theoretical and the experimental

waveforms are provided for a prototype 40-W converter.

246

6. CURRENT FED TWO-INDUCTOR BOOST CONVERTER

Parts of this chapter have been published in the Australian Journal of Electrical &

Electronic Engineering in 2004 and in the Proceedings of AUPEC 2003, 2004 and

2005, APEC 2005 and PESC 2005.

Chapter 2 has shown that MIC implementations with an unfolding stage are able to

avoid the complex circuit design and the high switching losses associated with the

PWM control technique in the dc-ac inversion stage. It has been shown in Chapter 3

that a buck conversion stage must be used as the current source for the two-inductor

boost converter so that the rectified sinusoidal waveforms can be generated at the

output and an unfolder can be employed in the dc-ac inversion stage. This chapter

studies the current fed two-inductor boost converter in detail and provides the

experimental results of a 100-W converter with both the hard-switched and the soft-

switched topologies. While this approach does result in a rather long power train, it

is still possible to achieve adequate conversion efficiencies. One advantage is that

the boost cell can operate at fixed duty ratio and be optimised better as the buck

stage can perform most or all of the required voltage variations for the control.

6.1 Buck Conversion Stage

It has been shown earlier in the thesis that under the voltage source input, a variable

output voltage can be produced by varying the switching duty ratios in the hard-

247

switched two-inductor boost converter or by varying the switching frequency in the

soft-switched two-inductor boost converter. However, the two-inductor boost

converter is a boost derived converter and zero output voltage cannot be reached in

either the hard-switched or the soft-switched forms. In order to generate the

rectified sinusoidal waveforms at the output of the two-inductor boost converter, a

buck conversion stage must be added. Therefore the converters in Figures 3.10 and

3.11 can be developed.

Recently, multi-phase converter arrangements have been widely adopted as an

efficient approach to parallel multiple converters to provide high current output

[168]. Under multi-phase operation, the individual converter input and output

currents with an equal phase shift, which is the quotient of 360º divided by the

number of phases, are added together and the equivalent input and output current

ripple frequencies will be multiplied by the number of the phases. The converter

also has a smaller input or output current ripple magnitude as the current ripples in

the individual phases cancel [169]. This eases the requirement on bulky input and

output filter components such as inductors and capacitors. A two-phase buck

converter will be employed as the current source for the two-inductor boost

converter.

In order to feed the output from the two-phase buck converter to the input of the

two-inductor boost converter and make use of the two existing inductors in the boost

converter, an interphase transformer (IPT) is utilised. The IPT is a tapped inductor,

which has 1:1 turns ratio. The IPT has been previously used in the dc-dc converter

248

applications [170] and more widely in mains frequency, high pulse number rectifiers

[101]. The employment of the IPT enables the equivalent switching frequency of

the buck converter to be doubled without higher switching losses. The hard-

switched and the soft-switched two-inductor boost converters with a two-phase buck

converter are respectively shown in Figures 6.1 and 6.2.

E

L1 L2

D4

D3

T2

CO2

D1 D2

Q1

Q2 T1

+ −

S1 S2

S3S4

CO1

+

−

vOQ3 Q4

T2vC

Figure 6.1 Hard-Switched Two-Inductor Boost Converter with a Two-Phase Buck

Converter

E

D4

D3

CO2

D1 D2

Q1

Q2 T1

+ −

S1 S2

S3S4

CO1

+

−

vO

T2vC

L1 L2

C1C2

Lr

Q3 Q4

T2

DQ2DQ1

Figure 6.2 Soft-Switched Two-Inductor Boost Converter with a Two-Phase Buck

Converter

The two-phase buck topology shown in Figures 6.1 and 6.2 can be further improved

by using the concept of the synchronous rectifier, where the diodes are replaced by

the MOSFETs. In a conventional converter which uses a diode in the load current

249

conduction path, the minimisation of the conduction power losses in the diode is

difficult as the reduction of the diode forward voltage drop below a certain level

presents a great challenge [171]. The synchronous rectifier is able to largely

improve the converter efficiency by replacing the diode with a MOSFET, as the

forward resistance of the synchronous MOSFET can be very low [172]. If the

synchronous rectifier is used, dead time must be applied between the turn-on of the

control and the synchronous MOSFETs to prevent “shoot-through”. A Schottky

diode is placed in reverse parallel with the synchronous MOSFET in the standard

design to stop the load current from flowing through the MOSFET body diode,

which normally has a higher voltage drop and inferior reverse recovery

characteristic.

The hard-switched and the soft-switched two-inductor boost converters, which are

fed from a sinusoidally modulated two-phase synchronous buck converter, will be

respectively analysed in detail in the following sections.

6.2 Hard-Switched Current Fed Two-Inductor Boost Converter

This section provides a detailed analysis of the hard-switched current fed two-


6.2.1 Circuit Diagram

Figure 6.3 shows the hard-switched two-inductor boost converter with a two-phase

250

synchronous buck converter, where a resistive load is used.

E

L1 L2

D4

D3

CO2

D1 D2

Q1

Q2 T1

+ −

CO1

vC

+

−

vH

+

−

+

−

v2

+

−

T2T2

Q3 Q4

Q6Q5 v1vO

R

S1 S2

S3S4

vT2p+ −

Figure 6.3 Hard-Switched Two-Inductor Boost Converter with a Two-Phase

Synchronous Buck Converter

The converter in Figure 6.3 is a three stage converter including the buck, the boost

and the unfolding stages. The transfer functions of the individual stages can be

respectively found as:

EDv buckavgH =, (6.1)

avgHboost

TC v

Dnv ,

2

12−

= (6.2)

⎩⎨⎧−

=onSandSvonSandSv

vC

CO

42

31

,,

(6.3)

where Dbuck and Dboost are respectively the duty ratios of the buck stage MOSFETs

Q1 and Q2 and the boost stage MOSFETs Q3 and Q4, nT2 is the transformer T2 turns

ratio, E is the converter input voltage, vH,avg is the boost stage average input voltage

over one equivalent buck stage switching period, vC is the boost stage output voltage

and vO is the converter output voltage.

251

In order to produce the sinusoidal waveforms at the output of the unfolding stage,

the duty ratio of the buck stage MOSFETs Dbuck needs to be modulated in a

sinusoidal manner as:

tfD gridbuck π2sin= (6.4)

where fgrid is the grid frequency, which is 50 Hz in this thesis.

The duty ratio of the boost stage MOSFETs Dboost needs to be a fixed value slightly

greater than 50%. Therefore, the gain of the buck stage is the absolute sine function,

that of the boost stage is a constant and that of the unfolding stage is ±1 depending

on the pair of the switches that are on. The output voltage of the converter can be

obtained by multiplying Equations (6.1) to (6.3) as:

⎪⎪⎩

⎪⎪⎨

⎧

−−

−=

onSandSEDDn

onSandSEDDn

v

boost

buckT

boost

buckT

O

422

312

,12

,12

(6.5)

Considering a simplified case where %50=boostD and the gate signal of Q1 is

synchronised with that of Q3, the theoretical switching waveforms of the buck and

the boost stages can be drawn in Figure 6.4, where the switching frequency of the

buck stage fbuck is twice that of the boost stage fboost. Tbuck and Tboost are respectively

the switching periods of the buck and the boost stages. Figures 6.4(a) and (b)

252

respectively shows the switching waveforms when %50<buckD and .

The voltage after the IPT swings between zero and the half input voltage when

, while it swings between the half and the full input voltage when

. The three levels and the frequency doubling effect can be seen in v

%50>buckD

%50<buckD

%50>buckD H

waveform in both cases.

t

t

t

t

t

t

vQ1G

vQ2G

vQ3G

vQ4G

vT2p

vH

E/2

Tbuck 2Tbuck 4Tbuck3Tbuck

Tboost 2Tboost


Tboost 2Tboost

0 t

t

t

t

t

t

vQ1G

vQ2G

vQ3G

vQ4G

vT2p

vH

E/2


Tboost 2Tboost

E

Tboost 2Tboost


0

(a) (b)

Figure 6.4 Theoretical Switching Waveforms in the Buck and the Boost Stages

(a) %50<buckD (b) %50>buckD

6.2.2 Non-Dissipative Snubbers

In order to limit the switch over voltage caused by the leakage inductance during the

253

MOSFET turn-off transition and utilise MOSFETs with low voltage ratings in the

hard-switched two-inductor boost converter, voltage clamping or snubber circuits

must be used. The non-dissipative snubbers, which do not require additional control

circuit, are attractive solutions [173] and they have been previously applied to the

hard-switched two-inductor boost converter, as shown in Figure 6.5 [112].

E

L1 L2

D4

D1

D3

D2

Cs1 Cs2Ds1 Ds2

Lsr1

Dsr1 Dsr2

Q1 Q2

T1 T1

RCO VO

+

−

Lsr2

Figure 6.5 Passive Non-Dissipative Snubbers Proposed in [112]

The snubber circuit uses two snubber inductors, two snubber capacitors and four

diodes and is able to control the peak switch voltage at the MOSFET turn-off. The

energy trapped in the snubber circuit can be also transferred in a lossless way back

to the voltage source supply E at the next MOSFET turn-on under certain

circumstances.

In the snubber circuit shown in Figure 6.5, the snubber diode Dsr1 or Dsr2 is only

forward biased between the instant when the MOSFET Q1 or Q2 turns on and the

254

instant when the resonant current in the snubber inductor Lsr1 or Lsr2 reaches zero.

This is the only duration when the snubber inductors are actively involved in the

operation. If the snubber inductor current in the snubber circuit for one MOSFET

reaches zero before the other MOSFET turns on, the snubber inductor can be shared

by the snubber circuits for both MOSFETs and only one snubber inductor is

required. Figure 6.6 shows the hard-switched current fed two-inductor boost

converter with the variation of the non-dissipative snubbers in Figure 6.5.

E

L1 L2

D4

D3

CO2

D1 D2

T1S1 S2

S3S4

CO1

vC

+

−

+

−

+

−

+

−

Cs1 Cs2Ds1 Ds2

Lsr

Dsr1 Dsr2

vs1

+

−

vCs1+ −

vQ3

+

−

v2vH

Q3 Q4

Q6

Q2

Q1

Q5 v1

T2 T2

+ −vO

R

Figure 6.6 Hard-Switched Current Fed Two-Inductor Boost Converter with Non-

Dissipative Snubbers

The snubber circuit in Figure 6.6 utilises only one snubber inductor, two snubber

capacitors and four diodes. Space-saving is possible as the inductors generally have

the biggest packages among the components used in the snubber circuit.

As the average input voltage and current to the two-inductor boost cell follow the

rectified sinusoidal waveforms, variable peak voltages across MOSFETs Q3 and Q4

exist in the converter in Figure 6.3. The snubber circuit therefore only needs to be

255

active when the buck stage duty ratio is relatively high. This avoids the energy

circulation in the snubber circuit under low buck stage duty ratios or low boost cell

input voltages, when the peak MOSFET voltages are within the certain level without

the assistance from the snubber circuit. The energy circulation in the snubber circuit

could potentially cause additional power losses and reduce the overall efficiency due

to the parasitic effects in the practical circuit. The snubber circuit in Figure 6.6 can

be analysed using the equivalent circuit shown in Figure 6.7.

+ile DCs1 LlevCs1

i0

vd

Q3 iLsr

vCs2+

i0

Cs2

Q4Coss,Q3

Ds1E

Coss,Q4

Ds2E

Dsr1 Dsr2

Lsr

+

vQ3

+

vQ4+vs1

+vs2−

−

−−

−

−

Figure 6.7 Equivalent Snubber Circuit

In Figure 6.7, Lle is the transformer T2 leakage inductance reflected to the primary.

The MOSFET Q3 or Q4 output capacitance is ossQossQoss CCC == 4,3, . The current

source i0 models the input inductor L1 or L2 over a high frequency switching period.

The snubber capacitance is sss CCC == 21 . The voltage source vd is the output

voltage across the capacitor CO1 or CO2 over a high frequency switching period

reflected to the transformer T2 primary winding and the diode D corresponds to the

diodes in the voltage-doubler rectifier. The arrangement of the voltage source vd

and the diode D in Figure 6.7 assumes a positive current ile in the transformer T2

256

primary winding as illustrated and their polarities reverse when ile becomes negative.

In the theoretical analysis, the MOSFET output capacitance Coss,Q3 or Coss,Q4 can be

neglected whenever the snubber capacitor Cs1 or Cs2 is actively involved in the

operation as the snubber capacitance needs to be selected to be much larger than the

MOSFET output capacitance. The MOSFET output capacitance Coss,Q3 or Coss,Q4 is

also neglected after the transformer primary current ile first reaches i0 or –i0 or the

MOSFET Q3 or Q4 drain source voltage vQ3 or vQ4 reaches its peak in the theoretical

analysis. In the practical operation, damped oscillations happen after this time. The

MOSFET output capacitance and the transformer leakage inductance oscillate with

damping provided by the parasitic resistances in the circuit. In the following

discussion, the snubber diodes are considered as ideal components.

As the input voltage and current to the boost cell vary, different snubber capacitor

voltages result at the end of the snubber operational cycle. The snubber capacitor

voltage at the end of the snubber operation is also the snubber capacitor voltage

before the MOSFET turn-off, vCs1(0) or vCs2(0), which is less than or equal to zero

due to the resonance between the snubber capacitor and inductor and is a critical

parameter in determining the operation mode of the snubber circuit. It is established

that the snubber circuit can operate in four modes with different initial values of vCs1

or vCs2. The operation of the snubber circuit for the MOSFET Q3 will be analysed

within one switching period starting from Q3 turn-off. The range of the buck stage

MOSFET duty ratio Dbuck for each operation mode will be determined in due course.

Only the first mode of operation for this snubber circuit has been previously reported

[112], [173]. The additional modes that arise with a wide input voltage range have

257

not been previously analysed.

(i) MODE 1 ( EvCs −=)0(1 )

In Mode 1, and the snubber circuit becomes active at the instant

when the MOSFET Q

EvCs −=)0(1

3 turns off. In this mode, the snubber circuit returns the

energy to the voltage source supply E after the MOSFET Q3 turns on. The

snubber circuit in Figure 6.7 moves through six states in one switching period,

which are shown in Figure 6.8. The voltage and current waveforms in the

snubber circuit are shown in Figure 6.9.

Before Q3 turns off at 0=t , both Q3 and Q4 are on. The state analysis in Mode

1 is given below. It is worth mentioning that before Q3 turns on later in the

cycle, the snubber inductor belongs to the snubber circuit for Q4 and operates

exactly the same as in the snubber circuit for Q3. Therefore, iLsr will not be

included in the analysis of the states before Q3 turns on. Also when ile finally

becomes negative after Q4 turns off, the polarities of the voltage source vd and

the diode D will be reversed and the transformer leakage inductance Lle, the

diode D and the voltage source vd will interact with the snubber circuit for Q4.

Therefore, ile will not be included in the analysis of the states after Q3 turns on.

• State (a) ( ) 10 tt ≤≤

258

This state starts when Q3 turns off at 0=t . As EvCs −=)0(1 , the diode Ds1 is

forward biased and current source i0 linearly charges the capacitor Cs1. The

diodes D and Dsr1 are both reverse biased. The initial conditions are

EvCs −=)0(1 and 0)0( =lei . The snubber capacitor Cs1 voltage vCs1, the

transformer T2 primary current ile, the MOSFET Q3 drain source voltage vQ3 and

the snubber diode Ds1 anode voltage vs1 are respectively:

+

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

State (b)

+

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

State (c)

+

−Cs1vCs1

i0iLsr

E Lsr

+

−

vQ3+

−

vs1

State (d)

+

−Cs1vCs1

i0iLsr

E Lsr

+

−

vQ3+

−

vs1

State (e)

+

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

State (a)

+

−Cs1vCs1

i0iLsr

E Lsr

+

−

vQ3+

−

vs1

State (f)

Figure 6.8 Six States in Mode 1 Operation

259

0 t1 t2 t3 t4 t5 t6 t

vQ3G

vCs1

iLsr

vQ3

vs1

−E

E

vd

0 t1 t2 t3 t4 t5 t6 t

0 t1 t2 t3 t4 t5 t6 t

0 t1 t2 t3 t4 t5 t6 t

0 t1 t2 t3 t4 t5 t6 t

Figure 6.9 Snubber Voltage and Current Waveforms in Mode 1 Operation

tCi

Etvs

Cs0

1 )( +−= (6.6)

0)( =tile (6.7)

tCi

tvs

Q0

3 )( = (6.8)

260

Etvs =)(1 (6.9)

• State (b) ( ) 21 ttt ≤≤

This state starts when vQ3 reaches vd at 0

1 ivC

t ds= . Both of the diodes Ds1 and D

are forward biased and the snubber capacitance resonates with the transformer

leakage inductance. The diode Dsr1 remains reverse biased. The initial

conditions are Evtv dCs −=)( 11 and 0)( 1 =tile . The snubber capacitor Cs1

voltage vCs1, the transformer T2 primary current ile and the MOSFET Q3 drain

source voltage vQ3 are respectively:

)(sin)( 11101 ttZiEvtv dCs −+−= ω (6.10)

)(cos)( 1100 ttiitile −−= ω (6.11)

)(sin)( 11103 ttZivtv dQ −+= ω (6.12)

where s

le

CL

Z =1 is the characteristic impedance and sleCL

11 =ω is the

angular resonance frequency of the resonant tank made up by Cs1 and Lle. It can

been seen from Equation (6.12) that the peak MOSFET voltage is limited to

. The snubber diode D10Zivd + s1 anode voltage vs1 is given by Equation (6.9).

• State (c) ( ) 32 ttt ≤≤

261

This state starts when ile reaches i0 at 1

12 2ωπ

+= tt . The diode Ds1 becomes

reverse biased as the current flowing through it is zero. The diode D remains

forward biased and the current source i0 flows through the transformer leakage

inductance and the voltage source vd. The diode Dsr1 is still reverse biased. This

state is an idle state, where the snubber circuit is inactive and no resonance

happens. The snubber capacitor Cs1 voltage vCs1, the transformer T2 primary

current ile, the MOSFET Q3 drain source voltage vQ3 and the snubber diode Ds1

anode voltage vs1 are respectively:

101 )( ZiEvtv dCs +−= (6.13)

0)( itile = (6.14)

dQ vtv =)(3 (6.15)

101 )( ZiEtvs −= (6.16)

As the MOSFET Q3 drain source voltage has been forced higher than the steady

state transformer primary voltage a parasitic oscillation can occur as the

MOSFET output capacitance Coss,Q3 can ring with the transformer leakage

inductance Lle. In practice this can cause Electromagnetic Interference (EMI)

problems and it is often dealt with using a small RC snubber to deliver damping

and a quick decay.

• State (d) ( ) 43 ttt ≤≤

262

This state starts when Q3 turns on at boostboost TDt )1(3 −= . The diode Ds1 remains

reverse biased. The diode D is forward biased until ile is discharged to zero by

vd. The duration of the discharge is very short as the transformer leakage

inductance is very small. The diode Dsr1 becomes forward biased in this state

and the snubber inductor resonates with the snubber capacitor. The initial

conditions are 1031 )( ZiEvtv dCs +−= and 0)( 3 =tiLsr . The snubber capacitor

Cs1 voltage vCs1, the snubber inductor Lsr current iLsr, the MOSFET Q3 drain

source voltage vQ3 and the snubber diode Ds1 anode voltage vs1 are respectively:

)(cos)()( 32101 ttZiEvtv dCs −+−= ω (6.17)

)(sin)( 322

10 ttZ

ZiEvti d

Lsr −+−

= ω (6.18)

0)(3 =tvQ (6.19)

)(cos)()( 32101 ttZivEtv ds −−−= ω (6.20)

where s

sr

CL

Z =2 is the characteristic impedance and ssrCL

12 =ω is the

angular resonance frequency of the resonant tank made up by Cs1 and Lsr.

• State (e) ( ) 54 ttt ≤≤

This state starts when vCs1 reaches –E at t4. The diode Ds1 becomes forward

biased. The diode Dsr1 remains forward biased. The voltage source E linearly

263

discharges the snubber inductor Lsr and the energy stored in the snubber inductor

is returned to the voltage supply E. The initial conditions are and EtvCs −=)( 41

)(sin)( 3422

104 tt

ZZiEv

ti dLsr −

+−= ω . The snubber capacitor Cs1 voltage vCs1

and the snubber inductor Lsr current iLsr are respectively:

EtvCs −=)(1 (6.21)

)()()( 44 ttLEtitisr

LsrLsr −−= (6.22)

The snubber diode Ds1 anode voltage vs1 and the MOSFET Q3 drain source

voltage vQ3 are respectively given by Equations (6.9) and (6.19).

• State (f) ( ) 65 ttt ≤≤

This state starts when iLsr reaches 0 at E

tiLtt Lsrsr )( 4

45 += . This state is an idle

state similar to Mode 1 State (c) and the snubber circuit will become active when

Q3 turns off again at boostTt =6 except that the snubber inductor will be earlier

involved in the operation of the snubber circuit for Q4 when Q4 turns on at

boostboost TDt )23('6 −= .

(ii) MODE 2 ( 0)0(1 <<− CsvE and ) dQ vtv <)( 13

264

In Mode 2, 0)0(1 <<− CsvE and the snubber circuit becomes active after the

MOSFET Q3 turns off but before vQ3 reaches vd. In this mode, the snubber

circuit does not return the energy to the voltage source supply E after the

MOSFET Q3 turns on. The snubber circuit in Figure 6.7 moves through six

states in one switching period, which are shown in Figure 6.10. The voltage and

current waveforms in the snubber circuit are shown in Figure 6.11. It is worth

mentioning that the duration of State (a) is extremely short therefore t1 is very

close to zero.


2 is given below. As in Mode 1, iLsr or ile will not be included in the analysis of

the states before or after Q3 turns on.

• State (a) ( ) 10 tt ≤≤

This state starts when Q3 turns off at 0=t . As , the diode DEvCs −>)0(1 s1 is

reverse biased and the current source i0 linearly charges the MOSFET Q3 output

capacitance Coss,Q3. The diodes D and Dsr1 are both reverse biased. The initial

conditions are and 0)0(3 =Qv 0)0( =lei . The snubber capacitor voltage vCs1, the

MOSFET Q3 drain source voltage vQ3 and the snubber diode Ds1 anode voltage

vs1 are respectively:

)0()( 11 CsCs vtv = (6.23)

265

tCi

tvoss

Q0

3 )( = (6.24)

tCi

vtvoss

Css0

11 )0()( +−= (6.25)

The transformer primary current ile is given by Equation (6.7).

+

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

State (b)

+

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

State (c)

+

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

State (d)

+

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

State (a)

Cos

s,Q

3

+

−Cs1vCs1

i0iLsr

E Lsr

+

−

vQ3+

−

vs1

State (e)

+

−Cs1vCs1

i0iLsr

E Lsr

+

−

vQ3+

−

vs1

State (f)


266

0 t

vQ3G

vCs1

iLsr

vQ3

vs1E

vd

t1 t2 t3 t4 t5 t6

0 t

0 t

0 t

0 t


• State (b) ( ) 21 ttt ≤≤

267

This state starts when vs1 reaches E at [ ]

0

11

)0(i

vECt Csoss += . The diode Ds1

becomes forward biased and the current source i0 linearly charges Cs1. The

diode D remains reverse biased as dQ vtv <)( 13 . The diode Dsr1 also remains

reverse biased. The initial conditions are )0()( 111 CsCs vtv = and . The

snubber capacitor C

0)( 1 =tile

s1 voltage vCs1 and the MOSFET Q3 drain source voltage vQ3

are respectively:

)()0()( 10

11 ttCi

vtvs

CsCs −+= (6.26)

)()0()( 10

13 ttCi

vEtvs

CsQ −++= (6.27)

The transformer primary T2 current ile and the snubber diode Ds1 anode voltage

vs1 are respectively given by Equations (6.7) and (6.9).

• State (c) ( ) 32 ttt ≤≤

This state starts when vQ3 reaches vd at [ ]

0

112

)0(i

vEvCtt Csds −−+= . The states

of the diodes are the same as Mode 1 State (b) and the snubber capacitance

resonates with the transformer leakage inductance. The initial conditions are

and Evtv dCs −=)( 21 0)( 2 =tile . The snubber capacitor Cs1 voltage vCs1, the

transformer T2 primary current ile and the MOSFET Q3 drain source voltage vQ3

268

are respectively:

)(sin)( 21101 ttZiEvtv dCs −+−= ω (6.28)

)(cos)( 2100 ttiitile −−= ω (6.29)

)(sin)( 21103 ttZivtv dQ −+= ω (6.30)

It can been seen from Equation (6.30) that the peak MOSFET voltage is again

limited to , where v10Zivd + d and i0 are smaller than those in Mode 1. The

snubber diode Ds1 anode voltage vs1 is given by Equation (6.9).

• State (d) ( ) 43 ttt ≤≤

This state starts when ile reaches i0 at 1

23 2ωπ

+= tt and operates in the same way

as Mode 1 State (c). The snubber capacitor Cs1 voltage vCs1, the transformer T2

primary current ile, the MOSFET Q3 drain source voltage vQ3 and the snubber

diode Ds1 anode voltage vs1 are respectively given in Equations (6.13) to (6.16).

• State (e) ( ) 54 ttt ≤≤

This state starts when Q3 turns on at boostboost TDt )1(4 −= . The states of the

diodes are the same as those in Mode 1 State (d) and the snubber inductor

resonates with the snubber capacitor. The initial conditions are

269

1041 )( ZiEvtv dCs +−= and 0)( 4 =tiLsr . The snubber capacitor Cs1 voltage vCs1,

the snubber inductor Lsr current iLsr and the snubber diode Ds1 anode voltage vs1

are respectively:

)(cos)()( 42101 ttZiEvtv dCs −+−= ω (6.31)

)(sin)( 422

10 ttZ

ZiEvti d

Lsr −+−

= ω (6.32)

)(cos)()( 42101 ttZivEtv ds −−−= ω (6.33)

The MOSFET Q3 drain source voltage vQ3 is given by Equation (6.19).

• State (f) ( ) 65 ttt ≤≤

This state starts when iLsr reaches 0 at 2

45 ωπ

+= tt and the snubber circuit

operates in the same way as Mode 1 State (f).

(iii) MODE 3 ( 0)0(1 <<− CsvE and ) dQ vtv =)( 13

In Mode 3, 0)0(1 <<− CsvE but the absolute value of vCs1(0) is so small that the

snubber circuit is active after vQ3 reaches vd. As in Mode 2, the snubber circuit

operating in this mode does not return the energy to the voltage source supply E

after the MOSFET Q3 turns on. The snubber circuit in Figure 6.7 moves through

270

six states in one switching period, which are shown in Figure 6.12. The voltage

and current waveforms in the snubber circuit are shown in Figure 6.13. It is

worth mentioning that the durations of States (a) and (b) are both extremely short

therefore t1 and t2 are very close to zero and omitted in the waveforms.

State (b)

+

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

State (c)

+

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

State (d)

+

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

State (a)

Cos

s,Q

3 +

−ileCs1 LlevCs1

i0 vd

E

+

−

vQ3+

−

vs1

Cos

s,Q

3

+

−Cs1vCs1

i0iLsr

E Lsr

+

−

vQ3+

−

vs1

State (e)

+

−Cs1vCs1

i0iLsr

E Lsr

+

−

vQ3+

−

vs1

State (f)


271

vQ3G

vCs1

iLsr

vQ3

vs1

vd

0 t3 t4 t5 t6 t

0 t3 t4 t5 t6 t

0 t3 t4 t5 t6 t

0 t3 t4 t5 t6 t

0 t3 t4 t5 t6 t

E



3 is given below. As in Mode 1, iLsr or ile will not be included in the analysis of

the states before or after Q3 turns on.

272

• State (a) ( ) 10 tt ≤≤

This state starts when Q3 turns off at 0=t and operates in the same way as

Mode 2 State (a). The transformer T2 primary current ile, the snubber capacitor

Cs1 voltage vCs1, the MOSFET Q3 drain source voltage vQ3 and the snubber diode

Ds1 anode voltage vs1 are respectively given by Equations (6.7) and (6.23) to

(6.25).

• State (b) ( ) 21 ttt ≤≤

This state starts when vQ3 reaches vd at 0

1 ivC

t doss= . The diode Ds1 remains

reverse biased as Etvs <)( 11 . The diode D becomes forward biased and the

MOSFET output capacitance resonates with the transformer leakage inductance.

The diode Dsr1 remains reverse biased. The initial conditions are dQ vtv =)( 13 ,

and )0()( 111 CsCs vtv = 0)( 1 =tile . The transformer T2 primary current ile and the

MOSFET Q3 drain source voltage vQ3 and the snubber diode Ds1 anode voltage

vs1 are respectively:

)(cos)( 1300 ttiitile −−= ω (6.34)

)(sin)( 13303 ttZivtv dQ −+= ω (6.35)

)(sin)0()( 133011 ttZivvtv Csds −+−= ω (6.36)

273

where oss

le

CL

Z =3 is the characteristic impedance and ossleCL

13 =ω is the

angular resonance frequency of the resonant tank made up by Coss,Q3 and Lle.

The snubber capacitor Cs1 voltage vCs1 is given by Equation (6.23).

• State (c) ( ) 32 ttt ≤≤

This state starts when vs1 reaches E at t2. The diode Ds1 becomes forward biased

and the snubber capacitance resonates with the transformer leakage inductance.

The diode D remains forward biased and the diode Dsr1 reverse biased. The

initial conditions are )0()( 121 CsCs vtv = and )(cos)( 123002 ttiitile −−= ω . The

snubber capacitor Cs1 voltage vCs1, the transformer T2 primary current ile and the

MOSFET Q3 drain source voltage vQ3 are respectively:

[ ][ ] )(cos)0(

)(sin)()(

211

211201

ttvEvttZtiiEvtv

Csd

ledCs

−−−−−−+−=

ωω

(6.37)

[ ] )(cos)()(sin)0(

)( 2120211

10 tttiitt

ZvEv

iti leCsd

le −−−−−−

−= ωω (6.38)

[ ] [ ] )(cos)0()(sin)()( 211211203 ttvEvttZtiivtv CsdledQ −−−−−−+= ωω (6.39)

It can been seen from Equation (6.39) that the peak MOSFET voltage is limited

to [ ] [ ] 21

220

21 )()0( ZtiivEvv leCsdd −+−−+ . The snubber diode Ds1 anode

voltage vs1 is given by Equation (6.9).

274

• State (d) ( ) 43 ttt ≤≤

This state starts when ile reaches i0 at t3 and operates in the same way as Mode 1

State (c). The snubber capacitor Cs1 voltage vCs1 and the snubber diode Ds1

anode voltage vs1 are respectively:

)()( 311 tvtv CsCs = (6.40)

)()( 311 tvvtv Csds −= (6.41)

The transformer T2 primary current ile and the MOSFET Q3 drain source voltage

vQ3 are respectively given in Equations (6.14) and (6.15).

• State (e) ( ) 54 ttt ≤≤

This state starts when Q3 turns on at boostboost TDt )1(4 −= . The states of the

diodes are the same as those in Mode 1 State (d). The initial conditions are

and )()( 3141 tvtv CsCs = 0)( 4 =tiLsr . The snubber capacitor Cs1 voltage vCs1, the

snubber inductor Lsr current iLsr and the snubber diode Ds1 anode voltage vs1 are

respectively:

)(cos)()( 42311 tttvtv CsCs −= ω (6.42)

)(sin)(

)( 422

31 ttZ

tvti Cs

Lsr −= ω (6.43)

275

)(cos)()( 42311 tttvtv Css −−= ω (6.44)

The MOSFET Q3 drain source voltage vQ3 is given by Equation (6.19).

• State (f) ( ) 65 ttt ≤≤

This state starts when iLsr reaches 0 at 2

45 ωπ

+= tt and the snubber circuit

operates in the same way as Mode 1 State (f).

(iv) MODE 4 ( ) 0)0(1 =Csv

In Mode 4, and the snubber circuit is not active during the converter

operation. The diodes in the snubber circuit remain reverse biased at all times.

0)0(1 =Csv

As the snubber capacitor is charged to different voltage levels at the end of the

snubber operation under different converter buck stage duty ratios, the operation

mode of the snubber circuit is intrinsically determined by Dbuck. The border

conditions of Dbuck for each operation mode are now analysed.

In Mode 1, in order to have EvCs −=)0(1 , the snubber capacitor voltage vCs1 must

reach –E before the snubber inductor current iLsr reaches zero in State (d).

276

According to Equation (6.18), iLsr reaches zero at 2

34 'ωπ

+= tt . Therefore, the

border condition for the snubber circuit to operate in Mode 1 is:

EtvCs −=)'( 41 (6.45)


ED

Dv

boost

buckd −=

1 (6.46)

According to Equation (6.4), if the converter average power is Pavg, the converter

instantaneous power p at the converter output is:

22 buckavg DPp = (6.47)

The converter instantaneous power can be also written at the input of the two-

inductor boost cell as:

0, 2ivp avgH ⋅= (6.48)


277

buckavg DE

Pi =0 (6.49)

Substituting Equations (6.46) and (6.49) to (6.17) and (6.45) and replacing Dbuck

with Dbuck,1, the lower border buck stage duty ratio for Mode 1 snubber operation,

yield:

12

1,

11

2

ZEP

D

Davg

boost

buck

+−

= (6.50)

Therefore the condition for the snubber circuit to operate in Mode 1 is

. 1,buckbuck DD ≥

If , the snubber circuit starts to operate in Mode 2. It is also required

that in this mode, the snubber diode D

1,buckbuck DD <

s1 anode voltage vs1 reaches E before the

MOSFET Q3 drain source voltage reaches vd in State (a). According to Equations

(6.24) and (6.25), the lower border condition for the snubber circuit to operate in

Mode 2 is:

[ ]0

1

0

)0(i

CvEiCv ossCsossd +

= (6.51)

According to Equation (6.31), the initial snubber capacitor Cs1 voltage vCs1(0) can be

278

found as:

10511 )()0( ZivEtvv dCsCs −−== (6.52)

Therefore Equation (6.51) can be simplified to:

022 10 =−− ZivE d (6.53)

Substituting Equations (6.46) and (6.49) to (6.53) and replacing Dbuck with Dbuck,2,

the lower border buck stage duty ratio for Mode 2 snubber operation, yield:

12

2,

211

1

ZE

PD

Davg

boost

buck

+−

= (6.54)


. 1,2, buckbuckbuck DDD <≤

If , the snubber circuit starts to operate in Mode 3. It is also required

that in this mode, the peak snubber diode D

2,buckbuck DD <

s1 anode voltage vs1 be greater than E in

State (b). According to Equation (6.36), the snubber diode Ds1 anode voltage vs1

reaches its peak at 3

12 2'

ωπ

+= tt . As 0)0(1 =Csv when the snubber circuit operates

at the border between Modes 3 and 4, the lower border condition for the snubber

279

circuit to operate in Mode 3 can be found as:

EZivd =+ 30 (6.55)

Substituting Equations (6.46) and (6.49) to (6.55) and replacing Dbuck with Dbuck,3,

the lower border buck stage duty ratio for Mode 3 snubber operation, yield:

32

3,

11

1

ZEP

D

Davg

boost

buck

+−

= (6.56)


. 2,3, buckbuckbuck DDD <<

If , the snubber circuit starts to operate in Mode 4, where the snubber

circuit is not active at all times in the converter operation.

3,buckbuck DD ≤

To illustrate the snubber operation a circuit model is developed with the following

parameters:

• The converter input voltage VE 20= and average power . WPavg 100=

• The boost stage switching frequency kHzfboost 75= and duty ratio

55.0=boostD .

280

• The transformer T2 leakage inductance HLle µ60.0= and the MOSFET Q3

Infineon SPB80N06S2L-07 output capacitance pFCoss 990= .

In the design of the snubber circuit, the leakage inductance can be considered as a

fixed value once the transformer T2 is designed. Therefore the peak switch voltage

over a low frequency cycle decreases with a larger snubber capacitance according to

Equation (6.12) while the range of Dbuck for Mode 1 snubber operation when the

snubber circuit returns the energy to the supply voltage increases with a smaller

snubber capacitance according to Equation (6.50). The snubber capacitance is

designed as 0.1 µF to obtain a reasonable peak switch voltage and range of Dbuck for

Mode 1 snubber operation. Once the snubber capacitance is determined, the peak

snubber inductor current over a low frequency cycle decreases with a larger snubber

inductance according to Equation (6.18) while the time duration of the non-zero

snubber inductor current decreases with a smaller snubber inductance according to

Equations (6.17), (6.22), (6.32) and (6.43). The snubber inductance is initially

designed as 10 µH. It is finally confirmed that the time duration of the non-zero

snubber inductor current is less than half of Tboost in Modes 1 to 3 and this justifies

the sharing of the snubber inductor by the two snubber circuits for Q3 and Q4.

The border conditions for the four operation modes of the snubber circuit can be

calculated and shown in Table 6.1.

281

Dbuck,1 Dbuck,2 Dbuck,3

0.706 0.396 0.119

Table 6.1 Border Conditions for Four Operation Modes of the Snubber Circuit

The peak switch voltage when 1=buckD can be calculated as 56.7 V and with a

small limit on the upper value of Dbuck MOSFETs with either 55 V or 60 V voltage

ratings may be considered in the circuit design. It is worth noting that the border

conditions in Table 6.1 are estimations only as the calculation assumes 990 pF

output capacitance of the MOSFET with 55 V voltage rating. In the practice a little

more margin in the voltage rating would be required. This is a reliability issue for

the practitioner and we will not further consider here.

Figure 6.14 shows the theoretical waveforms when 1=buckD and the snubber circuit

operates in Mode 1. This mode is characterised by the MOSFET Q3 drain source

voltage waveform with a small voltage slope at the turn-off due to the linear

charging of the relatively large snubber capacitance.

Figure 6.15 shows the theoretical waveforms when 60.0=buckD and the snubber

circuit operates in Mode 2. This mode is characterised by the MOSFET Q3 drain

source voltage waveform with an initial large voltage slope followed by a small

voltage slope at the turn-off due to the linear charging of the much smaller MOSFET

output capacitance first and then the larger snubber capacitance.

282

0 2 4 6 8 10 12 14 16 18 20 22 24 26-40

-30

-20

-10

0

10

20

30

40

0 2 4 6 8 10 12 14 16 18 20 22 24 26-40

-30

-20

-10

0

10

20

30

40

0 2 4 6 8 10 12 14 16 18 20 22 24 260

0.5

1

1.5

2

2.5

3

3.5

4

0 2 4 6 8 10 12 14 16 18 20 22 24 260

10

20

30

40

50

60

MO

SFET

Q3 D

rain

Sou

rce

Vol

tage

v Q3 (

V)

Snub

ber C

apac

itorC

s1 V

olta

gev C

s1 (V

)

t (µs)

t (µs)

Snub

ber I

nduc

torL

sr C

urre

nti L

sr (A

)

t (µs)

t (µs)

Snub

ber D

iode

Ds1

Ano

de V

olta

gev s

1 (V

)

Figure 6.14 Theoretical Waveforms in Mode 1 Snubber Operation

Figure 6.16 shows the theoretical waveforms when 35.0=buckD and the snubber

circuit operates in Mode 3. This mode is characterised by the MOSFET Q3 drain

source voltage waveform with large voltage slopes at the turn-off almost until it

reaches its peak due to the linear charging of the MOSFET output capacitance first

and the resonance between the MOSFET output capacitance and the transformer

leakage inductance. Then the resonance between the snubber capacitance and the

transformer leakage inductance only happens in a very short time before the

transformer primary current reaches i0.

283

0 2 4 6 8 10 12 14 16 18 20 22 24 26-20

-15

-10

-5

0

5

10

15

20

0 2 4 6 8 10 12 14 16 18 20 22 24 26-30

-20

-10

0

10

20

30

0 2 4 6 8 10 12 14 16 18 20 22 24 260

0.5

1

1.5

2

0 2 4 6 8 10 12 14 16 18 20 22 24 260

10

20

30

40

50

60

MO

SFET

Q3 D

rain

Sou

rce

Vol

tage

v Q3 (

V)

Snub

ber C

apac

itorC

s1 V

olta

gev C

s1 (V

)

t (µs)

t (µs)

Snub

ber I

nduc

torL

sr C

urre

nti L

sr (A

)

t (µs)

t (µs)

Snub

ber D

iode

Ds1

Ano

de V

olta

gev s

1 (V

)


The experimental waveforms of the snubber circuit operating in Modes 1, 2 and 3

are respectively shown in Figures 6.17 to 6.19. From top to bottom, Figures 6.17 to

6.19 respectively shows the MOSFET Q3 drain source voltage vQ3, the diode Ds1

anode voltage vs1 and the snubber inductor Lsr current iLsr. The key components

used in the snubber circuit are:

284

0 2 4 6 8 10 12 14 16 18 20 22 24 260

0.05

0.1

0.15

0.2

0 2 4 6 8 10 12 14 16 18 20 22 24 26-30

-20

-10

0

10

20

30

0 2 4 6 8 10 12 14 16 18 20 22 24 26-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

0 2 4 6 8 10 12 14 16 18 20 22 24 260

10

20

30

40

50

60

MO

SFET

Q3 D

rain

Sou

rce

Vol

tage

v Q3 (

V)

Snub

ber C

apac

itorC

s1 V

olta

gev C

s1 (V

)

t (µs)

t (µs)

Snub

ber I

nduc

torL

sr C

urre

nti L

sr (A

)

t (µs)

t (µs)

Snub

ber D

iode

Ds1

Ano

de V

olta

gev s

1 (V

)


• Capacitors Cs1 and Cs2 – Kemet class X7R surface mount capacitor

C0805C104K5RAC, FC µ1.0= , VVdc 50= .

• Inductor Lsr – Core type Siemens RM7 with 0.16 mm air gap in the centre

pole, ferrite grade Siemens N48, inductor winding 7=LN turns.

• Diodes Ds1, Ds2, Dsr1 and Dsr2 – Fairchild SS26, AI F 0.2= , ,

.

VVRRM 60=

VVF 7.0=

285

Figure 6.17 Experimental Waveforms in Mode 1 Snubber Operation


286


The buck stage duty ratios in Figures 6.17 and 6.19 are respectively ,

and and these are estimated by the individual

instantaneous converter output voltages captured by the oscilloscope.

84.0=buckD

57.0=buckD 38.0=buckD

The characteristics of the individual operation modes can be clearly observed

although the buck stage duty ratio is not a constant under the consecutive high

frequency cycles in the practical converter. Some differences between the

theoretical and the experimental waveforms lie on the damped oscillations after the

MOSFET Q3 drain source voltage vQ3 reaches its peak due to the resonance between

the MOSFET output capacitance and the transformer leakage inductance and as well

287

on the voltage source vd being not a constant due to the voltage ripple on the

capacitors in the voltage-doubler rectifier of the boost cell.


In the practical implementation of the hard-switched current fed two-inductor boost

converter with the power rating of 100 W, the switching frequency of the buck stage

MOSFETs fbuck and that of the boost stage MOSFETs fboost are respectively selected

to be and kHzfbuck 150= kHzfboost 75= .

The two-phase synchronous buck converter is based upon a commercial two-phase

synchronous step-down switching regulator – Linear Technology LTC1929CG. The

standard control loop is modified slightly to secure a widely variable output voltage

range. Two current transformers are used to sense the control MOSFET drain

current to accomplish the chip-embedded current mode control, which is critical in

the converter as it prevents the IPT from saturation. The current transformers also

allow the output voltage range of the control to be extended to 0 to 20 V. On the

other hand, the IPT is also gapped so that it will not saturate under a certain level of

unbalanced current from the two-phase buck converter. The switching timing of the

two-phase buck converter is synchronised with the synchronising signal generated

by the regulating pulse width modulator – Unitrode UC3526A, which is used as the

switching controller for the MOSFETs in the two-inductor boost cell.

288

In order to remove the power loss related to the diode reverse recovery in the

voltage-doubler rectifier, Schottky diodes are preferred instead of normal PN

junction diodes. However, normal Schottky diodes are not qualified as they have

only low reverse breakdown voltage ratings. Therefore, silicon carbide Schottky

diodes, which have high reverse breakdown voltage ratings and near-zero reverse

recovery time, are suited in this application [174]. These diodes are targeted toward

the single phase boost rectifier market. This too is a 400-V boost converter design

and has similar reverse recovery issues.

To avoid the high side drivers and the additional control circuitry for the MOSFETs

in the unfolder, electrically isolated optical MOSFET drivers – Dionics DIG-11-15-

30-DD are used to provide the MOSFET gate signals. The selected MOSFET driver

has an output open circuit voltage of 15 V, a short circuit current of 60 µA at input

current of 30 mA with 50% duty cycle and an isolation voltage of 2500 V. The

MOSFET gate charging current from the integrated driver is large enough to achieve

short turn-on transitions. The integrated driver also has an embedded active

discharge circuit to discharge the MOSFET gate capacitance so that fast turn-off

behaviours can be easily obtained.

Other main components used in the converter are listed below:

• MOSFETs Q1, Q2, Q5 and Q6 – International Rectifier IRF7809AV,

, , VVDS 30= AI D 3.13= Ω= 009.0)(onDSR .

289

• Diodes D1 and D2 – ON Semiconductor MRBS130LT3, , AIF 0.1=

VVRRM 30= , . VVF 395.0=

• IPT T1 – Core type Epcos EFD15 with a 0.35-mm air gap in each of the three

core legs, ferrite grade Epcos N87, primary winding turns and

secondary winding

141 =pN

141 =sN turns.

• Inductors L1 and L2 and transformer T2 – Core type Ferroxube ETD39 with a

0.5-mm air gap in each of the two outer legs, ferrite grade Ferroxube 3F3,

Structure A magnetic integration, inductor winding turns,

primary winding

2321 == LL NN

232 =pN turns, secondary winding turns. 982 =sN

• MOSFETs Q3 and Q4 – Infineon SPB80N06S2L-07, ,

,

VVDS 55=

AI D 80= Ω= 007.0)(onDSR .

• Diodes D3 and D4 – Microsemi UPSC600, AI F 0.1= , ,

.

VVRRM 600=

VVF 6.1=

• Capacitors CO1 and CO2 – Vishay class X7R multilayer ceramic surface

mount capacitor VJ1210Y104KXCAT, FC µ1.0= , . VVdc 200=

• MOSFETs S1 to S4 – International Rectifier IRF830AS, ,

,

VVDS 500=

AI D 0.5= Ω= 4.1)(onDSR .

Figure 6.20 shows the buck converter waveforms under static tests. From top to

bottom, Figures 6.20(a) and (b) respectively shows the waveforms of v1, v2 and vH

with Dbuck lower and greater than 50%. The voltage after the IPT swings between

290

zero and the half input voltage when %50<buckD while it swings between the half

and the full input voltages when . In both cases, the frequency of the

voltage v

%50>buckD

H after the IPT is twice that of the voltage v1 or v2.

Figure 6.21 shows the waveforms of the two-inductor boost converter output voltage

vC and the input voltage vH from top to bottom with the sinusoidal modulation. A

three-level modulation can be clearly seen from the vH waveform although the

displayed waveform is heavily aliased. The screen of the oscilloscope has a limited

number of pixels therefore only the envelope of the PWM waveform is evident and

asymmetry exists in the displayed vH waveform. Small voltage spikes appear every

half grid frequency cycle because all four switches in the unfolder turn off for a

small amount of time around the zero crossing of the sinusoidal waveform.

Figure 6.22 shows the gate waveforms of the low frequency unfolder switches and

the output voltage vO from top to bottom. In this case a resistive load is supplied

and this is adjusted to give the rated power, 100 W average, at 240 V ac, which is

equivalent to the nominal mains voltage.

Figure 6.23 shows the MOSFETs Q3 and Q4 drain source voltages and the voltage

across the SiC Schottky diode when the converter output voltage is close to its peak.

The snubber circuit controls the maximum peak switch voltage in a low frequency

cycle to around 50 V. Technically, this allows the MOSFETs with drain-source

breakdown voltage ratings of 55 V to be used in the boost cell. In a commercial

291

application a large voltage margin would be desired from a reliability view point.

The SiC diode voltage waveform is relatively clean although some high frequency

oscillations exist due to the resonance between the transformer leakage inductance

referred to the secondary and the diode junction capacitance.

Figure 6.24 shows the MOSFET Q3 drain source voltage vQ3 and the diode Ds1

anode voltage vs1 from top to bottom when the snubber circuit operates in Mode 1.

These have been analysed in detail in Section 6.2.2.

In the hard-switched current fed two-inductor boost converter, a conversion

efficiency of 92% at the rated power rating of 100 W was obtained. Both the input

and the output powers were measured using the mathematical functions of a

Tektronix TDS5034 four-channel oscilloscope equipped with the voltage and the

current probes measuring the converter input and output voltages and currents. The

current probes are Tektronix TCP202. The power loss includes the losses in all

three conversion stages in the hard-switched current fed two-inductor boost

converter including the buck, the boost and the unfolding stages.

292

(a)

(b)

Figure 6.20 Experimental Waveforms in the Two-Phase Buck Converter


293

100V

Figure 6.21 Experimental Waveforms of the Sinusoidal Modulation

250V

Figure 6.22 Experimental Waveforms in the Unfolder

294

250V

Figure 6.23 Experimental Waveforms in the Two-Inductor Boost Cell

Figure 6.24 Experimental Waveforms in the Snubber

295

A photo of the prototype hard-switched current fed two-inductor boost converter is

shown in Figure 6.25. At the time of writing the converter had not been operated in

a grid interactive mode. There is no obvious technical impediment. However, to do

so would require the development of a suitable control system and this will require

additional time. This is an area of future work.

Figure 6.25 Photo of the Hard-Switched Current Fed Two-Inductor Boost Converter

6.3 Soft-Switched Current Fed Two-Inductor Boost Converter

This section provides a detailed analysis of the soft-switched current fed two-


296


Figure 6.26 shows the soft-switched two-inductor boost converter with a two-phase

synchronous buck converter, where a resistive load is used.

L2

C1 C2

Lr

Q3 Q4

T2

DQ4DQ3

E D1 D2

T1

+

−

+

−

+

−

Q1

Q2

Q6Q5 v1 v2 vH+

−vC1

+

−vC2

L1

D4

D3

CO2

+ −

S1 S2

S3S4

CO1

+

−

vO

T2vC

Figure 6.26 Soft-Switched Two-Inductor Boost Converter with a Two-Phase

Synchronous Buck Converter

The buck and the unfolding stages of the converter are the same as those in the hard-

switched current fed two-inductor boost converter and their transfer functions are

respectively given by Equations (6.1) and (6.3). The transfer function of the boost

stage is determined by the converter design parameters such as the resonant

inductance, capacitance and the load condition.

As a constant gain is required in the boost stage, the soft-switched two-inductor

boost cell is able to operate under the fixed switching frequency and switch duty

ratio. Therefore, an optimised operating point, which is favourable in the power loss

respect, can be selected for the boost cell as discussed in Chapter 4. However as the

input voltage of the boost cell follows an absolute sine function as given by

Equation (6.4), the average variable power loss over a low frequency sinusoidal

297

cycle, Ploss,avg, must be established instead so that the operating point with the

minimum average power loss in the boost cell can be identified. The calculation can

be performed numerically with the MATLAB program with the same set of the

component parameters used in Section 4.6.1. The average power loss in Regions 1

and 2 are respectively drawn in Figures 6.27 and 6.28.

k∆1

P los

s,avg

(W)

Figure 6.27 Average Variable Power Loss in Region 1

Following the same process in Section 4.6.2, the circuit parameters are selected to be

, and 1.1=k 01 =∆ 0=dα , where the average power loss is 2.33 W and the peak

switch voltage is 90 V. Then the design parameters can be obtained as below:

298

• The resonant inductance HLr µ40.1= .

• The resonant capacitance nFCr 7.15= .

• The transformer T2 turns ratio 95.32 =Tn .

kαd (radians)

P los

s,avg

(W)

Figure 6.28 Average Variable Power Loss in Region 2

6.3.2 Resonant Gate Drive

The two-inductor boost cell in the converter shown in Figure 6.26 employs the

resonant technique and ZVS can be achieved. Theoretically, the switching power

losses in the main switching devices are completely removed. However, higher

current and voltage stresses exist due to the resonant feature and they lead to higher

299

conduction power losses in the switching devices. In the converter design, attention

has to be paid to the conduction power losses so that the reduction in the switching

power losses will not be forfeited. Therefore, the resistance in the conduction paths

must be minimised and MOSFETs with low drain source on resistances are

desirable. A low MOSFET drain source on resistance normally demands a large die

size and the MOSFET input capacitance tends to be large [175]. This results in high

power losses in the drive circuit if a conventional MOSFET gate drive circuit is

used.

The conventional MOSFET gate drive circuit commonly employs two transistors in

the totem-pole arrangement as shown in Figure 6.29.

VDDQp

Qt

Qb

Figure 6.29 Conventional MOSFET Gate Drive Circuit

In Figure 6.29, Qt and Qb are the control transistors in the gate drive circuit and Qp is

the power MOSFET in the main circuit. VDD is the gate drive circuit supply voltage.

While the conventional MOSFET driver is easy to use and has a compact package

readily available in the integrated semiconductor chip format, it is subject to the

following power loss mechanisms [176]:

300

• loss, which is caused by the MOSFET gate capacitance charging and

discharging current flowing through the drain source on resistances of the

two control transistors in the driver Q

2CV

t and Qb and the internal gate resistance

of the power MOSFET Qp.

• Cross conduction loss, which results from the shorting of the supply voltage

across the two transistors Qt and Qb in the driver if their on times are

overlapped to any degree.

• Switching loss, which is due to the hard switching conditions of the two

transistors Qt and Qb in the driver.

Among these power losses, loss is the dominant part. It is independent of the

gate charge rate and will not reduce with shorter gate charging times. Therefore, a

high MOSFET input capacitance requires high gate charge from the drive circuit and

causes high loss in the conventional MOSFET drivers. The drive power is

exacerbated when the switching frequency is high as the power dissipation is

proportional to the switching frequency.

2CV

2CV

In order to reduce the power consumption in the MOSFET gate drive circuit, the

resonant technique can be used and many types of the resonant gate drive circuits

have been proposed [147], [176]-[181]. In [176] and [177], higher than normal

charging or discharging current due to the resonant operation flows through the

transistors in the drive circuit and the conduction power loss is still high. In [178]-

[180], the power loss of the drive circuit cannot be minimised as transistors in the

301

gate drive circuit still switch under the hard-switching conditions. In [147] and

[181], an ideally lossless gate drive circuit has been proposed as shown in Figure

6.30. Both of the MOSFET turn-on and turn-off are achieved by using a small

inductor LG to provide current to charge and discharge the input capacitance of the

MOSFET during a transition time when neither of the control transistors in the drive

circuit conducts. A capacitor CG, is required to maintain a dc level equal to the

average gate voltage.

VDD

QpLG

CG

Qt

Qb

Figure 6.30 Resonant Transition Gate Drive Proposed in [147] and [181]

In the two-inductor boost converter, the gate signals of the two MOSFETs are 180º

out of phase and this allows the gate charging inductor LG to be shared by the two

drive circuits and the dc level setting capacitor CG to be removed. The individual

MOSFET input capacitances function as the dc level setting capacitor for each other.

Figure 6.31 shows the proposed resonant transition gate drive circuit for the two-

inductor boost converter. Compared with the conventional MOSFET gate drive

circuit shown in Figure 6.29, only one small inductor LG is introduced between the

gates of the two power MOSFETs Q3 and Q4.

302

iLG

iG3

VDD

Q3t

Q3b

Q3

Q4t

Q4b

Q4VDD

LG

vQ3G

+

−

vQ4G

+

−

+ −vLG

iQ3t

iQ3b

iQ4t

iQ4biG4

Figure 6.31 Resonant Transition Gate Drive for the Two-Inductor Boost Cell

Although the resonant gate drive circuit in Figure 6.31 is not significantly more

complex than the conventional MOSFET gate drive circuit and the component count

is not greatly higher, the control of the resonant gate drive circuit does become much

more complex and this is especially true compared with that of the integrated

MOSFET driver chips. The operation of the resonant transition gate drive circuit

can be explained using the waveforms shown in Figure 6.32.

The inductor current can be approximated as a constant during the time interval

between the instant when one MOSFET gate capacitance starts being charged and

the instant when the other MOSFET gate capacitance finishes being discharged.

This time interval is insignificantly short compared with the entire switching period

Tboost as long as the switching duty ratio Dboost is not significantly larger than 50%.

Therefore the MOSFET gate capacitances are charged and discharged linearly. The

MOSFETs Q3 and Q4 are considered to be fully on when the individual gate

capacitance voltages are higher than half of the gate drive supply voltage VDD.

During the time interval Td1, the gate capacitance of Q4 is charged. The gate

303

capacitance of Q3 is later discharged over a time interval of the same length. The

two P type transistors Q3t and Q4t turn on and tie the gates of the power MOSFETs

to the positive rail of the gate drive circuit power supply once the gate capacitances

are charged to that level while the two N type transistors Q3b and Q4b turn on and tie

the gates of the power MOSFETs to the ground once the gate capacitances are

completely discharged. During the time interval Td2, when Q3 is on and Q4 is off,

the inductor current linearly increases from the negative peak to the positive peak.

Therefore the energy is transferred back and forth between two MOSFET gate

capacitances through the inductor.

Q3t Q3b

Q4tQ4b

vQ3G

vQ4G

vLG

iLGILGp

−ILGp

VDD

−VDD

VDD

VDD

Td2

On

Dev

ices Q3t

Q4bQ4t

Td1

0 DboostTboost Tboost t




Figure 6.32 Theoretical Waveforms in the Resonant Transition Gate Drive

304

Theoretically, the resonant gate drive circuit has zero power loss due to the

following features:

• The MOSFET input capacitance is charged and discharged by the inductor

current and loss can be removed. 2CV

• A transition time or dead time of Td1 exists between the turn-on of the two

transistors in the totem-pole arrangement in the gate drive circuit and the

cross conduction loss can be avoided.

• Both transistors in the gate drive circuit turn on or off at zero voltage or zero

current and the switching power loss is absent.

In the gate drive circuit design and power loss analysis, a dead time ratio ρ is

defined as:

boost

d

TT 1=ρ (6.57)

Therefore the inductor linear charging or discharging interval can be obtained as:

boostboostd TDT )1(2 ρ−−= (6.58)

Assuming that the input capacitance of the MOSFET Q3 or Q4 is Ciss, the peak

inductor current ILGp and the inductance LG are respectively:

305

ρboostDDiss

LGpfVC

I = (6.59)

boostLGp

DDboostG fI

VDL

2)1( ρ−−

= (6.60)

Theoretically, the resonant transition gate drive is lossless. However, the inductor

current iLG also flows through the top transistor Q3t or Q4t when the gate capacitance

of the MOSFET Q3 or Q4 is fully charged, through the bottom transistor Q3b or Q4b

when the gate capacitance of the MOSFET Q3 or Q4 is fully discharged and through

the gate of the MOSFET Q3 or Q4 during the gate charging and discharging

intervals. Therefore, due to the parasitic effects, a small amount of power loss still

exists and has the following origins:

• The power loss in the inductor between the gates of the two MOSFETs : LGP

2,rmsLGLGLG IRP = (6.61)

where RLG is the equivalent series dc plus ac resistance of LG and ILG,rms is

the effective current in LG.

• The conduction power loss in the four control transistors in the drive circuit

: condtbQP ,34

306

)(2 2,3),(

2,3),(,34 rmsbQbonDSrmstQtonDScondtbQ IRIRP += (6.62)

where RDS(on),t and RDS(on),b are respectively the drain source on resistances of

the top and the bottom transistors and IQ3t,rms and IQ3b,rms are respectively the

effective currents in Q3t and Q3b.

• The conduction power loss in the gate of the two power MOSFETs : 34QP

2,334 2 rmsGgQ IRP = (6.63)

where Rg is the internal gate resistance of the power MOSFET and IG3,rms is

the effective charging and discharging current in the gate of Q3.

• The loss in the drive circuit of the four control transistors : 2CV drivetbQP ,34

boostDDbisstissdrivetbQ fVCCP 2,,,34 )(2 += (6.64)

where Ciss,t and Ciss,b are respectively the input capacitances of the top and

the bottom transistors and it is assumed that the supply voltage is also VDD in

the gate drive circuit for the control transistors.

If the duty ratio Dboost is not significantly larger than 50% and the zero inductor

voltage period in Figure 6.32 can be neglected, the current terms in Equations (6.61)

307

to (6.63) can be respectively found as:

LGprmsLG II381

,ρ+

= (6.65)

LGprmstQ II681

,3ρ+

= (6.66)

LGprmsbQ II641

,3ρ−

= (6.67)

LGprmsG II ρ2,3 = (6.68)

It is worth noting that Equations (6.65) to (6.68) can be also used to estimate the

individual effective currents when the charging or discharging intervals of Q3 and Q4

overlap as long as ρ is kept small.

The total power loss in the resonant transition gate drive circuit is:

drivetbQQcondtbQLGdrive PPPPP ,3434,34 +++= (6.69)

Equations (6.61) to (6.69) confirm that the power loss in the gate drive circuit is very

small if the parasitic component values are small.

The MOSFET input capacitance includes gate-to-drain and gate-to-source

capacitances. Due to the Miller Effect, the input capacitance is highly non-linear

and the total gate charge QG is therefore a better parameter in determining the turn-

308

on and the turn-off characteristics of the MOSFET [182]. Consequently, the peak

inductor current can be found more accurately as:

ρboostG

LGpfQ

I = (6.70)

In the selection of the transistors in the MOSFET gate drive circuit, special attention

must be paid to their total gate charges, which must be at least an order of magnitude

less than those of the power MOSFETs. Apart from being an additional loss term, a

low gate charge of the transistor is a must in obtaining fast turn-on and turn-off

transitions. A short turn-on transition after the power MOSFET input capacitance is

charged to the supply voltage stops the peak inductor current from flowing through

the reverse body diode of the transistors. Otherwise, higher conduction power loss

could result due to the high forward voltage of the transistor reverse body diode.

Moreover, if the dead time is very short, the turn-on and the turn-off transitions of

the transistors must be kept minimal to ensure that the on times of the two transistors

in the totem-pole do not overlap.

In the practical operation of the resonant transition gate drive circuit, the MOSFET

gate charging and discharging currents are not a constant as the inductor between

two gates resonates with the MOSFET input capacitance when both control

transistors in its drive circuit are turned off. Therefore, the actual charging and

discharging currents iG3 and iG4 follow the sinusoidal waveform and their absolute

values are higher than the absolute inductor current iLG at the end of its linear

309

charging or discharging interval. If the average of the absolute of iG3 or iG4 is IG and

the absolute value of iLG at the end of its linear charging or discharging interval is

ILG’, where , Equations (6.60) and (6.70) can be respectively rewritten to: 'LGG II >

boostLG

DDboostG fI

VDL

'2)1( ρ−−

= (6.71)

ρboostG

GfQ

I = (6.72)

However, ILG’ in Equation (6.71) cannot be easily obtained and this makes the

inductor design difficult. In order to simplify the design process of the inductance

LG, ILG’ can be approximated by IG in Equation (6.72) as ρ is small. Equation

(6.71) can be further rewritten to:

boostG

DDboostG fI

VDL

2)1( ρ−−

= (6.73)

As , the actual inductance value should be selected to be slightly larger

than what is calculated from Equation (6.73).

'LGG II >

A simulation is performed with SIMULINK with the following parameters:

• The gate drive circuit supply voltage VVDD 12= ,

• The total gate charge of the MOSFET STB50NE10 nCQG 123= ,

310

• The switching frequency kHzfboost 500= , the duty ratio and the

dead time ratio

6.0=boostD

1.0=ρ , and

• The inductor in the gate drive circuit HLG µ3.7= .

The two power MOSFETs Q3 and Q4 are modelled by two capacitors and the

capacitance values are derived from the total gate charge. The four control

transistors Q3t, Q3b, Q4t and Q4b in the gate drive circuit are modelled by the ideal

switches. The inductance in the resonant gate drive circuit is first calculated as

HLG µ85.5= from Equations (6.72) and (6.73) and then an adjustment is made to

remove the over voltage on the input capacitance at the MOSFET turn-on and the

under voltage on the input capacitance at the MOSFET turn-off.

The simulation waveforms are shown in Figure 6.33. They respectively show the

waveforms of the MOSFETs Q3 and Q4 gate voltages and the inductor LG voltage

and current. The simulation waveforms agree well with the waveforms in Figure

6.32 except that the zero inductor voltage intervals do not exist in this particular

case.

311

0 1 2 3 4-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 1 2 3 4-10

-5

0

5

10

15

20

0 1 2 3 4-10

-5

0

5

10

15

20

0 1 2 3 4-20

-15

-10

-5

0

5

10

15

20

Indu

ctor

L G C

urre

nti L

G (A

)

t (µs)

t (µs)

t (µs)

t (µs)

MO

SFET

Q3 G

ate

Vol

tage

v Q3G

(V)

MO

SFET

Q4 G

ate

Vol

tage

v Q4G

(V)

Indu

ctor

L GV

olta

gev L

G (V

)

Figure 6.33 Simulation Waveforms of the Resonant Transition Gate Drive

Figure 6.34 shows the experimental waveforms. The main components used in the

resonant transition gate drive circuit are:

• High side transistors Q3t and Q4t – P channel MOSFET International

Rectifier IRLML5103, VVDS 30−= , AI D 76.0−= , Ω= 60.0)(onDSR ,

. nCQ tG 4.3, =

• Low side transistors Q3b and Q4b – N channel MOSFET International

Rectifier IRLML2803, VVDS 30= , AID 2.1= , Ω= 25.0)(onDSR ,

nCQ bG 3.3, = .

312

(a)

(b) (d)

200 mA(c)

Figure 6.34 Experimental Waveforms of the Resonant Transition Gate Drive

(a) MOSFETs Q3t, Q3b and Q3 Gate Voltages

(b) MOSFETs Q4t, Q4b and Q4 Gate Voltages

(c) Inductor LG Current

(d) MOSFETs Q3 and Q4 Drain Source Voltages

• Inductor LG – Core type Philips ETD44 with 1.6-mm air gap in the centre

leg, ferrite grade Philips 3F3, Litz wire made up of 34 strands of 0.11-mm

313

(0.135-mm overall diameter) wire, inductor winding turns and 7=LGN

HLG µ98.6= , series dc plus ac resistance Ω= 99.0LGR at 500 kHz.


,

AI D 50=

Ω= 027.0)(onDSR nFCoss 675.0= , Ω= 5.1gR .

The experimental waveforms match well with the simulation waveforms shown in

Figure 6.33. From top to bottom, Figure 6.34(a) shows the gate voltage waveforms

of Q3t, Q3b and Q3 and Figure 6.34(b) shows those of Q4t, Q4b and Q4. After turn-on

of the control transistors in the gate drive circuit, an over voltage or under voltage

appears on the gate waveforms of Q3 and Q4. This is caused by the voltage drop

across the embedded reverse body diodes of the transistors. Figure 6.34(c) shows

the current waveform in the inductor between the gates. When one of the MOSFETs

Q3 and Q4 is fully on and the other is fully off, the inductor current linearly increases

or decreases as the voltage across the inductor is a constant. Figure 6.34(d) shows

the drain source voltage waveforms of Q3 and Q4 from top to bottom. The

waveforms confirm that the two power MOSFETs Q3 and Q4 turn on at zero voltage.

Table 6.2 shows the comparisons of the power consumptions in the resonant

transition and the conventional gate drive circuits. The conventional gate drive

circuit employs the regulating pulse width modulator – Unitrode UC3526A and the

MOSFET driver – MAXIM MAX4429.

314

Power Resonant Transition Gate Drive Circuit

Conventional Gate Drive Circuit

Control Signal Generation (W) 0.66 0.72

Control Transistors and Power MOSFETs Driving (W) 0.72 2.75

Total (W) 1.38 3.47

Table 6.2 Power Consumptions in Two Gate Drive Circuits

An estimated power loss breakdown for the MOSFET driving power loss in the

resonant transition gate drive circuit using Equations (6.61) to (6.64) is given in

Table 6.3.

Component Power Loss (W)

Inductor 0.22

Control Transistors Conduction 0.16

Power MOSFETs Gate Resistance 0.23

Control Transistors Driving 0.08

Total 0.69

Table 6.3 Resonant Transition Gate Drive Power Loss Breakdown

In the estimation of the loss of the four control transistors, in order to use the

total gate charges of the control transistors instead of the gate input capacitances,

Equation (6.64) is rewritten to:

2CV

boostDDbGtGdrivetbQ fVQQP )(2 ,,,34 += (6.74)

315

where QG,t and QG,b are respectively the total gate charges of the top and the bottom

transistors. The calculated total power loss is 0.69 W and agrees favourably with the

MOSFET driving power loss in the experiment.

The size of the inductor used in the drive circuit is relatively large compared with

that of the control transistors. Therefore, Newport Component 2200 series miniature

axial lead inductors with high quality factors are used in the converter. This type of

inductor has a body length of 10 mm and diameter of 4 mm. A series connection of

two 1-µH and one 4.7-µH axial inductors are finally used in the drive circuit for the

soft-switched current fed two-inductor boost converter, where under

the operating point selected in Section 6.3.1. A slightly higher drive power of 0.83

W is observed.

615.0=boostD

The control signals in both of the drive circuits are generated by the analogue

circuitry and the control signal generation consumes the same level of power as that

in the conventional gate drive circuit. However, compared with the conventional

gate drive circuit, the resonant gate drive circuit saves around 2 W in driving the

four control transistors and the two power MOSFETs and this improves the overall

efficiency of a 100-W converter by around 2%.


In the practical implementation of the soft-switched current fed two-inductor boost

316

converter with the power rating of 100 W, the switching frequency of the buck stage

MOSFETs fbuck and that of the boost stage MOSFETs fboost are respectively selected

to be and kHzfbuck 250= kHzfboost 500= .

The arrangement for the buck conversion stage is the same as that in the hard-

switched current fed two-inductor boost converter except that the switching timing

of the two-phase buck converter is synchronised with the signal from a frequency

divider, whose input is the gate signal for the MOSFETs in the two-inductor boost

cell.

The components used in the buck stage, the rectification stage of the boost cell and

the unfolding stage are the same as those in the hard-switched current fed two-

inductor boost converter. Other main components used in the converter are listed

below:

• Inductors L1 and L2 – Core type Ferroxube ETD29 with a 0.5-mm air gap in

each of the two outer legs, ferrite grade Ferroxube 3F3, two inductor

windings respectively on two outer legs, inductor winding turns. 20=LN

• Transformer T2 – Core type Ferroxube ETD29, ferrite grade Ferroxube 3F3,

primary and secondary wires: Litz wires respectively made up 36 and 10


52 =pN turns, secondary winding 202 =sN turns, leakage inductance

reflected to the transformer T2 primary HLle µ25.0= .

317

• Additional resonant inductor – Core type air core toroidal, inductor wire:

Litz wire made up 50 strands of 0.11-mm (0.135 mm overall diameter) wire,

quality factor , 1.25 µH measured inductance. 96=Q

• Additional resonant capacitors – Cornell Dubilier surface mount mica

capacitor MC22FA202J, 2 nF, VVdc 100= , 60001=DF at 500 kHz, 15

nF capacitance used.

Figure 6.35 shows the buck converter waveforms under static tests. From top to

bottom, Figures 6.35(a) and (b) respectively shows the waveforms of v1, v2 and vH

with the duty ratio lower and greater than 50%. The voltage after the IPT swings

between zero and the half input voltage when %50<buckD while it swings between

the half and the full input voltages when . In both cases, the frequency

of the voltage v

%50>buckD

H after the IPT is twice that of the voltage v1 or v2.

Figure 6.36 shows the two-inductor boost converter output voltage vC and the input

voltage vH from top to bottom with the sinusoidal modulation. A three-level

modulation can be obviously observed in the vH waveform although the waveform

displayed by the oscilloscope is heavily aliased. The screen of the oscilloscope has a

limited number of pixels therefore only the envelope of the PWM waveform is

evident and asymmetry exists in the displayed vH waveform.

Figure 6.37 shows the gate waveforms of the low frequency unfolder switches and

the output voltage vO from top to bottom. In this case a resistive load is supplied

318

and this is adjusted to give the rated power, 100 W average, at 240 V ac, which is

equivalent to the nominal mains voltage.

From top to bottom, Figure 6.38 shows the gate and drain source voltage waveforms

of the MOSFETs in the ZVS two-inductor boost cell when the output voltage is

close to its peak. The MOSFET drain source voltage waveforms confirm that the

MOSFETs turn on at zero voltage.

Figure 6.39 shows the voltage across the diode in the voltage-doubler rectifier when

the output voltage is close to its peak. The waveform is relatively clean. No reverse

recovery can be seen in the SiC Schottky diodes although some lower frequency

oscillations with an approximate 200-ns period can be seen. These are due to the

resonance between the diode junction capacitance and the inductance in series with

the transformer T2 secondary winding including the leakage inductance and the

additional resonant inductance referred to the secondary.

In the soft-switched current fed two-inductor boost converter, a conversion

efficiency of 91% at the rated power rating of 100 W was obtained. Both the input

and the output powers were measured with the same equipment as in the hard-

switched current fed two-inductor boost converter.

319

(b)

(a)

Figure 6.35 Experimental Waveforms in the Two-Phase Buck Converter


320

100V

Figure 6.36 Experimental Waveforms of the Sinusoidal Modulation

250V

Figure 6.37 Experimental Waveforms in the Unfolder

321

Figure 6.38 Experimental Waveforms in the Two-Inductor Boost Cell

100V

Figure 6.39 Experimental Waveform of the Diode Voltage

322

A photo of the prototype soft-switched current fed two-inductor boost converter is

shown in Figure 6.40. Like the hard-switched current fed two-inductor boost

converter, this converter had not been operated in a grid interactive mode at the time

of writing and this is an area of future work.

Figure 6.40 Photo of the Soft-Switched Current Fed Two-Inductor Boost Converter

6.4 Summary

In this chapter, the MIC implementations employing the two-inductor boost

topology with an unfolding stage are discussed. Both of the hard-switched and the

soft-switched forms of the two-inductor boost converter are developed. In the hard-

switched current fed two-inductor boost converter, non-dissipative snubbers are

analysed in detail while in the soft-switched current fed two-inductor boost

323

converter, the resonant transition gate drive circuit is thoroughly investigated. The

hard-switched and the soft-switched current fed two-inductor boost converters have

respectively achieved 92% and 91% efficiency at the rated power rating of 100 W.

324

7. TWO-INDUCTOR BOOST CONVERTER WITH A

FREQUENCY CHANGER

Parts of this chapter have been published in the Proceedings of AUPEC 2002.

In Chapter 3, MIC implementations with a frequency changer based on the two-

inductor boost converter is proposed as shown in Figure 3.12. This chapter provides

a detailed theoretical analysis of the two-inductor boost converter with a frequency

changer. The simulation results are also provided to validate the theoretical

analysis.

An experimental implementation was not attempted for this converter. A judgement

had to be made in the early part of the thesis as to how resources, especially time,

would be allocated. This converter requires bi-directional switches in the converter

secondary side, reverse blocking switches in the converter primary side and the

control complexity was judged to be high. The possibility of utilising a load

capacitor for 100-Hz power balance was judged to be novel and it was decided that

this feature should at least be illustrated via a simulation study. Obviously a

challenge remains for those interested in experimenting with a physical

implementation.

325

7.1 Introduction

Common to the MIC implementations shown in Figures 3.8 to 3.11 is the existence

of the constant or variable dc link between the dc-dc converter and the dc-ac

converter. This approach has the following advantages:

• It is relatively easy to implement with the relatively independent designs for

the two separate converters.

• The high voltage dc link may provide a location where the capacitive energy

storage can be included for single-phase applications.

However, this approach has three apparent trade-offs:

• Two separate converters generally demand a larger PCB space than one

single converter.

• The dc link between the two converters requires the presence of the reactive

components as filters such as inductors and capacitors and this usually

contributes significantly to the total weight and volume [183].

• Electrolytic capacitors are most often used for the energy storage and

significantly increase the converter volume and raise the failure rates [184].

To avoid these trade-offs, the two-inductor boost converter with a frequency changer

is proposed.

326

7.2 Two-Inductor Boost Converter with a Frequency Changer

This section provides an in-depth analysis of the two-inductor boost converter with a

frequency changer.


In the two-inductor boost converter with a frequency changer, the rectification stage

of the original dc-dc converter is replaced by the frequency changer to transform the

high frequency ac voltage directly into the low frequency ac voltage. In order to

avoid the need for the energy storage in the two-inductor boost converter and

employ the minimum number of the switching devices in the frequency changer,

three bi-directional switches are used to provide a two-phase output including a

resistive load and a power balancing capacitor as shown in Figure 3.12. To simplify

the discussion, the converter can be redrawn in Figure 7.1, where S1, S2 and S3 are

all bi-directional switches. The MOSFETs Qj1 and Qj2 in Figure 3.12 respectively

turns on to allow the positive or the negative transformer secondary current as

illustrated to flow through the switch Sj, where 3,2,1=j . In Figure 7.1, two diodes

D1 and D2 are respectively connected in series with the MOSFETs Q1 and Q2 as

negative drain source voltages exist in this application due to the power balance

feature.

The voltage waveform of the power balancing capacitor is controlled to achieve a

constant power when it is combined with the single phase resistive load. At least

327

three bi-directional switches must be used to offer three degrees of freedom in

controlling the resistive load current, the power balancing capacitor current and the

volt-second balance of the high frequency transformer. The closings of the three bi-

directional switches will direct either the positive or the negative transformer current

into the load R and the capacitor Cb. Compared with the power balancing capacitor

Cb, the capacitors Ct1, Ct2 and Ct3 are much smaller. They only provide high

frequency paths for the transformer secondary current and do not provide significant

100-Hz energy storage in the single-phase applications.

vCt2

iS2

E

L2T

Q1 Q2

+ −

R

vO

Cb

Ct3Ct1 Ct2

S1 S3S2

+ −vCb

vCt1−

+

−

+vCt3−

+vQ1−

+vQ2−

+

L1 iS1 iS3is

vp

−

+ipvs

−

+ iO iCb

D1 D2

Figure 7.1 Two-Inductor Boost Converter with a Frequency Changer

7.2.2 Constant Power Output

In order to obtain a constant instantaneous power of the two-phase output, the

capacitor Cb needs to provide the 100-Hz power balance for the resistive load and

the current in the capacitor Cb is controlled. Assume that AO and ACb are

respectively the amplitudes of the voltages of the resistive load R and the capacitor

328

Cb, ωgrid and ωCb are respectively the angular frequencies of the voltages of the

resistive load R and the capacitor Cb and the phase angles of the voltages of the

resistive load R and the capacitor Cb are respectively 0 and θCb, the voltages and the

currents in the two-phase output can be respectively found as:

tAtv gridOO ωsin)( = (7.1)

tRA

Rtv

ti gridOO

O ωsin)(

)( == (7.2)

)sin()( CbCbCbCb tAtv θω += (7.3)

⎟⎠⎞

⎜⎝⎛ ++==

2sin

)()( πθωω CbCbbCbCb

CbbCb tCA

dttdv

Cti (7.4)

Therefore, the instantaneous powers of the resistive load R and the capacitor Cb can

be calculated as:

)2cos1(2

)()()(2

tR

Atitvtp grid

OOOO ω−=⋅= (7.5)

⎟⎠⎞

⎜⎝⎛ ++=⋅=

2322cos

2)()()(

2 πθωω

CbCbbCbCb

CbCbCb tCA

titvtp (7.6)

In Equation (7.5), the average and the ripple resistive load powers can be

respectively found as:

RA

dttpT

P OTt

t Ogrid

avggrid

2)(1 2

0∫=

=== (7.7)

329

tR

APtpp grid

OavgOripple ω2cos

2)(

2

−=−= (7.8)

where grid

gridTω

π2= is the voltage period of the resistive load R.

In order to achieve a constant power output, the following equation can be

established:

0=+ rippleCb pp (7.9)

Substituting Equations (7.6) and (7.8) to (7.9), one particular solution for Equation

(7.9) can be found as:

bCb

OCb CR

AA

ω= (7.10)

gridCb ωω = (7.11)

43πθ −=Cb (7.12)

If the conditions in Equations (7.10) to (7.12) are maintained, the instantaneous

output power as well as the power on the dc input will be a constant. Therefore, an

energy storage element, such as an electrolytic capacitor can be eliminated from the

converter input.

330

For the simplicity of the following discussion, it is assumed that the amplitudes of

the currents of the resistive load R and the capacitor Cb are the same and this gives:

bCbCbO CA

RA

ω= (7.13)


OCb AA = (7.14)

RC

gridb ω

1= (7.15)

Therefore, Equations (7.3) and (7.4) can be simplified as:

⎟⎠⎞

⎜⎝⎛ −=

43sin)( πω tAtv gridOCb (7.16)

⎟⎠⎞

⎜⎝⎛ −=

4sin)( πω t

RA

ti gridO

Cb (7.17)

7.2.3 Open Loop PWM

In the two-inductor boost converter with a frequency changer, PWM can be used to

control the switching actions of the three bi-directional switches S1, S2 and S3 [109].

Therefore, the duty ratios of the individual switches S1, S2 and S3 are proportional to

the low frequency terms of the individual switch currents iS1,LF, iS2,LF and iS3,LF,

331

which can be respectively found as:

)sin()()(,1 tRA

titi gridO

OLFS ω== (7.18)

⎟⎠⎞

⎜⎝⎛ +⎟

⎠⎞

⎜⎝⎛−=−=

83sin

8sin

2)()()(,2

πωπ tRA

tititi gridO

OCbLFS (7.19)

⎟⎠⎞

⎜⎝⎛ −−=−=

4sin)()(,3

πω tRA

titi gridO

CbLFS (7.20)

In the following discussion, the symbol is defined as the symbol of the half

wave rectification and the operation can be expressed as:

⇑⇑

⎩⎨⎧

<≥

⇑=⇑0)(,00)(),(

)(tftftf

tf (7.21)

where is an arbitrary function. )(tf

If DSj+ and DSj− are respectively the duty ratios of the switch Sj when the transformer

secondary current is is positive and negative, where 3,2,1=j and Is is the amplitude

of the transformer secondary current is when only one of the MOSFETs Q1 and Q2 is

on, the duty ratio of each switch can be calculated from Equations (7.18) to (7.20)

as:

⇑⇑⇑=⇑=+ )sin()(1)( ,11 tRI

Ati

ItD grid

s

OLFS

sS ω (7.22)

332

⇑−⇑⇑=−⇑=− )sin()(1)( ,11 tRI

Ati

ItD grid

s

OLFS

sS ω (7.23)

⇑⎟⎠⎞

⎜⎝⎛ +−⇑⎟

⎠⎞

⎜⎝⎛⇑=⇑=+ 8

3sin8

sin2

)(1)( ,22πωπ t

RIA

tiI

tD grids

OLFS

sS (7.24)

⇑⎟⎠⎞

⎜⎝⎛ +⇑⎟

⎠⎞

⎜⎝⎛⇑=−⇑=− 8

3sin8

sin2

)(1)( ,22πωπ t

RIA

tiI

tD grids

OLFS

sS (7.25)

⇑⎟⎠⎞

⎜⎝⎛ −−⇑⇑=⇑=+ 4

sin)(1)( ,33πω t

RIA

tiI

tD grids

OLFS

sS (7.26)

⇑⎟⎠⎞

⎜⎝⎛ −⇑⇑=−⇑=− 4

sin)(1)( ,33πω t

RIA

tiI

tD grids

OLFS

sS (7.27)

It is required that the maximum duty ratio of the switches S1, S2 and S3 be less than

or equal to the ratio of the maximum positive or negative transformer secondary

current period to the converter switching period otherwise the modulation fails.

From Equations (7.22) to (7.27), the maximum switch duty ratio of the switches S1,

S2 and S3 is RI

A

s

O . If the minimum switch duty ratio of the MOSFETs Q1 and Q2 is

Ds,min, it is required that min,1 ss

O DRI

A−≤ and the constraint on the amplitude of the

transformer secondary current is RD

AI

s

Os )1( min,−

≥ .


0)(3

1, =∑

=jLFSj ti (7.28)

333

At any time, there must be at least one positive current term and one negative

current term in Equation (7.28). Therefore the following equation can be

established:

∑∑<>

=0

,0

,,, LFSjLFSj i

LFSji

LFSj ii , 3,2,1=j (7.29)

According to Equations (7.22) to (7.27) and (7.29), the instantaneous switch duty

ratio of the MOSFETs Q1 and Q2 can be calculated as:

∑∑=

−=

+ ===3

1

3

121 )()()()(

jSj

jSjQQ tDtDtDtD (7.30)

In the practical converter operation, the duty ratios of the switches S1, S2 and S3 are

calculated at the beginning of each high frequency switching period and they

maintain fixed for the complete high frequency switching period. If two switches

have non-zero duty ratios within one positive or negative transformer secondary

current period, the switches turn on one after another and in the order of S1, S2 and

S3.

The above discussion can be made clearer with the following example. Considering

a simplified case where %50min, =sD and RA

I Os

2= , the demanded low frequency

switch current waveforms in one low frequency period can be shown in Figure 7.2.

334

0 π/6 π/4 5π/8 π 5π/4 13π/8 2π ωgridt

Is/2

Is/4

-Is/2

-Is/4

iS1,LF, iS2,LF, iS3,LFiS3,LFiS1,LF

iS2,LF

Figure 7.2 Demanded Low Frequency Switch Currents

The duty ratios in Equations (7.22) to (7.27) at a specific time can be found by

inspecting the absolute values of the ordinates of the waveforms in Figure 7.2 and

setting Is to 1. For example, at 6/πω =tgrid , 25.01 =+SD , ,

and the other three duty ratios are zero. Figure 7.3 shows the

switching sequence at

3794.02 =−SD

1294.03 =+SD

6/πω =tgrid within one switching period, Ts. The on

intervals of the individual switches S1, S2 and S3 are respectively illustrated by the

shaded areas.

0 Ts/2 Ts t

S1

S2

S3

isIs

-IsQ2 on

Q1 on

Q2 on

Figure 7.3 Switching Sequence in One Switching Period

335

7.2.4 Closed Loop Transformer Volt-Second Balance Control

In the operation of the high frequency link converter, the transformer volt-second

balance must also be controlled to protect the high frequency transformer from

saturation. The following equations can be established from Figure 7.1:

)()()( 21 tvtvtv OCtCt =− (7.31)

)()()( 32 tvtvtv CbCtCt =− (7.32)

Equations (7.31) and (7.32) confirm that the load voltage vO and the capacitor

voltage vCb impose only two constraints on the three capacitor voltages vCt1, vCt2 and

vCt3. Therefore a degree of freedom remains to allow the control of the average

transformer voltage over a switching period.

In order to protect the high frequency transformer from saturation, the average

transformer primary voltage must be zero within one switching period. The

discussion can be simplified by assuming 1:1 turns ratio for the high frequency

transformer. The instantaneous voltage across the transformer is one of the voltages

across the capacitors Ct1, Ct2 or Ct3 depending on which secondary switch is closed.

The average transformer primary voltage can be calculated as:

avgQavgQavgp vvv ,2,1, −= (7.33)

336

where vQ1,avg and vQ2,avg are respectively the average drain source voltages across the

MOSFETs Q1 and Q2. If DSj+ and DSj− are the duty ratios calculated by Equations

(7.22) to (7.27) at the beginning of each high frequency switching period, where

, v3,2,1=j Q1,avg and vQ2,avg at the same time can be respectively calculated as:

∑=

+=3

1,1

jCtjSjavgQ vDv (7.34)

∑=

−−=3

1,2

jCtjSjavgQ vDv (7.35)


∑=

−+ +=3

1, )(

jCtjSjSjavgp vDDv (7.36)

In Equation (7.36), vp,avg must be zero. The individual switch duty ratios DSj+ must

be decreased and DSj− increased if while D0, >avgpv Sj+ must be increased and DSj−

decreased if , where 0, <avgpv 3,2,1=j . Therefore, the feedback control circuit can

be designed as shown in Figure 7.4, where H(t) is a Proportional-Integral-Derivative

(PID) controller to remove the high frequency component in the transformer primary

voltage and provide the control on the system stability.

In the converter with only the open loop PWM control, the constraint on the

amplitude of the transformer secondary current ensures that the sums of the

337

secondary switch duty ratios are less than or equal to min,1 sD− at any time.

However, with the closed loop transformer volt-second balance control, there are

chances that the sums of the secondary switch duty ratios are greater than .

In this case, the individual duty ratios must be recalculated so that the available

transformer secondary current positive or negative pulse is allocated to each switch

proportionally to the demanded duty ratios calculated through the closed loop

control.

min,1 sD−

+0 H(t) Duty RatioCalculator

vp

iS1,LF iS2,LF iS3,LF

DS1+

DQ2

DS3−

DS3+

DS2−

DS2+

DS1−

DQ1

Figure 7.4 Feedback Control Circuit

7.2.5 Simulation Results

The simulation based on the ideal circuit model in Figure 7.5 is performed with

SIMULINK. The two input inductors are modelled by the ideal current sources.

The transformer is modelled by the dependent sources. All of the primary and

secondary switches are modelled by the ideal switches. The important parameters

used in the simulation are:

338

• The transformer turns ratio 1:1: =sp NN ,

• The current source AI 25.10 = ,

• The switching frequency kHzf s 10= ,

• The output voltage amplitude VAO 340= ,

• The output voltage angular frequency sradgrid 314=ω ,

• The load resistance Ω= 576R ,

• The power balancing capacitor FCb µ53.5= ,

• The high frequency capacitors FCCC ttt µ5.0321 === , and

• The minimum duty ratio of the MOSFETs Q1 and Q2 . 52.0min, =sD

is

vCt2

iS2

Q1 Q2

+ −

R

vO

Cb

Ct3Ct1 Ct2

S1 S3S2

+ −vCb

vCt1−

+

−

+vCt3−

+vQ1−

+vQ2−

+

I0 iS1 iS3

isvp −+

vp

−

+ iO iCb

I0

Figure 7.5 Simulation Circuit Model

Figure 7.6 shows the simulation waveforms of the resistive load voltage vO and the

capacitive load voltage vCb. It can be clearly seen that the capacitor voltage is of the

same amplitude as the resistive load voltage but is displaced by 4

3π .

339

Figure 7.7 shows the voltage waveforms across the three capacitors Ct1, Ct2 and Ct3.

These voltages are not sinusoidal but are adjusted by the closed loop control to

provide volt-second balance for the high frequency transformer. The three capacitor

voltages show a significant amount of high switching frequency ripples. These

capacitors are purposefully kept small to allow for rapid adjustments. The capacitor

voltages with the corresponding switch closures decide the instantaneous voltage

across the transformer secondary. Figure 7.7 validates that the peak transformer

secondary voltage happens when S2 closes and this is less than the amplitude of the

load voltage.

Figure 7.8 shows two cycles of the secondary switch currents to allow a close

examination of the PWM control scheme used in this converter. It can be observed

that at this particular time, the duty ratios DS1+ is increasing, DS2− is increasing and

DS3+ is decreasing. This means that the demanded current in the switch S1 is

positive and the magnitude is increasing, the demanded current in the switch S2 is

negative and the magnitude is increasing, the demanded current in the switch S3 is

positive and the magnitude is decreasing. According to Figure 7.2, this time should

fall into the interval of ⎥⎦⎤

⎢⎣⎡

8,0 π in a low frequency cycle. A spike can be seen at the

beginning of the switch S1 current pulse and this is due to the overlap of the closings

of the primary MOSFETs. It is also worth noting that DS2− varies slightly from the

sum of DS1+ and DS3+ due to the feedback transformer volt-second balance control.

Figure 7.9 shows the voltages across the primary MOSFETs and the transformer

340

primary during the same two high frequency cycles shown in Figure 7.8. At this

particular time, Ct1 and Ct3 have positive charging currents as iS1 and iS3 are positive

while Ct2 has a negative charging current as iS2 is negative. The power flow is

negative in Ct1 and positive in Ct2 and Ct3. For the switch S1 closures, the power is

returned to the primary side of the converter and temporarily stored in the inductor

L1. The power flow reversal is required for 100-Hz power balance and will need the

reverse blocking requirements for the primary MOSFETs Q1 and Q2. It is also worth

mentioning that the power flow reversal causes extra energy flow in the transformer.

0 5 10 15 20 25 30 35 40-400

-300

-200

-100

0

100

200

300

400

Cap

aciti

ve L

oad

Vol

tage

v Cb

(V)

t (ms)

0 5 10 15 20 25 30 35 40-400

-300

-200

-100

0

100

200

300

400

Res

istiv

e Lo

ad V

olta

gev O

(V)

t (ms)

Figure 7.6 Simulation Waveforms of the Two-Phase Output Voltages

341

0 5 10 15 20 25 30 35 40-400

-300

-200

-100

0

100

200

300

400

0 5 10 15 20 25 30 35 40-400

-300

-200

-100

0

100

200

300

400

0 5 10 15 20 25 30 35 40-400

-300

-200

-100

0

100

200

300

400

Cap

acito

r Vol

tage

v Ct3

(V)

t (ms)

Cap

acito

r Vol

tage

v Ct2

(V)

t (ms)

Cap

acito

r Vol

tage

v Ct1

(V)

t (ms)

Figure 7.7 Simulation Waveforms of the High Frequency Capacitor Voltages

342

0 20 40 60 80 100 120 140 160 180 200-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

0 20 40 60 80 100 120 140 160 180 200-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

0 20 40 60 80 100 120 140 160 180 200-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

Switc

h C

urre

nti S

3(A

)

t (µs)

Switc

h C

urre

nti S

2(A

)

t (µs)

Switc

h C

urre

nti S

1(A

)

t (µs)

Figure 7.8 Simulation Waveforms of the Secondary Switch Currents

343

0 20 40 60 80 100 120 140 160 180 200-200

-150

-100

-50

0

50

100

150

200

0 20 40 60 80 100 120 140 160 180 200-200

-150

-100

-50

0

50

100

150

200

0 20 40 60 80 100 120 140 160 180 200-200

-150

-100

-50

0

50

100

150

200

Tran

sfor

mer

Prim

ary

Vol

tage

v p(V

)

t (µs)

MO

SFET

Vol

tage

v Q2

(V)

t (µs)

MO

SFET

Vol

tage

v Q1

(V)

t (µs)

Figure 7.9 Simulation Waveforms of the MOSFET and Transformer Primary

Voltages

344

7.3 Summary

In this chapter, the MIC implementation based on the two-inductor boost converter

with a frequency changer is discussed. The proposed converter is a two-stage

converter and is capable of transforming the high frequency ac voltage directly to

the low frequency ac voltage without the rectification stage. A significant advantage

of this converter is the constant power output provided by the additional power

balancing capacitor. Both the open loop PWM and the closed loop transformer volt-

second balance controls are explicitly demonstrated. The simulation results are also

provided to verify the theoretical analysis. As the negative voltage appears in the

drain source voltage waveforms of the primary MOSFETs, a diode is required to be

in series with the MOSFET in the practical implementation of the converter. The

converter will have implementation challenges that might become easier over time

particularly with a recent research upswing internationally in matrix converter

technology. The ac-ac converter challenges raised in motor drives are similar.

345

8. CONCLUSIONS

This thesis concentrated on the development of the converter topologies based on

the two-inductor boost converter for MIC applications. It has presented a broad

range of new contributions to our understanding of the two-inductor boost converter

and builds significantly upon the author’s earlier Master of Engineering study.

Chapter 2 classified the MIC implementations with high frequency transformers into

three topologies and provided a review of the existing literature on the individual

topologies. Amongst the three possible MIC topologies, the MIC implementations

with an unfolding stage have drawn significant interest and the reasons are:

• Two separate dc-dc and dc-ac conversion stages make the design and the

control relatively simple.

• The dc-ac conversion stage operates at low frequency and this avoids the

high switching losses.

Chapter 3 discussed the power balance issue in the MIC design. In order to deal

with the 100-Hz power ripple in MIC implementations, capacitive energy storage is

most frequently used and it can be located at the converter input, dc link or output as

a second phase associated with the load. Then a review of the recent literature on

the two-inductor boost converter was presented. Also, different arrangements of the

two-inductor boost converter including the two-inductor boost converters with a

346

PWM inverter, an unfolder and a frequency changer were respectively demonstrated

for the individual MIC topologies.

Chapter 4 presented a detailed analysis of the ZVS two-inductor boost converter.

Under variable frequency control, the ZVS two-inductor boost converter is able to

achieve a maximum to minimum output voltage ratio of 2.3 by varying the three

circuit parameters including the load factor, the timing factor and the delay angle

while maintaining the resonant condition. The ZVS two-inductor boost converter

with the voltage clamp was also analysed in detail and a larger maximum to

minimum output voltage ratio of 5.3 could be obtained in this converter without

excessive switch voltage stresses. Both of the design equations and the control

functions were established for the two resonant two-inductor boost converters.

If the ZVS two-inductor boost converter is required to operate under a fixed load

condition, different operating conditions exist, which require different combinations

of the three circuit parameters as mentioned above and the three key converter

design parameters including the resonant inductance and capacitance and the

transformer turns ratio. It has been shown that the power losses in the MOSFETs,

the resonant inductor and capacitors vary under different operating conditions.

These power loss terms as well as the total variable power loss can be drawn as

surfaces using the numerical analysis in MATLAB and the operating point with the

minimised total power loss can be easily identified.

347

Chapter 5 provided a detailed analysis of the magnetic integration solutions in the

two-inductor boost converter, which aim to integrate the three separate magnetic

components and achieve an overall compact design. This chapter systematically

developed four integrated magnetic structures using both of the magnetic core

integration and the winding integration methods. A detailed analysis of the


flux densities and the current ripples in the individual windings of the hard-switched

two-inductor boost converter with four integrated magnetic structures was also

provided. It has been shown that among the four integrated magnetic structures,

Structure A has the lowest transformer leakage inductance, Structure B has the

lowest number of copper winding components and Structures C and D have the

lowest ac flux densities in the centre core leg therefore the lowest core loss.

The ZVS two-inductor boost converter with Structure B magnetic integration was

also analysed in detail. In this converter, the four magnetic cores and the five copper

windings required by the two input inductors, the resonant inductor and the

transformer are integrated into one magnetic core with three copper windings. With

the magnetic integration technique, the component count is significantly reduced and

this results in a more compact converter design with possible higher efficiency.

Finally, a 40-W prototype converter has been developed and achieved 93%

efficiency.

Chapter 6 developed the hard-switched and the soft-switched current fed two-

inductor boost converters. These two converters are both three-stage converters

348

including the buck, the boost and the inversion stages. In the buck stage, a two-

phase synchronous buck converter is modulated to produce a rectified sinusoidal

current and interfaced with the two-inductor boost cell through an IPT. As the boost

stage converter produces a fixed dc gain, the rectified sinusoidal voltage is generated

at the output and this reduces the following inverter to an unfolder with simple

square-wave control.

In the hard-switched current fed two-inductor boost converter, non-dissipative

snubbers are employed to control the switch voltage stress and recover part of the

energy trapped in the snubber circuit back to the supply. The four operation modes

in the snubber circuit under different buck stage MOSFET duty ratios were

thoroughly studied. Structure A magnetic integration, which has been discussed in

Chapter 5 and the silicon carbide rectifiers, which have high reverse breakdown

voltage ratings and the near zero reverse recovery time are also used in the two-

inductor boost cell to minimise the converter size and power loss.

In the soft-switched current fed two-inductor boost converter, a resonant transition

gate drive circuit is developed for the two MOSFETs in the boost cell to reduce the

drive power loss, which will otherwise become significant under high switching

frequency operation if a conventional gate drive circuit is used. The two-inductor

boost cell is also designed to operate at the optimised operating point with the

minimised total variable power loss as discussed in Chapter 4.

349

In the unfolder for both converters, the electrically isolated optical MOSFET drivers

are used to achieve a simple control circuit design. The hard-switched and the soft-

switched current fed two-inductor boost converters have respectively achieved 92%

and 91% efficiency.

Chapter 7 presented the two-inductor boost converter with a frequency changer. In

this two-stage converter, no dc link exists in the power conversion process. The

rectification stage of the two-inductor boost converter is replaced by a frequency

changer, which converts the high frequency ac current directly to the ac voltage of

the grid frequency. Compared with the MIC implementations with the constant or

the variable dc link, this topology is simpler and has a potential for size reduction.

A small non-polarised capacitor is also employed in the converter in combination

with the resistive load to achieve the constant power output and the large electrolytic

capacitor, which is normally used to deal with the 100-Hz power ripple, can be

avoided. It has been shown that in the practical implementation of this converter, a

diode is required to be in series with the low-voltage primary side MOSFET to

provide the reverse voltage blocking. The practical implementation of the hard-

switched converter and the development of the soft-switched converter are both

areas of future research.

Another future research area is the implementation of the digital control for the

converter topologies presented in this thesis, which is expected to result in the

reductions of the overall converter size and control power loss. It is also clear that

the resonant converter understandings developed in this thesis can be readily

350

extended to the hard-switched variations of the two-inductor boost converters that

have been recently proposed by other researchers. This is a promising avenue for

future research.

351

REFERENCES

[1] P. D. Maycock, “World PV Cell/Module Production,” PV News, Vol. 24, No.

2, Feb. 2005.

[2] International Energy Agency. (2005 Sept.). Trends in Photovoltaic

Applications: Survey Report of Selected IEA Countries between 1992 and

2004. [Online]. Available: http://www.iea-pvps.org/products/download/

rep1_14.pdf

[3] Q. Li, “Development of High Frequency Power Conversion Technologies for

Grid Interactive PV Systems,” Master of Engineering Dissertation, Central

Queensland University, Australia, 2002.

[4] European Renewable Energy Council. (2004, May). Renewable Energy

Scenario to 2040. [Online]. Available: http://www.erec-renewables.org/

documents/targets_2040/EREC_Scenario%202040.pdf

[5] W. El-Khattam and M. M. A. Salama, “Distributed Generation Technologies,

Definitions and Benefits,” Electric Power Systems Research, Vol. 71, No. 2,

pp. 119-128, Oct. 2004.

[6] D. M. Chapin, C. S. Fuller, G. L. Pearson, "Solar Energy Converting

Apparatus," U.S. Patent 2 780 765, 5 Feb. 1957.

[7] H. Yoon, J. E. Granata, P. Hebert, R. R. King, C. M. Fetzer, P. C. Colter, K. M.

Edmondson, D. Law, G. S. Kinsey, D. D. Krut, J. H. Ermer, M. S. Gillanders

and N. H. Karam, “Recent Advances in High-Efficiency III-V Multi-Junction

Solar Cells for Space Applications: Ultra Triple Junction Qualification,”

352

Progress in Photovoltaics: Research and Applications, Vol. 13, No. 2, pp. 133-

139, Feb. 2005.

[8] O. Schultz, S. W. Glunz, J. C. Goldschmidt, H. Lautenschlager, A.

Leimenstoll, E. Schneiderlöchner, G. P. Willeke, “Thermal Oxidation

Processes for High-Efficiency Multicrystalline Silicon Solar Cells,” in Proc.

European Photovoltaic Solar Energy Conference, 2004.

[9] O. Schultz, S. W. Glunz, G. P. Willeke, “Multicrystalline Silicon Solar Cells

Exceeding 20% Efficiency,” Progress in Photovoltaics: Research and

Applications, Vol. 12, No. 7, pp. 553-558, Nov. 2004.

[10] P. D. Maycock, “World PV Cell/Module Production,” PV News, Vol. 25, No.

3, Mar. 2006.

[11] M. Shahidehpour and F. Schwarts, “Don't Let the Sun Go down on PV,” IEEE

Power Energy Mag., Vol. 2, No. 3, pp. 40-48, May/Jun. 2004.

[12] S. Karaki, D. S. Ward and G. O. G. Lof, “Utilization of Solar Energy Today,”

in Proc. IEEE Power Engineering Society Summer Meeting and Energy

Resources Conference, 1974.

[13] W. Kleinkauf, J. Sachau and H. Hempel, “Developments in Inverters for

Photovoltaic Systems – Modular Power Conditioning and Plant Technology,”

in Proc. European Community Photovoltaic Solar Energy Conference, 1992,

pp. 1029-1033.

[14] M. Meinhardt and G. Cramer, “Past, Present and Future of Grid Connected

Photovoltaic- and Hybrid-Power-Systems,” in Proc. IEEE Power Engineering

Society Summer Meeting, 2000, pp. 1283-1288.

353

[15] M. Calais, J. Myrzik, T. Spooner and V. G. Agelidis, “Inverters for Single-

Phase Grid Connected Photovoltaic Systems – an Overview,” in Proc. IEEE

Power Electronics Specialists Conference, 2002, pp. 1995-2000.

[16] G. Cramer, M. Ibrahim and W. Kleinkauf, “PV System Technologies: State-of-

the-Art and Trends in Decentralised Electrification,” Refocus, pp. 38-42,

Jan./Feb. 2004.

[17] F. Blaabjerg, Z. Chen and S. B. Kjær, “Power Electronics as Efficient Interface

in Dispersed Power Generation Systems,” IEEE Trans. Power Electron., Vol.

19, No.5, pp. 1184-1194, Sept. 2004.

[18] J. M. A. Myrzik and M. Calais, “String and Module Integrated Inverters for

Single-Phase Grid Connected Photovoltaic Systems – a Review,” in Proc.

IEEE Bologna Power Tech Conference, 2003, pp. 1-8.

[19] L. E. de Graaf and T. C. J. van der Weiden, “Characteristics and Performance

of a PV-System Consisting of 20 AC-Modules,” in Proc. IEEE World

Conference on Photovoltaic Energy Conversion, 1994, pp. 921-924.

[20] H. Oldenkamp and I. J. de Jong, “AC Modules: Past, Present and Future,”

Workshop Installing the Solar Solution, Hatfield, UK, 1998.

[21] R. H. Wills, S. Krauthamer, A. Bulawka and J. P. Posbic, "The AC

Photovoltaic Module Concept," in Proc. Intersociety Energy Conversion

Engineering Conference, 1997, pp. 1562-1563.

[22] B. Verhoeven. (1998, Dec.). Utility Aspects of Grid Connected Photovoltaic

Power Systems. International Energy Agency. [Online]. Available:

http://www.oja-services.nl/iea-pvps/products/download/rep50_01.pdf

354

[23] G. Keller, T. Krieger, M. Viotto and U. Krengel, “Module Orientated

Photovoltaic Inverters – a Comparison of Different Circuits,” in Proc. IEEE

World Conference on Photovoltaic Energy Conversion, 1994, pp. 929-932.

[24] S. W. H. de Haan, H. Oldenkamp, C. F. A. Frumau and W. Bonin,

“Development of a 100 W Resonant Inverter for AC-Modules,” Proc.

European Photovoltaic Solar Energy Conference, 1994, pp. 395-398.

[25] S. B. Kjær, J. K. Pedersen and F. Blaabjerg, “Power Inverter Topologies for

Photovoltaic Modules – a Review,” in Proc. IEEE Industry Applications

Conference, 2002, pp. 782-788.

[26] D. M. Roche, “Economic Comparison of Central versus Module Inverters in

Residential Rooftop Photovoltaic Systems,” in Proc. Solar Harvest

Conference, Annual Australian New Zealand Solar Energy Society Conference,

2002.

[27] R. H. Wills, F. E. Hall, S. J. Strong and Wohlgemuth, "The AC Photovoltaic

Module," in Proc. IEEE Photovoltaic Specialist Conference, 1996, pp. 1231-

1234.

[28] S. J. Strong, "World Overview of Building-Integrated Photovoltaics," in Proc.

IEEE Photovoltaic Specialist Conference, 1996, pp. 1197-1202.

[29] S. J. Strong, “Power Windows, Building-Integrated Photovoltaics,” IEEE

Spectr., Vol. 33, No. 10, pp. 49-55, Oct. 1996.

[30] S. J. Strong, “A New Generation of Solar Electric Architecture,” in Proc.

World Solar Electric Buildings Conference, 2000.

355

[31] H. Oldenkamp and I. de Jong, “Next Generation of AC Module Inverters,” in

Proc. World Conference and Exhibition on Photovoltaic Solar Energy

Conversion, 1998, pp. 2078-2081.

[32] T. G. Wilson, “The Evolution of Power Electronics,” IEEE Trans. Power

Electron., Vol. 15, No. 3, pp. 439-446, May 2000; also in Proc. IEEE

International Symposium on Industrial Electronics, 1992, pp. 1-9; also in Proc.

IEEE Applied Power Electronics Conference and Exposition, 1999, pp. 3-9.

[33] P. Cheasty, J. Flannery, M. Meinhardt, A. Alderman and S. C. O'Mathuna,

“Benchmark of Power Packaging for DC/DC and AC/DC Converters,” IEEE

Trans. Power Electron., Vol. 17, No. 1, pp. 141-150, Jan. 2002.

[34] M. Meinhardt, T. O’Donnell, H. Schneider, J. Flannery, C. Ó Mathuna, P.

Zacharias and T. Krieger, “Miniaturised Low Profile Module Integrated

Converter for Photovoltaic Applications with Integrated Magnetic

Components,” in Proc. IEEE Applied Power Electronics Conference and

Exposition, 1999, pp. 305-311.

[35] M. Meinhardt, M. Hofmann, S. C. O’Mathuna, “Reliability of Module

Integrated Converters for Photovoltaic Applications,” in Proc. International

Conference on Power Conversion & Intelligent Motion, 1998, pp. 589-598.

[36] J. Myrzik, M. Meinhardt, B. de Mey, J. Flannery, C. F. A. Frumau, H.

Hofkens, M. Jantsch, Th. Kreiger, H. Schneider, G. Vanwiijnsberghe and P.

Zacharias, “HICAAP – Highly Integrateable Converters for Advanced AC-

Photovoltaics – Study of Topologies, Principle Design,” in Proc. World

Conference and Exhibition on Photovoltaic Solar Energy Conversion, 1998,

pp. 2146-2149.

356

[37] B. Lindgren, “Topology for Decentralised Solar Energy Inverters with a Low

Voltage AC-Bus,” in Proc. European Conference on Power Electronics and

Applications, 1999.

[38] H. Oldenkamp, I. J. de Jong, C. W. A. Baltus and S. A. M. Verhoeven,

“Advanced High Frequency Switching Technology of OK4 AC Module

Inverters Break the 1 US$/Watt Price Barrier,” in Proc. Photovoltaic Solar

Energy Conference, 1997.

[39] H. Laukamp, T. Schoen and D. Ruoss. (2002 Mar.). Reliability Study of Grid

Connected PV Systems – Field Experience and Recommended Design

Practice. International Energy Agency. [Online]. Available: http://www.oja-

services.nl/iea-pvps/products/download/rep7_08.pdf

[40] P. J. M. Heskes, P. M. Rooij, S. Islam, A. Woyte and J. Wouters,

“Development, Production and Verification of the Second Generation of AC-

Modules (PV2GO),” in Proc. European PV Solar Energy Conference and

Exhibition, 2004.

[41] R. H. Bonn, “Inverter for the 21st Century,” in Proc. National Center

Photovoltaics Program Review Meeting, Oct. 2001.

[42] H. Oldenkamp, I. J. de Jong, C. W. A. Baltus, S. A. M. Verhoeven and S.

Elstgeest, “Reliability and Accelerated Life Tests of the AC Module Mounted

OKE4 Inverter,” in Proc. IEEE Photovoltaic Specialists Conference, 1996, pp.

1339-1342.

[43] S. B. Kjær. (2002 Feb.). Specifications for the ‘Solcelleinverter’ Project.

Aalborg University. [Online]. Available: http://www.iet.auc.dk/~sbk/solar/

papers/SPEC.pdf

357

[44] R. H. Bonn, “Developing a ‘Next Generation’ PV Inverter,” in Proc. IEEE

Photovoltaic Specialists Conference, 2002, pp.1352-1355.

[45] International Energy Agency. (2002 Apr.) Glossary. [Online]. Available:

http://www.iea-pvps.org/pv/glossary.htm

[46] P. Fairley, “BP Solar Ditches Thin-Film Photovoltaics – A Big Setback to

Industry’s Vision,” IEEE Spectr., Vol. 40, No. 1, pp. 18-19, Jan. 2003.

[47] H. Oldenkamp, S. W. H. de Haan, I. J. de Jong and C. W. A. Baltus,

“Competitive Implementation of Multi-Kilowatts Grid Connected PV-Systems

with OKE4 AC Modules,” in Proc. European Photovoltaic Solar Energy


[48] S. B. Kjær, (2002 Feb.). State of the Art Analysis for the ‘Solcelleinverter’

Project. Aalborg University. [Online]. Available: http://www.iet.auc.dk/~sbk/

solar/papers/SOTA.pdf

[49] J. Schmid, F. Raptis and P. Zacharias, “PV Hybrid Plants – State of the Art and

Future Trends,” in Proc. European PV and Hybrid Power Systems Conference,

2000.

[50] B. K. Bose, “Energy, Environment, and Advances in Power Electronics,” IEEE

Trans. Power Electron., Vol. 15, No. 4, pp. 688-701, Jul. 2000; also in Proc.

IEEE International Symposium on Industrial Electronics, 2000, pp. TU1-14.

[51] M. Andersen and B. Alvsten, “200 W Low Cost Module Integrated Utility

Interface for Modular Photovoltaic Energy Systems,” in Proc. IEEE

International Conference on Industrial Electronics, Control, and

Instrumentation, 1995, pp. 572-577.

358

[52] A. Lohner, T. Meyer and A. Nagel, “A New Panel-Integratable Inverter

Concept for Grid-Connected Photovoltaic Systems,” in Proc. IEEE

International Symposium on Industrial Electronics, 1996, pp. 827-831.

[53] E. T. Calkin and B. H. Hamilton, “Circuit Techniques for Improving the

Switching Loci of Transistor Switches in Switching Regulators,” IEEE Trans.

Ind. Applicat., Vol. IA-12, No. 4, pp. 364-369, Jul./Aug. 1976.

[54] N. Mohan, T. M. Undeland and W. P. Robbins, Power Electronics, Converters,

Applications, and Design, New York: John Wiley & Sons, Inc., 1995.

[55] K. M. Smith, Jr. and K. M. Smedley, “Properties and Synthesis of Passive

Lossless Soft-Switching PWM Converters,” IEEE Trans. Power Electron.,

Vol. 14, No. 5, pp. 890-899, Sept. 1999.

[56] T. Zeng, D. Y. Chen and F. C. Lee, “Variations of Quasi-Resonant DC-DC

Converter Topologies,” in Proc. IEEE Power Electronics Specialists


[57] A. K. S. Bhat and S. D. Dewan, "Resonant Inverters for Photovoltaic Array to

Utility Interface," in Proc. IEEE International Telecommunications and Energy

Conference, 1986, pp. 135-142; also IEEE Trans. Aerosp. Electron. Syst., Vol.

24, No. 4, pp. 377-386, Jul. 1988.

[58] G. Hua and F. C. Lee, “Soft-Switching Techniques in PWM Converters,” IEEE

Trans. Ind. Electron., Vol. 42, No.6, pp. 595-603, Dec. 1995.

[59] G. Hua, C. Leu, Y. Jiang and F. C. Lee, “Novel Zero-Voltage-Transition PWM

Converters,” in Proc. IEEE Power Electronics Specialists Conference, 1992,

pp. 55-61; also IEEE Trans. Power Electron., Vol. 9, No. 2, pp. 213-219, Mar.

1994.

359

[60] C. Tseng and C. Chen, “Novel ZVT-PWM Converters with Active Snubbers,”

IEEE Trans. Power Electron., Vol. 13, No. 5, pp. 861-869, Sept. 1998.

[61] H. Bodur and A. F. Bakan, “A New ZVT-PWM DC-DC Converter,” IEEE

Trans. Power Electron., Vol. 17, No. 1, pp. 40-47, Jan. 2002.

[62] T. J. Liang, Y. C. Kuo and J. F. Chen, "Single-Stage Photovoltaic Energy

Conversion System," IEE Proc. Electric Power Applications, Vol. 148, No. 4,

pp. 339-344, Jul. 2001.

[63] U. Herrmann, H. G. Langer and H. van der Broeck, “Low Cost DC to AC

Converter for Photovoltaic Power Conversion in Residential Applications,” in

Proc. IEEE Power Electronics Specialists Conference, 1993, pp. 588-594.

[64] D. C. Martins, R. Demonti, “Interconnection of a Photovoltaic Panels Array to

a Single-Phase Utility Line from a Static Conversion System,” in Proc. IEEE

Power Electronics Specialists Conference, 2000, pp. 1207-1211.

[65] C. Prapanavarat, M. Barnes and N. Jenkins, “Investigation of the Performance

of a Photovoltaic AC Module,” IEE Proc. Generation, Transmission and

Distribution, Vol. 149, No. 4, pp. 472-478, Jul. 2002.

[66] T. Shimizu, K. Wada and N. Nakamura, “A Flyback-Type Single Phase Utility

Interactive Inverter with Low-Frequency Ripple Current Reduction on the DC

Input for an AC Photovoltaic Module System,” in Proc. IEEE Power

Electronics Specialists Conference, 2002, pp. 1483-1488.

[67] S. B. Kjær and F. Blaabjerg, “Design Optimization of a Single Phase Inverter

for Photovoltaic Applications,” in Proc. IEEE Power Electronics Specialists

Conference, 2003, pp. 1183-1190.

360

[68] N. Kasa, T. Iida and A. K. S. Bhat, “Zero-Voltage Transition Flyback Inverter

for Small Scale Photovoltaic Power System,” in Proc. IEEE Power Electronics

Specialists Conference, 2005, pp. 2098-2103.

[69] B. K. Bose, P. M. Szczesny, and R. L. Steigerwald, “Microcomputer Control of

a Residential Power Conditioning System,” IEEE Trans. Ind. Applicat., Vol.

IA-21, No. 5, pp. 1182-1191, Sept./Oct. 1985.

[70] S. Saha and V. P. Sundarsingh, “Novel Grid-Connected Photovoltaic Inverter,”

IEE Proc. Generation, Transmission and Distribution, Vol. 143, No. 2, pp.

219-224, Mar. 1996.

[71] V. Vlatkovic, “Alternative Energy: State of the Art and Implications on Power

Electronics,” in Proc. IEEE Applied Power Electronics Conference and


[72] S. Saha, N. Matsui and V. P. Sundarsingh, “Design of a Low Power Utility

Interactive Photovoltaic Inverter,” in Proc. International Conference on Power

Electronic Drives and Energy Systems for Industrial Growth, 1998, pp. 481-

487.

[73] F. Kang, C. Kim, S. Park and H. Park, “Interface Circuit for Photovoltaic

System Based on Buck-Boost Current-Source PWM Inverter,” in Proc. IEEE

International Conference on Industrial Electronics, Control, and


[74] K. Chomsuwan, P. Prisuwanna and V. Monyakul, “Photovoltaic Grid-

Connected Inverter Using Two-Switch Buck-Boost Converter,” in Proc. IEEE

Photovoltaic Specialists Conference, 2002, pp. 1527-1530.

361

[75] S. Funabiki, T. Tanaka and T. Nishi, “A New Buck-Boost-Operation-Based

Sinusoidal Inverter Circuit,” in Proc. IEEE Power Electronics Specialists

Conference, 2002, pp. 1624-1629.

[76] M. Nagao and K. Harada, “Power Flow of Photovoltaic System Using Buck-

Boost PWM Power Inverter,” in Proc. International Conference on Power

Electronics and Drive Systems, 1997, pp. 144-149.

[77] M. Kusakawa, H. Nagayoshi, K. Kamisako and K. Kurokawa, “A New Type of

Module Integrated Converter with Wide Voltage Matching Ability,” in Proc.

World Conference on Photovoltaic Solar Energy Conversion, 1998.

[78] M. Kusakawa, H. Nagayoshi, K. Kamisako and K. Kurokawa, “Further

Improvement of a Transformerless, Voltage-Boosting Inverter for AC

Modules,” Solar Energy Material and Solar Cells, Vol. 67, pp. 379-387, Mar.

2001.

[79] N. Kasa, T. Iida, and H. Iwamoto, “An Inverter Using Buck-Boost Type

Chopper Circuits for Popular Small-Scale Photovoltaic Power System,” in

Proc. Annual Conference of IEEE Industrial Electronics Society, 1999, pp.

185-190.

[80] N. Kasa, H. Ogawa, T. Iida and H. Iwamoto, “A Transformer-less Inverter

Using Buck-Boost Type Chopper Circuit for Photovoltaic Power System,” in

Proc. International Conference on Power Electronics and Drive Systems,

1999, pp. 653-658.

[81] J. Myrzik, “Static Converter Unit for Photovoltaic or Single-Phase

Applications,” German Patent DE 19603823A1, 14 Aug. 1996.

362

[82] J. M. A. Myrzik, “Power Conditioning of Low-Voltage Generators with

Transformerless Grid Connected Inverter Topologies,” in Proc. European

Conference on Power Electronics and Applications, 1997, pp. 2.625-2.630.

[83] J. Myrzik, P. Zacharias, “New Inverter Technology and Harmonic Distortion

Problems in Modular PV Systems,” in Proc. European Photovoltaic Solar

Energy Conference, 1997, pp. 2207-2210.

[84] J. M. A. Myrzik, “Novel Inverter Topologies for Single-Phase Stand-Alone or

Grid-Connected Photovoltaic Systems,” in Proc. International Conference on

Power Electronics and Drive Systems, 2001, pp. 103-108.

[85] D. Schekulin, “Transformerless AC Inverter Circuit,” German Patent

DE19732218C1, 18 Mar. 1999.

[86] S. B. Kjær and F. Blaabjerg, “A Novel Single-Stage Inverter for the AC-

Module with Reduced Low-Frequency Ripple Penetration,” in Proc. European

Conference on Power Electronics and Applications, 2003, pp. 1-10.

[87] R. O. Cáceres and I. Barbi, “A Boost DC-AC Converter: Analysis, Design, and

Experimentation,” in Proc. IEEE International Conference on Industrial

Electronics, Control, and Instrumentation, 1995, pp.546-551; also IEEE Trans.

Power Electron., Vol. 14, No. 1, pp. 134-141, Jan. 1999.

[88] N. Vázquez, J. Almazan, J. Álvarez, C. Aguilar, and J. Arau, “Analysis and

Experimental Study of the Buck, Boost and Buck-Boost Inverters,” in Proc.

IEEE Power Electronics Specialists Conference, 1999, pp. 801-806.

[89] C. Wang, “A Novel Single-Stage Full-Bridge Buck-Boost Inverter,” in Proc.

IEEE Applied Power Electronics Conference and Exposition, 2003, pp. 51-57;

also IEEE Trans. Power Electron., Vol. 19, No. 1, pp. 150-159, Jan. 2004.

363

[90] Y. Xue, L. Chang and P. Song, “Recent Developments in Topologies of Single-

Phase Buck-Boost Inverters for Small Distributed Power Generators: an

Overview,” in Proc. International Power Electronics and Motion Control

Conference, 2004, pp. 1118-1123.

[91] Y. Xue, L. Chang. S. B. Kjær; J. Bordonau and T. Shimizu, “Topologies of

Single-Phase Inverters for Small Distributed Power Generators: an Overview,”

IEEE Trans. Power Electron., Vol. 19, No. 5, pp. 1305-1314, Sept. 2004.

[92] D. Maksimovic and S. Cuk, “Constant-Frequency Control of Quasi-Resonant

Converters,” IEEE Trans. Power Electron., Vol. 6, No. 1, pp. 141-150, Jan.

1991.

[93] L. Yang, D. Z. Long and C. Q. Lee, “From Variable to Constant Switching

Frequency Topologies: A General Approach,” in Proc. IEEE Power


[94] W. Gu and K. A. Harada, “A New Method to Regulate Resonant Converters,”

IEEE Trans. Power Electron., Vol. 3, No. 4, pp. 430-439, Oct. 1988.

[95] P. K. Sood and T. A. Lipo, “Power Conversion Distribution System Using a

Resonant High Frequency AC Link,” in Proc. IEEE Industry Applications


[96] P. K. Sood and T. A. Lipo, “Power Conversion Distribution System Using a

High Frequency AC Link,” IEEE Trans. Ind. Applicat., Vol. 24, No. 2, pp.

288-300, Mar./Apr. 1988.

[97] G. Hua and F. C. Lee, "An Overview of Soft Switching Techniques for PWM

Converters," European Power Electronics and Drives Journal, Vol. 3, No. 1,

364

pp. 39-50, Mar. 1993; also in Proc. International Power Electronics and

Motion Control Conference, 1994.

[98] C. P. Henze, H. C. Martin and D. W. Parsley, “Zero-Voltage Switching in High

Frequency Power Converters Using Pulse Width Modulation,” in Proc. IEEE

Applied Power Electronics Conference and Exposition, 1988, pp. 33-40.

[99] G. Hua and F. C. Lee, “A New Class of Zero-Voltage-Switched PWM

Converters,” in Proc. International High Frequency Power Conversion


[100] S. Bhowmik and R. Spee, “A Guide to the Application-Oriented Selection of

AC/AC Converter Topologies,” in Proc. IEEE Applied Power Electronics

Conference and Exposition, 1992, pp. 571-578; also IEEE Trans. Power

Electron., Vol. 8, No. 2, pp. 156-163, Apr. 1993.

[101] B. R. Pelly, Thyristor Phase-Controlled Converters and Cycloconverters.

New York: John Wiley & Sons, 1971.

[102] L. Gyugyi and B. R. Pelly, Static Power Frequency Changers. New York:

John Wiley & Sons, 1976.

[103] P. W. Wheeler, J. Rodriguez, J. C. Clare, L. Empringham and A. Weinstein,

“Matrix Converters: a Technology Review,” IEEE Trans. Ind. Electron., Vol.

49, No. 2, pp. 276-288, Apr. 2002.

[104] S. Yatsuki, K. Wada, T. Shimizu, H. Takagi and M. Ito, “A Novel AC

Photovoltaic Module System Based on the Impedance-Admittance Conversion

Theory,” in Proc. IEEE Power Electronics Specialists Conference, 2001, pp.

2191-2196.

365

[105] K. C. A. de Souza, M. R. de Castro and F. Antunes, “A DC/AC Converter

for Single-Phase Grid-Connected Photovoltaic Systems,” in Proc. IEEE

International Conference on Industrial Electronics, Control and


[106] H. Fujimoto, K. Kuroki, T. Kagotani and H. Kidoguchi, “Photovoltaic

Inverter with a Novel Cycloconverter for Interconnection to a Utility Line,” in

Proc. IEEE Industry Applications Conference, 1995, pp. 2461-2467.

[107] J. Beristain, J. Bordonau, A. Gilabert and G. Velasco, “Synthesis and

Modulation of a Single Phase DC/AC Converter with High-Frequency

Isolation in Photovoltaic Energy Applications,” in Proc. IEEE Power

Electronics Specialist Conference, 2003, pp. 1191-1196.

[108] M. Xu, J. Zhou and F. C. Lee, “A Current-Tripler DC/DC Converter,”

IEEE Trans. Power Electron., Vol. 19, No. 3, pp. 693-700, May 2004.

[109] P. J. Wolfs, G. F. Ledwich and K. Kwong, “A High Frequency Current

Sourced Link DC to Three Phase Converter,” Journal of Electrical and

Electronics Engineering, Australia, Vol. 11, No. 4, pp. 233-237, Dec. 1991.

[110] P. Wolfs, “High Frequency Link Power Conversion,” PhD Dissertation,

University of Queensland, Australia, 1992.

[111] C. A. Desoer and E. S. Kuh, Basic Circuit Theory. New York: McGraw-Hill,

1969.

[112] P. J. Wolfs, “A Current-Sourced DC-DC Converter Derived via the Duality

Principle from the Half-Bridge Converter,” IEEE Trans. Ind. Electron., Vol.

40, No. 1, pp. 139-144, Feb. 1993.

366

[113] G. Ivensky, I. Elkin and S. Ben-Yaakov, “An Isolated DC-DC Converter

Using Two Zero Current Switched IGBTs in a Symmetrical Topology,” in

Proc. IEEE Power Electronics Specialists Conference, 1994, pp. 1218-1225.

[114] W. C. P. De Aragão Filho and I. Barbi, “A Comparison between Two

Current-Fed Push-Pull DC-DC Converters-Analysis, Design and

Experimentation,” in Proc. IEEE International Telecommunications Energy


[115] D. Qu, “EMI Characterization and Improvement of Bi-Directional DC/DC

Converters,” Master of Science Dissertation, Virginia Polytechnic Institute and

State University, U.S.A., 1999.

[116] J. Kang, “Phase-Shifted Constant Duty Cycle Converter Derived from Two

Module Parallel-Input/Series-Output Modularized Dual Converter for High-

Power Step-up Applications,” Master of Engineering Dissertation, Division of

Electrical Engineering, Korea Advanced Institute of Science and Technology,

Daejon, Korea, Aug. 1999.

[117] J. Kang, C. Roh, G. Moon and M. Youn, “Phase-Shifted Parallel-

Input/Series-Output Dual Inductor-Fed Push-Pull Converter for High-Power

Step-up Applications,” in Proc. European Conference on Power Electronics

and Applications, 2001, pp. 1-12

[118] J. Kang, C. Roh, G. Moon and M. Youn, “High-Power Step-up Converter

with High Efficiency and Fast Output Voltage Dynamics,” in Proc. IEEE

International Conference on Power Electronics and Drive Systems, 2001, pp.

847-853.

367

[119] J. Kang, C. Roh, G. Moon and M. Youn, “Design of Phase-Shifted Parallel-

Input/Series-Output Dual Inductor-Fed Push-Pull Converter for High-Power

Step-up Applications,” in Proc. IEEE International Conference on Industrial

Electronics, Control and Instrumentation, 2001, pp. 1249-1254.


Input/Series-Output Dual Converter for High-Power Step-up Applications,”

IEEE Trans. Ind. Electron., Vol. 49, No. 3, pp. 649-652, Jun. 2002.


Input/Series-Output Dual Convertor for High-Power High-Output Voltage

Applications,” International Journal of Electronics, Vol. 89, No. 8, pp. 603-

624, Aug. 2002.

[122] S. N. Manias and G. Kostakis, “Modular DC-DC Convertor for High-Output

Voltage Applications,” IEE Proc.-B, Vol. 140, No. 2, pp. 97-102, Mar. 1993.

[123] S. N. Manias and G. Kostakis, “A Modular DC-DC Converter for High

Output Voltage Applications,” in Proc. IEEE/NTUA Athens Power Tech


[124] Y. Jang and M. M. Jovanovic, "Two-Inductor Boost Converter," U.S. Patent

6 239 584, 29 May 2001.

[125] Y. Jang and M. M. Jovanovic, “New Two-Inductor Boost Converter with

Auxiliary Transformer,” in Proc. IEEE Applied Power Electronics Conference

and Exposition, 2002, pp. 654-660; also IEEE Trans. Power Electron., Vol.

19, No. 1, pp. 169-175, Jan. 2004.

368

[126] C. Roh, S. Han, S. Hong, S. Sakong and M. Youn, “Dual-Coupled Inductor-

Fed DC/DC Converter for Battery Drive Applications,” IEEE Trans. Ind.

Electron., Vol. 51, No. 3, pp. 577-584, Jun. 2004.

[127] Y. Jang and M. M. Jovanovic, “A New Soft-Switched DC-DC Front-End

Converter for Applications with Wide-Range Input Voltage from Battery

Power Sources,” in Proc. IEEE International Telecommunications Energy


[128] X. Xie, J. M. Zhang, D. Jiao and Z. Qian, “A Novel Control Scheme for the

Two-Inductor Boost Converter,” in Proc. IEEE International Conference on

Power Electronics and Drive Systems, 2003, pp. 578-581.

[129] M. H. Todorovic, L. Palma and P. Enjeti, “Design of a Wide Input Range

DC-DC Converter with a Robust Power Control Scheme Suitable for Fuel Cell

Power Conversion,” in Proc. IEEE Applied Power Electronics Conference and

Exposition, 2004, pp.374-379.

[130] X. Gao and R. Ayyannar, “A Novel Buck-Cascaded Two-Inductor Boost

Converter with Integrated Magnetics,” in Proc. IEEE International

Telecommunications and Energy Conference, 2004, pp. 190-197.

[131] B. O’Sullivan, R. Morrison, M. G. Egan, J. Slowey and B. Barry, “A

Regenerative Load System for the Test of Intel VRM 9.1 Compliant Modules,”

in Proc. IEEE Applied Power Electronics Conference and Exposition, 2004,

pp. 298-303.

[132] R. P. Severns and G. E. Bloom, Modern DC-to-DC Switchmode Power

Converter Circuits. New York: Van Nostrand Reinhold, 1985.

369

[133] D. C. Hamill, “Time Reversal Duality and the Synthesis of a Double Class E

DC-DC Converter,” in Proc. IEEE Power Electronics Specialists Conference,

1990, pp. 512-521.

[134] D. C. Hamill, “Time Reversal Duality in DC-DC Converters,” in Proc. IEEE

Power Electronics Specialists Conference, 1997, pp.789-795.

[135] R. Severns, “Circuit Reinvention in Power Electronics and Identification of

Prior Work,” in Proc. IEEE Applied Power Electronics Conference and

Exposition, 1997, pp. 654-660; also IEEE Trans. Power Electron., Vol. 16, No.

1, pp. 3-9, Jan. 2001.

[136] O. S. Seiersen, “Power Supply Circuit,” Danish Patent PA 1987 03826, 22

Jul. 1987.

[137] O. S. Seiersen, “Power Supply Circuit,” U.S. Patent 4 899 271, 6 Feb. 1990.

[138] C. Peng, M. Hannigan and O. Seiersen, “A New Efficient High Frequency

Rectifier Circuit,” in Proc. International High Frequency Power Conversion


[139] K. O’Meara, “A New Output Rectifier Configuration Optimized for High

Frequency Operation,” in Proc. International High Frequency Power

Conversion Conference, 1991, pp. 219-226.

[140] L. Balogh. (1994, Dec.). The Current-Doubler Rectifier: an Alternative

Rectification Technique for Push-Pull and Bridge Converters. Unitrode Corp.

[Online]. Available: http://focus.ti.com/lit/an/slua121/slua121.pdf

[141] L. Huber and M. H. Jovanovic, “Forward-Flyback Converter with Current-

Doubler Rectifier: Analysis, Design, and Evaluation Results,” IEEE Trans.

Power Electron., Vol. 14, No. 1, pp. 184-192, Jan. 1999.

370

[142] P. Xu, Q. Wu, P. Wong and F. C. Lee, “A Novel Integrated Current Doubler

Rectifier,” in Proc. IEEE Applied Power Electronics Conference and


[143] P. Xu and F. C. Lee, “Design of High-Input Voltage Regulator Modules with

a Novel Integrated Magnetics,” in Proc. IEEE Applied Power Electronics

Conference and Exposition, 2001, pp. 262-267.

[144] L. Yan and B. Lehman, “Isolated Two-Inductor Boost Converter with One

Magnetic Core,” in Proc. IEEE Applied Power Electronics Conference and


[145] L. Yan and B. Lehman, “An Integrated Magnetic Isolated Two-Inductor

Boost Converter: Analysis, Design and Experimentation,” IEEE Trans. Power

Electron., Vol. 20, No. 2, pp. 332-342, Mar. 2005.

[146] R. L. Steigerwald, “Power Electronic Converter Technology,” Proc. IEEE,

Vol. 89, No. 6, pp. 890-897, Jun. 2001.

[147] D. Maksimovic, “A MOS Gate Drive with Resonant Transitions,” in Proc.

IEEE Power Electronics Specialists Conference, 1991, pp. 527-532.

[148] STMicroelectronics. (2001, Jul.). STB50NE10 Datasheet. [Online].

Available: http://www.st.com/stonline/products/literature/ds/6034/stb50ne10

.pdf

[149] Cornell Dubilier. Types MC and MCN Surface-Mount Mica Chip

Capacitors. [Online]. Available: http://www.cornell-dubilier.com/catalogs/

MC.pdf

371

[150] G. Bloom, "Multi-Chambered Planar Magnetics Blends Inductors and

Transformers," Power Electronics Technology, Vol. 29, No. 4, pp. 22-34, Apr.

2003.

[151] S. Cuk, “A New Zero-Ripple Switching Dc-to-Dc Converter and Integrated

Magnetics,” in Proc. IEEE Power Electronics Specialist Conference, 1980,

pp.12-32; also IEEE Trans. Magn., Vol. 19, No. 2, pp. 57-75, Mar. 1983,

[152] S. Cuk, “New Magnetic Structures for Switching Converters,” IEEE Trans.

Magn., Vol. 19, No. 2, pp. 75-83, Mar. 1983; also in Proc. Power Conversion

International Conference, Sept., 1981.

[153] G. Bloom and R. Severns, “The Generalized Use of Integrated Magnetics

and Zero-Ripple Techniques in Switchmode Power Converters,” in Proc. IEEE

Power Electronics Specialist Conference, 1984, pp. 15-33.

[154] G. B. Crouse, “Electrical Filter,” U.S. Patent 1 920 948, 1 Aug. 1933.

[155] W. Chen, “Low Voltage High Current Power Conversion with Integrated

Magnetics,” PhD Dissertation, Virginia Polytechnic Institute and State

University, USA, 1998.

[156] W. Chen, G. Hua, D. Sable and F. Lee, “Design of High Efficiency, Low

Profile, Low Voltage Converter with Integrated Magnetics,” in Proc. IEEE

Applied Power Electronics Conference and Exposition, 1997, pp. 911-917.

[157] W. Chen, “Single Magnetic Low Loss High Frequency Converter,” U.S.

Patent 5 784 266, 21 Jul. 1998.

[158] P. Xu, Q. Wu, P. Wong and F. C. Lee, “A Novel Integrated Current Doubler

Rectifier,” in Proc. IEEE Applied Power Electronics Conference and


372

[159] J. Sun and V. Mehrotra, “Unified Analysis of Half-Bridge Converters with

Current-Doubler Rectifier,” in Proc. IEEE Applied Power Electronics


[160] J. Sun, K. F. Webb and V. Mehrotra, “An Improved Current-Doubler

Rectifier with Integrated Magnetics,” in Proc. IEEE Applied Power Electronics


[161] J. Sun, K. F. Webb and V. Mehrotra, “Integrated Magnetics for Current-

Doubler Rectifiers,” IEEE Trans. Power Electron., Vol. 19, No. 3, pp. 582-

590, May 2004.

[162] Q. Li and P. Wolfs, “A Current Fed Two-Inductor Boost Converter for Grid

Interactive Photovoltaic Applications,” in Proc. Australasian Universities

Power Engineering Conference, 2004.

[163] Q. Li and P. Wolfs, “A Leakage-Inductance-Based ZVS Two-Inductor Boost

Converter with Integrated Magnetics,” IEEE Power Electron. Lett., Vol. 3, No.

2, pp. 67-71, Jun. 2005.

[164] Q. Li and P. Wolfs, “A Comparison of Three Magnetics Integration

Solutions for the Two-Inductor Boost Converter,” in Proc. Australasian

Universities Power Engineering Conference, 2005, accepted.

[165] C. P. Steinmetz, “On the Law of Hysteresis,” Proc. IEEE, Vol. 72, pp. 196-

221, Feb. 1984.

[166] Ferroxcube. (2004, Sept.). ETD39/20/13 Datasheet. [Online]. Available:

http://www.ferroxcube.com/prod/assets/etd39.pdf

[167] Ferroxcube. (2004, Sept.). ETD29/16/10 Datasheet. [Online]. Available:

http://www.ferroxcube.com/prod/assets/etd29.pdf

373

[168] X. Zhou, P. L. Wong, P. Xu, F. C. Lee and A. Q. Huang, “Investigation of

Candidate VRM Topologies for Future Microprocessors,” IEEE Trans. Power

Electron., Vol. 15, No. 6, pp. 1172-1182, Nov. 2000.

[169] W. Chen. (1999, Sept.). High Efficiency, High Density, Polyphase

Converters for High Current Applications. Linear Technology Corp. [Online].

Available: http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,

C1003,C1042,C1032,C1062,P1726,D4166

[170] F. P. Dawson, “DC-DC Converter Interphase Transformer Design

Considerations: Volt-Seconds Balancing,” in Digests International Magnetics

Conference, 1990, pp. ER-05; also IEEE Trans. on Magn., Vol. 26, No. 5, pp.

2250 – 2252, Sept. 1990.

[171] B. Travis, “The Quest for High Efficiency in Low-Voltage Supplies,” EDN,

pp. 56-66, 1 Sept., 2000.

[172] C. Blake, D. Kinzer and P. Wood, “Synchronous Rectifiers versus Schottky

Diodes: a Comparison of the Losses of a Synchronous Rectifier versus the

Losses of a Schottky Diode Rectifier,” in Proc. IEEE Applied Power

Electronics Conference and Exposition, 1994, pp. 17-23.

[173] J. D. Van Wyk and J. A. Ferreira, “Transistor Inverter Design Optimization

in the Frequency Range above 5 kHz up to 50 kVA,” IEEE Trans. Ind.

Applicat., Vol. 19, No. 2, pp. 296-302, Mar./Apr. 1983.

[174] M. E. Levinshtein, T. T. Mnatsakanov, P. A. Ivanov, J. W. Palmour, S. L.

Rumyantsev, R. Singh and S. N. Yurkov, “High Voltage SiC Diodes with

Small Recovery Time,” Electron. Lett., Vol. 36, No. 14, pp. 1241-1242, Jul.

2000.

374

[175] S. H. Weinberg, “A Novel Lossless Resonant MOSFET Driver,” in Proc.

IEEE Power Electronics Specialists Conference, 1992, pp. 1003 –1010.

[176] J. Qian and G. Bruning, “2.65 MHz High Efficiency Soft-Switching Power

Amplifier System,” in Proc. IEEE Power Electronics Specialists Conference,

1999, pp. 370-375.

[177] W. A. Tabisz, P. Gradzki and F.C. Lee, “Zero-Voltage-Switched Quasi-

Resonant Buck and Flyback Converter – Experimental Results at 10 MHz,” in

Proc. IEEE Power Electronics Specialists Conference, 1987, pp. 404-413; also

IEEE Trans. Power Electron., Vol. 4, No. 2, pp. 194-204, Apr. 1989.

[178] J. Diaz, M. A. Perez, F. M. Linera and F. Aldana, “A New Lossless Power

MOSFET Driver Based on Simple DC/DC Converters,” in Proc. IEEE Power


[179] Y. Chen, F. C. Lee, L. Amoroso and H. Wu, “A Resonant MOSFET Gate

Driver with Complete Energy Recovery,” in Proc. International Power

Electronics and Motion Control Conference, 2000, pp. 402-406.

[180] K. Yao and F. C. Lee, “A Novel Resonant Gate Driver for High Frequency

Synchronous Buck Converters,” in Proc. Applied Power Electronics

Conference, 2001, pp. 280-286; also IEEE Trans. Power Electron., Vol. 17,

No. 2, pp. 180-186, Mar. 2002.

[181] T. López, G. Sauerlaender, T. Duerbaum and T. Tolle, “A Detailed Analysis

of a Resonant Gate Driver for PWM Applications,” in Proc. Applied Power

Electronics Conference, 2003, pp. 873-878.

375

[182] K. J. Christoph, D. M. Bernero, D. J. Shortt and B. J. Lamb, “High

Frequency Power MOSFET Gate Drive Considerations,” in Proc. International

High Frequency Power Conference, 1988, pp.173-180.

[183] P. D. Ziogas, Y. Kang and V. R. Stefanovic, “Rectifier-Inverter Frequency

Changers with Suppressed DC Link Components,” in Proc. IEEE Industry

Applications Conference, 1985, pp. 1180-1189.

[184] L. M. Malesani, L. Rossetto, P. Tenti, and P. Tomasin, “AC/DC/AC PWM

Converter with Reduced Energy Storage in the DC Link,” IEEE Trans. Ind.

Applicat., Vol. 31, No. 2, pp. 287–292, Mar./Apr. 1995.

376

APPENDIX COMMERCIAL AC MODULE INVERTERS

Inverter Name GRIDFIT 250 SUNMASTER 130S OK4-100 OK5-LV

Manufacturer EXENDIS MASTERVOLT NKF NKF

Rated Power (W) 200 110 100 280

Power Density (W/cm3) 0.13 0.13 0.30 0.23

Efficiency >90% 92% 94% 93%

Inverter Name Solcolino Soladin 120 Edisun E230721G

Manufacturer Hardmeier MASTERVOLT Alpha Real AG

Rated Power (W) 180 120 240

Power Density (W/cm3) - 0.20 0.18

Efficiency 91.7% 93% 91.7%

Other commercial ac module inverters include SunSine 300 and DMI150/35, which

employ line frequency transformers in the voltage boosting stage and EVO300,

PowerWall and Plug&Power, whose circuit topologies cannot be located.

High Frequency Transformer Linked Converters For Photovoltaic Applications Q Li [Thesis]

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