IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 2011 3461

High-Frequency High-Efficiency CLL ResonantConverters With Synchronous Rectifiers

Daocheng Huang, Dianbo Fu, Member, IEEE, Fred C. Lee, Fellow, IEEE, and Pengju Kong, Member, IEEE

Abstract—This paper proposes a CLL resonant dc–dc con-verter as an option for offline applications. This topology canachieve zero-voltage switching from zero load to a full load andzero-current switching for output rectifiers and makes the imple-mentation of a secondary rectifier easy. This paper also presentsa novel methodology for designing CLL resonant convertersbased on efficiency and holdup time requirements. An optimaltransformer structure is proposed, which uses a current-typesynchronous rectifier (SR) drive scheme. An 800-kHz 250-W CLLresonant converter prototype is built to verify the proposed circuit,design method, transformer structure, and SR drive scheme.

Index Terms—Design methodology, driving scheme, high effi-ciency, high frequency, high power density, resonant converter,synchronous rectifier, transformer.

I. INTRODUCTION

D ISTRIBUTED POWER SYSTEMS (DPSs) are widelyused in offline applications, such as servers and telecom

applications. In a DPS, power is processed in two stages:front-end converters and load converters. Efficiency and powerdensity are the two main driving forces of front-end convert-ers [1]. Front-end converters normally consist of three parts:an electromagnetic interference (EMI) filter, a power-factor-correction circuit, and a dc–dc converter.

For computing applications, holdup time operation is re-quired. Bulky capacitors must be used to provide energy duringthe holdup time. A wide operation range in the dc–dc stage isnecessary to reduce the holdup time capacitance.

Pulsewidth modulation (PWM) converters are widely em-ployed as front-end dc–dc converters. Two-switch forward con-verters [2] have received a lot of interest for their robustness andtheir easy transformer reset mechanism. However, their highswitching loss and large filter inductance are major concerns.Phase-shift full-bridge (PSFB) converters [3] can achieve zero-voltage switching (ZVS) to enhance the efficiency of the con-verter. However, when a holdup time is needed, the duty cycleof PSFB converters is small at nominal conditions. A smallduty cycle leads to large circulating energy and high turnoffswitching loss, which significantly sacrifices the efficiency.

Manuscript received January 2, 2010; revised May 3, 2010 and August 9,2010; accepted September 9, 2010. Date of publication November 18, 2010;date of current version July 13, 2011.

D. Huang, F. C. Lee, and P. Kong are with the Virginia Polytechnic Instituteand State University (Virginia Tech), Blacksburg, VA 24061 USA (e-mail:huangdao@vt.edu; fclee@vt.edu; pjkong@vt.edu).

D. Fu is with Huawei Technologies, Plano, TX 75075 USA (e-mail:dfu@huawei.com).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2010.2093474

The aforementioned problems can be solved by using anLLC resonant dc–dc converter [4]–[6]. Low switching loss andlow circulating energy are achievable at nominal conditions.Thus, high-efficiency operation is accomplished. A wide inputvoltage range is obtained in the low-frequency range, where thevoltage gain is very high. Thus, the LLC resonant converter issuitable for offline applications with holdup time requirements.

Nevertheless, for LLC resonant converters, there are stillissues, such as how to drive synchronous rectifiers (SRs) andhow to achieve low loss for a gapped transformer at highswitching frequencies.

Commercially, the drain–source voltage of SRs is sensed todrive SRs. However, the package inductance of an SR wouldcause a phase shift of the sensed voltage, which introduceshigh body-diode conduction loss. A compensation drivingscheme has been proposed to correct the deviation [7]; however,this compensation scheme requires extra circuits, which arecomplicated. A secondary-side current-sensing method is alsoused to drive SRs [8]. However, the large size of the current-sensing transformer makes it awkward to use. For high-currentapplications, the extra resistance of the current transformer(CT) winding becomes lossy. On the other hand, the primary-side current is much lower, which means that the CT can besmall and more efficient. However, the magnetizing inductanceof the transformer for an LLC converter is used as resonantinductance and thus is relatively small. Due to the magnetizingcurrent, the sensed primary-side current and the SR currentare out of phase. Hence, the SR cannot be driven by sensingthe primary-side current. To solve these issues, Wu et al. [9]propose an improved current-sensing method with an additionalinductor and compensation circuits. However, the complexityand cost are major drawbacks. Consequentially, determininghow to effectively drive an SR remains an issue for LLCresonant converters.

In the transformer design, an air gap is used to control themagnetizing inductance. However, high eddy-current losses areinduced due to the fringing effect of the air gap. The higher theswitching frequency, the stronger the fringing effect.

The CLL resonant converter is a potential alternative solu-tion for front-end dc–dc converters. The CLL resonant con-verter is studied with a full-bridge configuration in [10]. Thedesign methodology is limited to zero-current switching (ZCS)applications where insulated-gate bipolar transistors are em-ployed, and it is not suitable for high-frequency applicationswhere MOSFETs are used. In addition, the impact of the holduptime operation is not considered. An asymmetrical PWM ZVSCLL converter is proposed in [11] and [12]. The asymmet-rical operation introduces high rms currents and high turnoff

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3462 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 2011

currents, which cause high conduction loss and turnoff loss. Anextra snubber capacitor is needed to reduce the high turnoffloss, which increases the cost and complexity of the wholesystem.

This paper proposes a symmetrical-duty-cycle frequency-controlled CLL resonant converter. Using this control mode,lower rms current and turnoff currents can be achieved. Thisleads to much lower conduction loss and switching lossthan that in an asymmetrical PWM-controlled converter. Inaddition, snubber capacitors and complicated design are notrequired. Based on the symmetrical operation mode, it ispossible to achieve ZVS for the entire load range. Meanwhile,the air gap in the transformer is omitted to eliminate thefringing effect. Moreover, because of very high magnetizinginductance, the transformer’s primary-side current is in phasewith the secondary-side current. Thus, the SR can be easilydriven. Hence, higher efficiency and higher power density canbe achieved.

This paper is organized as follows. The basic characteristicsof the proposed CLL resonant converters are discussed inSection II. A novel optimization design methodology of CLLresonant converters is presented in Section III. Section IVpresents the optimal transformer structure for CLL resonantconverters. A current-type SR drive scheme is proposed inSection V. Finally, the experimental results are discussed inSection VI. An 800-kHz 250-W prototype is built to verify theproposed optimal design method, the transformer structure, andthe proposed SR driving scheme. Using this prototype, up to a96.7% efficiency is achieved.

II. CHARACTERISTICS OF CLL RESONANT CONVERTER

The topology of the CLL resonant converter is shown inFig. 1. The main relationships in the CLL resonant converterare given in (1)–(9), where ωs is the switching angular fre-quency, Ro is the load resistor, and Ts is the switching period.

1) Normalized voltage gain

M = 2Vo · n/Vin. (1)

2) Resonant inductor ratio

Ln = L1/L2. (2)

3) Equivalent resonant inductor

Leq = L1 · L2/(L1 + L2). (3)

4) Equivalent characteristic inductor

LP = L21/(L1 + L2) = Leq · Ln. (4)

5) Characteristic impedance

Z0 =√

Leq/C1. (5)

6) Characteristic angular frequency

ωo = 2πfo = 2π/T0 = 1/√

LeqC1. (6)

Fig. 1. CLL resonant converter.

Fig. 2. Basic characteristics of the CLL resonant converter. (a) Equivalentcircuit of CLL resonant converter. (b) CLL resonant converter’s gain curves.

7) Parallel resonant frequency

f02 = 1/(2π ·√

L1 · C1). (7)

8) Quality factor

Q = Z0/(n2 · Ro). (8)

9) Normalized characteristic angular frequency

ωn = ωs/ωo = fs/fo. (9)

Fundamental mode approximation is used for resonant tankanalysis. Based on the equivalent circuit shown in Fig. 2(a),the voltage gain expression of the CLL resonant converter isdeduced as follows:

M =nVo

Vin

2

=

∣∣∣∣∣ −(1 + Ln) · ω2n

(1+Ln)2

Ln· π2

8 Q (1 − ω2n) · jωn + 1 − (1 + Ln) · ω2

n

∣∣∣∣∣ .

(10)

The gain curves of the CLL resonant converter are plotted inFig. 2(b). There are two resonant frequencies for CLL resonantconverters. One is the series resonant frequency, whose value isequal to the characteristic frequency. The other resonant fre-quency is the parallel resonant frequency. The parallel resonantfrequency is introduced by L1 and C1 and is defined as f02. Theoperation regions of CLL resonant converters could be dividedinto three parts, as shown in Fig. 2. These operation regions arethe ZCS region, the ZVS1 region, and the ZVS2 region.

HUANG et al.: HIGH-FREQUENCY HIGH-EFFICIENCY CLL RESONANT CONVERTERS WITH SRs 3463

Fig. 3. Waveforms of CLL resonant converter at each operation region.(a) ZCS region. (b) ZVS1 region. (c) ZVS2 region. (d) At resonant frequencywith full load. (e) At resonant frequency with no load.

As shown in Fig. 3(a), in the ZCS region, the primary-sideswitches (S1, S2) can achieve ZCS. During [0, tr], L1, L2, andC1 resonate with each other. During [tr, Ts/2], L1 resonateswith C1, and iC1 turns negative before S1 is turned off. As aresult, iC1 goes through D1, which is the body diode of S1.At Ts/2, S2 is turned on, and D1 will be turned off. The hardturnoff of the MOSFET body diodes generates severe reverse-recovery loss and high-voltage stress. Thus, this operationregion should be avoided for MOSFETs.

As shown in Fig. 3(b), in the ZVS1 region, the primary-side switches (S1, S2) can achieve ZVS. During [0, Ts/2], Vs2

and Vo1 are positive. During [0, tr], L1, L2, and C1 resonate.During [tr, Ts/2], L1 resonates with C1. At Ts/2, iC1 remainspositive. When S1 is turned off, iC1 charges and discharges thejunction capacitors of S1 and S2, respectively. Hence, ZVS isachieved. In this region, an output rectifier can achieve ZCS.This suggests that low di/dt is beneficial for rectifiers.

The waveforms of the CLL resonant converter in the ZVS2region are plotted in Fig. 3(c). The primary-side switches(S1, S2) can also achieve ZVS. During [0, Ts/2], Vs2 andVo1 are positive. During [0, Ts/2], L1, L2, and C1 resonate.At Ts/2, iC1 is still positive. When S1 is turned off, iC1

contributes to the ZVS operation. When S1 is turned off, Vs2

drops sharply. However, due to the conduction of the SR, Vm

is clamped to nVo. During the MOSFET’s transition dead time,VC1 changes very little. As a consequence, the voltage acrossL2 becomes very high. iL2 drops quickly until it reaches zero.It can be observed that high di/dt will be generated if the L2

value is small. Therefore, this region is not preferred with thedesign of a small L2.

The point at which the switching frequency equals the res-onant frequency is very important. This point is the optimalpoint of the frequency range for minimal switching loss andcirculating energy. Thus, at the nominal condition, the CLLresonant converter should be designed to operate close to theresonant frequency.

At the resonant frequency [shown by a black dot in Fig. 2(b)],according to (10), the voltage gain is derived as

M = 1 + 1/Ln. (11)

The voltage gain value at the resonant frequency is indepen-dent of the load. The waveforms of the heavy-load and no-load conditions at this point are shown in Fig. 3(d) and (e),respectively.

Equation (12) is derived from the circuit drawn in Fig. 1.From Fig. 3(d) and (e), the boundary conditions are representedin (13). {

C1 · d(Vin−Vm)dt = iC1, L1 · diL1

dt = Vm

L2d(iC1−iL1)

dt = Vm − Vo1

(12)

{iL1(0) = −iL1

(Ts

2

), iC1(0) = iL1(0)

2Ts

·∫ Ts

20 [iC1(t) − iL1(t)] dt = Vo

n·Ro.

(13)

Thus, the current expressions at the series resonant frequencyare deduced in⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩

iL1(t) = πL2Vin

4ωsL21·[

(L1+L2)ωs

n2Rosin(ωst) − cos(ωst)

]+ Vin

2L1

(t − Ts

4

)iC1(t) = πL2ωsC1Vin

4L1·[

(L1+L2)ωs

n2Rosin(ωst) − cos(ωst)

]iC1(t) = iL1(t) + iL2(t).

(14)

At the MOSFETs’ transition dead time, t = 0, t = Ts/2, andiL1 = 0. Thus, iC1 = iL1 and is derived in (15). This currentcharges and discharges the junction capacitors of the primary-side MOSFETs. During the dead time, since iC1 and iL1 areindependent of the load, ZVS can be achieved for the entireload range with the proper design.

|iC1(0)| = |iL1(0)| =∣∣∣∣iC1

(Ts

2

)∣∣∣∣ =∣∣∣∣iL1

(Ts

2

)∣∣∣∣=

Vin

2To

4L1 + L2

L21

. (15)

Physically speaking, all three resonant elements resonateduring power delivery. When the output rectifiers are off, onlytwo elements (L1 and C1) resonate. In contrast, for exist-ing LLC resonant converters, two series-resonant elements

3464 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 2011

resonate during power delivery. When the output rectifiersare off, all three resonant elements resonate. Due to the verydifferent operation scenario for the proposed CLL resonantconverter, the voltage gain at the resonant frequency is 1 +1/Ln. The voltage boost capability at the resonant frequencymay be very useful for high-voltage applications. The benefitsof the topology difference in the transformer design and ofbeing SR driven are discussed in Sections IV and V.

III. DESIGN METHODOLOGY FOR CLLRESONANT CONVERTERS

There are many papers that present different design meth-ods for the LLC resonant converter. In [13], LLC resonantconverters are designed with a numeric processing scheme.In this scheme, resonant tank parameters are chosen basedon a numerically determined minimum input power with agiven output power. Nevertheless, this method relies purely onnumeric analysis and is hence very complicated. It requirestremendous programming work. Furthermore, even with ded-icated iterations, only the primary rms current is taken intoaccount; the switching loss and secondary-side rms current arenot considered. Thus, it is desirable to further improve theprocess of optimization.

Reference [14] gives a design method based on start-upcurrent, efficiency, and holdup time requirements. The combi-nation of Ln and Q impacts the efficiency, and this paper usesthese variables to present a trend of achieving high efficiency.However, the suitable range that is given for Ln and Q is basedon observation. Thus, the precise optimal efficiency point can-not be obtained, and trial and error iterations are still necessaryfor this design strategy. Lu et al. [15] provide a design methodbased on efficiency and holdup time requirements. However,the effects of dead time and device characteristics on the systemefficiency are ignored in both [14] and [15]. Thus, the Ln andQ curves plotted in these papers are actually not very accurateat high switching frequencies.

The optimal design methodology for CLL resonant convert-ers presented in this paper is based on the requirement of highefficiency and the need to accommodate holdup time operation.This design achieves high efficiency over a wide load range.

A. RMS Current Without Consideration of Dead-Time Period

If the switching frequency is low, the dead time (tdead) ismuch shorter than the switching period (Ts). For the sake ofsimplicity, we treat the switching period Ts as approximatelythe resonant period To at the resonant point.

In accordance with (14) and (15), assuming there is zerodead time, the primary-side and secondary-side rms currentsare derived in⎧⎪⎪⎨

⎪⎪⎩IRMS_P = 1

4√

2Vo

Ro

(2Vo

Vin

)√(Vin

2Vo

)4R2

oT 2s

L2P

+ 4π2

IRMS_S = π4

Vo

Ro

√5π2−4812π2

(Vin

2Vo

)4R2

oT 2s

π2L2P

+ 1.

(16)

In (16), IRMS_P and IRMS_S are the primary-side rmscurrent and the secondary-side rms current, respectively. Vin

and Vo represent the input voltage and the output volt-age, respectively, and Ro represents the full load resistance.LP should be designed to be large to reduce device rmscurrents.

B. RMS Current With Consideration of Dead-Time Period

For high-frequency operation, the dead time tdead is socritical that it affects the design considerably. During tdead,no energy is transferred to the load. Thus, a large dead timecauses less of an energy transfer interval at the same switchingfrequency than does a smaller dead time. This leads to higherrms current for the same energy transfer. This dead-time effectshould not be ignored. Hence, (16) provides only approximateresults for low frequencies or systems with very small tdead.With the consideration of tdead, the expressions of the primary-side and secondary-side rms currents can be deduced using (17)shown at the bottom of the page.

C. Dead-Time Influence on RMS Current andTurnoff Current

During tdead, the junction capacitor of the primary-sidedevices will be charged and discharged to achieve ZVS. Ceq

equals the junction capacitance of one primary-side MOSFET.During a short tdead, the current of L1, i.e., iL1_max, remains

almost the same and is equal to the primary-side turnoff currentIturnoff .

Iturnoff = |iL1(0)| =∣∣∣∣iL1

(Ts

2

)∣∣∣∣ =Vin

2Ts

4L1 + L2

L21

=To

8Vin

Lp. (18)

Iturnoff helps to achieve ZVS and should be large enough tocharge and discharge the junction capacitors during tdead.

Iturnoff × tdead ≥ 2CeqVin. (19)

⎧⎪⎪⎨⎪⎪⎩

IRMS_P = 12√

2

V 2o

VinRo·√(

Vin

2Vo

)4R2

oT 2o

L2P

+ 4π2 +16π2(Totdead+t2dead)

T 2o

IRMS_S =√

312

Vo

Ro·√(

Vin

2Vo

)4(5π2−48)R2

oT 3o

L2P

(To+2tdead)+ 12π4To

To+2tdead+

48π4(Totdead+t2dead)To(To+2tdead)

(17)

HUANG et al.: HIGH-FREQUENCY HIGH-EFFICIENCY CLL RESONANT CONVERTERS WITH SRs 3465

Substituting (18) into (19), we get

Lp ≤ To · tdead

16Ceq. (20)

To achieve ZVS, LP should satisfy (20). Meanwhile, a largeLP is preferred for low conduction loss. Hence, LP should bechosen as To · tdead/16Ceq .

Applying LP = To · tdead/16Ceq to (17), we get (21) shownat the bottom of the page.

Td_norm and ZC_norm are defined as follows:

Td_norm = tdead/Ts (22)

ZC_norm =1

Ceqωs

/ [Ro ·

(Vin

2Vo

)2]

. (23)

ZC_norm indicates the impedance relationship of the junctioncapacitor of the device and the load.

By substituting (22) and (23) into (21) and normalizing(21) by the factors Po/0.5Vin and Po/Vo, (24) shown at thebottom of the page can be derived. Po equals V 2

o /Ro. Hence,it is expedient to apply normalized current to evaluate theperformance.

By applying (22), (23), and LP = To · tdead/16Ceq to (18)and normalizing by the factor Po/0.5Vin, (15) can be deduced.

ITurnoff_norm =2π

1Td_norm

1ZC_norm

. (25)

Fig. 4(a) shows the difference in the primary rms currentwith and without the consideration of tdead. The dashed line isobtained from (16), and the dotted line is based on (17). As wecan see, tdead plays a significant role in a high Td_norm rangeor a high-frequency range.

Fig. 4(b) shows the normalized primary-side rms currentIRMS_P_norm and secondary-side rms current IRMS_S_norm.Td_norm influences the primary-side rms current in two ways.On the one hand, based on (22) and (18), a large Td_norm meansa large Lp, and less Iturnoff is required to achieve ZVS. Hence,

Fig. 4. RMS current calculation results. (a) Primary-side rms current with andwithout consideration of dead-time period. (b) Normalized primary-side andsecondary-side rms currents considering dead-time period.

less circulating current is achieved. On the other hand, a largerTd_norm causes a smaller power delivery duty cycle. To providethe same energy to the load, higher power is required during theshorter power delivery period, which leads to higher current.Taking the aforementioned two aspects into consideration, therelationship between Td_norm and the primary-side rms currentexhibits a U shape. There is an optimal dead time at which thelowest rms current can be achieved. This optimal dead time isidentified in the following paragraph.

With simple algebra, the normalized dead time for the min-imal primary-side rms current and secondary-side rms currentcan be calculated using⎧⎪⎨

⎪⎩Td_norm_min_prim = 2

/(4 + 3

√π4Z2

C_norm

)Td_norm_min_ sec = 1

/ (2 + π2

4

3√

12·Z2C_norm

5π2−48

).

(26)

D. Design Methodology

The design method is based on the requirements of highefficiency and holdup time. The device losses are a major partof the system losses. Based on (24) and (25), we know that theconduction loss and switching loss of the devices are relatedto the output power, the characteristics of the devices, the

⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩

IRMS_P = 12√

2

V 2o

VinRo·√(

Vin

2Vo

)4R2

oT 2o(

To·tdead16Ceq

)2 + 4π2 +16π2(Totdead+t2dead)

T 2o

IRMS_S =√

624π

Vo

Ro

√(Vin

2Vo

)4(5π2−48)R2

oT 3o(

To·tdead16Ceq

)2(To+2tdead)

+ 12π4To

To+2tdead+

48π4(Totdead+t2dead)To(To+2tdead)

(21)

⎧⎪⎪⎨⎪⎪⎩

IRMS_P_norm = 14√

2

√(1

Td_norm

8π

)21

Z2C_norm

+ 4π2

(1−2Td_norm)2

IRMS_S_norm =√

624π

√(1

Td_norm

8π

)21

Z2C_norm

(5π2 − 48)(1 − 2Td_norm) + 12π4

1−2Td_norm

(24)

3466 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 2011

Fig. 5. Design relationship. (a) Ratio of device loss and power versus deadtime under different loads. (b) Q and Ln relationship for ZVS requirement.

switching frequency, and the dead time. In particular, (24) indi-cates that the conduction losses of the primary- and secondary-side devices are not influenced by the resonant tank design.According to (25), the turnoff loss of the primary-side deviceis determined by the dead-time design, but it is not affected bythe resonant tank parameters. Therefore, the device losses areindependent of the resonant tank design.

For given output power, devices, and switching frequency,the device losses can be obtained using the dead-time design.The conduction losses of the devices can be easily calculatedby (24). The losses can be normalized by the output power.

Pcond_loss_P and Pcond_loss_S indicate the primary-side andsecondary-side conduction losses, respectively. Rdson_p andRdson_s indicate the turn-on resistances of the primary-sideand secondary-side devices. Pcond_P_norm and Pcond_S_norm

indicate the normalized primary-side and secondary-side con-duction losses⎧⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎩

Pcond_P_norm = Pcond_loss_P

Po

= Rdson_p

Ro

(2Vo

Vin

)2

I2RMS_P_norm

Pcond_S_norm = Pcond_loss_S

Po

= Rdson_s

RoI2RMS_S_norm.

(27)

Equation (25) shows the relationship between the dead timeand turnoff current. The turnoff loss can be attained either byprecise device simulation or by a circuit test. In this paper, thedevice turnoff loss is obtained by experimental measurement.A design example is given to show the proposed optimal designprocedure. The design specifications are Vin = 400 V, Vo =12 V, and Po = 250 W. The switching frequency is 800 kHzfor the sake of high power density. STB12NM50FD (Ceq =142 pF) and BSC014N03MSG are chosen as the primary- andsecondary-side devices.

Based on (25), (27), and the device test results, Fig. 5(a)shows the device loss percentage curves with variations indead time.

According to the 80 Plus requirement [1], high efficiencyshould be achieved at 20%, 50%, and 100% load conditions. Asuitable value for the dead time should be chosen to satisfy thehigh efficiency requirement. Hence, a dead time that falls withinthe shaded area is recommended for better efficiency over awide load range. Based on Fig. 5(a), a dead time of 170 ns ischosen. Once the optimal dead time is selected, (20) can be usedto determine that LP = 67.6 μH. Because the switching fre-

Fig. 6. Peak gain curves of different combinations of Q and Ln. (a) Peak gainfor fixed Ln. (b) Peak gain for different Ln’s.

Fig. 7. Three-dimensional plots of the proposed design method.

quency is 800 kHz, the series resonant frequency fo is 1.1 MHzwith the consideration of the dead time.

For a given LP , the relationship between Q and Ln can beexpressed as

Q · (1 + Ln)2

Ln= LP ·

(2Vo

Vin

)2 2πfo

Ro. (28)

In this case, Q · (1 + Ln)2/Ln = 2.918 is obtained becauseLP = 67.6 μH. The relationship between Q and Ln is plottedin Fig. 5(b). To complete the resonant tank design, Q and Ln

should be determined.The holdup time operation requirement is another resonant

tank design constraint. In general, for each Q, the maximumgain is achieved at the resonant ridge, as shown in Fig. 6(a).The peak gain curves of different Ln’s are drawn in Fig. 6(b).The peak gain decreases as Q increases when Ln is fixed.Meanwhile, the peak gain increases as Ln decreases for thesame Q.

Fig. 7 shows the peak gain surface for different values of Qand Ln, as well as the gain plane of the holdup time operationconstraint. In this design, the holdup time gain is adopted as 1.8.Thus, a peak gain surface higher than 1.8 can be considered.

Equation (28) and Fig. 7 are determined by the high ef-ficiency constraint, which should be recalled to finalize theresonant tank design. Fig. 7 shows the holdup time gain con-straint and the high-efficiency operation constraint. The finaloptimal design point is located at the intersection of the threesurfaces, which is where all requirements can be satisfied. If thisdesign point moves up along the boundary line of the peak gainsurface and the high-efficiency constraint surface, the voltageconversion range is enlarged and the efficiency of the converter

HUANG et al.: HIGH-FREQUENCY HIGH-EFFICIENCY CLL RESONANT CONVERTERS WITH SRs 3467

Fig. 8. Circuit stresses at different values of Ln. (a) Primary-side peakcurrent. (b) Peak voltage of resonant capacitor.

Fig. 9. Design procedure of the CLL resonant converters.

is kept the same. If this occurs, the impacts of design pointselection should be studied further.

During the holdup time operation, the primary-side peakcurrent is normalized by the factor Po/0.5Vin; this current isplotted in Fig. 8(a). The maximum voltage gain is achievedclose to the parallel resonant frequency f02. The primary-sidepeak current at f02 increases as Ln increases. If Ln � 1, basedon (3) and (7), it can be derived that Leq ≈ L2 and f02 ≈f0/

√Ln. The frequency operation range during the holdup time

also increases.In one switching cycle, the energy transfer period is close to

T0 due to the nature of resonance. If the switching frequencymoves farther from the series resonant frequency, the effectiveenergy transfer duty cycle is reduced, which results in a highercurrent. Roughly, the peak current is inversely proportional tof02 or proportional to

√Ln.

Normalized by the factor 0.5Vin, Fig. 8(b) shows how thepeak voltage of the resonant capacitor changes during theholdup time operation. The peak voltage decreases as Ln

increases.Based on (4)–(7), we know that C1 is proportional to Ln.

Since the peak current is roughly proportional to√

Ln duringthe holdup time, the increase in the capacitance is greater thanthe increase in the current going through the capacitor. Thus, thevoltage stress decreases.

Normally, a narrow frequency operation range and low cur-rent stress are preferred. Thus, the black dot in Fig. 7, where Ln

equals 17 and Q equals 0.153, is chosen as the optimal designpoint. According to (2)–(8), the resonant tank parameters canbe calculated as L1 = 74.06 μH, L2 = 4.35 μH, and C1 =5.09 nF. Based on (11), the transformer turn ratio is 18 : 1. Theoptimal design procedure is summarized in Fig. 9.

Fig. 10. LLC resonant converter with integrated Lm.

Fig. 11. LLC resonant converter transformer. (a) Transformer structure.(b) FEA simulation result.

IV. TRANSFORMER DESIGN INVESTIGATION

For the CLL resonant converter transformer design, twofactors need to be taken into consideration. First, the mag-netizing inductance of the transformer should be designed tobe as high as possible. Second, the leakage inductance of thetransformer could be utilized as Lr. The basic configurationof the transformer is as follows: Litz wires are utilized asthe primary-side winding for their ability to reduce the skineffect caused by high-frequency current. Printed circuit board(PCB) winding is utilized on the secondary side for the easyconnection of high-current devices.

As shown in Fig. 10, for a conventional LLC resonantconverter, Lm is usually integrated into the transformer withthe insertion of an air gap. A discrete inductor is required forLr. However, the air gap will cause a high eddy current in thePCB windings and, hence, high winding loss [16].

The LLC resonant converter transformer structure is shownin Fig. 11(a), where the rounded winding is the primary-sidelitz wire and the center two plates are the secondary-side PCBwinding. The primary-side and secondary-side windings areinterleaved for lower ac winding loss. The thickness of the coreis 2 mm (from the inner side to the outer side), and the windowarea of the core is 50 mm2. The width of the PCB copper is7 mm, and it has a weight of 4 oz. The diameter of the litzwire is 0.5 mm (AWG 24). We chose Maxwell 2-D-based finiteelement analysis (FEA) to investigate the winding loss. Thesecondary PCB winding loss is 2.89 W (23.1% of the systemloss) for a 250-W LLC transformer with an air gap. Fig. 11(b)shows a large eddy current that occurs at the edges of the copperplates near the air gaps.

For the CLL resonant converter transformer design, thereis no need to utilize magnetizing inductance (as shown inFig. 1). Thus, air gaps and the associated fringing effect canbe eliminated. The optimal design of the separate L1 for smallsize and high efficiency can be achieved easily. The next issue

3468 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 2011

Fig. 12. CLL resonant converter transformer without interleaving windings.(a) Transformer structure. (b) FEA simulation result.

Fig. 13. CLL resonant converter transformer with interleaving windings.(a) Transformer structure. (b) FEA simulation result.

is determining how to integrate L2 into the transformer withoutsuffering too much loss.

Fig. 12(a) shows the transformer structure without interleav-ing, and Fig. 12(b) shows the FEA simulation results. Withoutan interleaving structure, the secondary PCB conduction loss is2.82 W (22.6% of the system loss), and the leakage inductanceis 4.14 μH.

The transformer structure with interleaving is shown inFig. 13(a), and the FEA simulation results are shown inFig. 13(b). The conduction loss is 1.59 W (12.7% of the wholesystem loss), and the leakage inductance is 1.94 μH. The inter-leaving structure of the transformer makes the magnetomotiveforce (MMF) more evenly distributed but with a significantreduction of the leakage inductance.

The leakage inductance is mainly generated by the mag-netic energy stored in the space between the primary-sideand secondary-side windings. In an interleaving structure, theenergy is small due to low MMF. To increase the leakage induc-tance, a magnetic shunt with higher permeability is adopted. Aferrite polymer composite (FPC) film with μr = 9 is used as amagnetic shunt.

Fig. 14(a) shows the transformer with an interleaving struc-ture and a magnetic shunt. The FEA simulation results areshown in Fig. 14(b). The two gray bars between the primary-side and secondary-side windings represent the magnetic shuntlayers. The conduction loss of the secondary PCB winding is1.74 W (13.9% of the system loss), and the leakage inductanceis 3.89 μH. The leakage inductance of the transformer withmagnetic shunts is double that of the transformer without mag-netic shunts. The magnetic shunt layers attract more leakageflux. However, due to limited permeability, the induced leakageflux bends slightly. The leakage flux induces an eddy currentat the edge of the copper plates. Fortunately, the leakage fluxis very low. Thus, only a 0.15-W loss is added, which isacceptable for a 250-W converter.

Fig. 14. CLL resonant converter transformer with interleaving windings andmagnetic shunt. (a) Transformer structure. (b) FEA simulation result.

Based on the aforementioned analysis and comparison, theproposed transformer structure is very suitable for the CLLresonant converter. For the planar transformer, it may not befavorable to integrate the magnetizing inductance due to thesevere fringing effect. However, the leakage inductance can beeasily integrated without an apparent sacrifice in performance.The proposed CLL resonant converter can fully utilize theoptimal integration solution of the magnetic components, whichis an inherent merit of this topology.

V. SYNCHRONOUS RECTIFICATION DRIVING SCHEME

For conventional LLC resonant converters, it is not easy toapply a current-drive SR. Otherwise, discrete magnetic compo-nents should be applied. Unlike existing LLC resonant convert-ers, the magnetizing inductance of the proposed CLL resonantconverter is very large. The impact of the phase mismatchbetween the primary-side and secondary-side currents of thetransformer can be ignored. Thus, the transformer’s primary-side current can be utilized directly to drive the SR. Fig. 15(a)shows a diagram of the SR driving scheme, and Fig. 15(b)shows the schematic of the SR driving circuit. A CT is usedto sense the primary-side current, and comparators and simpleperipheral circuits are utilized as Schmitt triggers.

Unlike the conventional LLC resonant converter, there is noconflict between the current-driven SR and the integration ofmagnetic components. This is another inherent benefit of theproposed CLL resonant converter.

VI. EXPERIMENTAL RESULTS

A 250-W 800-kHz 400-V/12-V CLL resonant converterprototype is built to verify the theoretical analysis and the pro-posed design strategies. The resonant parameters are designedas follows: L1 = 73 μH, L2 = 4.4 μH, and C1 = 5 nF. Thetransformer turn ratio is 18 : 1 : 1. The core material is 3F45.L2 is integrated with the transformer. The relative permeabilityof the FPC is nine. For L1 [17], an RM8/ILP with 3F45 ischosen, and 24-turn AWG-26 litz wires are used. The powerdensity of the prototype is 94.6 W/in3. The part number of theprimary-side and secondary-side devices are STB12NM50FDand BSC014N03MSG, respectively.

Fig. 16(a) shows the experimental results of the CLL reso-nant converter at a no-load condition. ZVS is achieved duringthe dead time between the marked lines. Vds_s1 and Vds_s2 arethe drain–source voltages of S1 and S2, respectively. Vgs_s1 andVgs_s2 are the gate–source voltages of S1 and S2, respectively.

HUANG et al.: HIGH-FREQUENCY HIGH-EFFICIENCY CLL RESONANT CONVERTERS WITH SRs 3469

Fig. 15. CLL resonant converter with SR driving scheme. (a) CLL resonant converter. (b) Schematic of SR driving scheme.

Fig. 16. Experimental waveforms of prototype. (a) 400 V/12 V, no load.(b) 400 V/12 V, 250-W full load.

When the drain–source voltage drops to zero, the gate signalstarts to drive. The dead time is 160 ns, and the turnoff currentis around 0.68 A.

Fig. 16(b) shows the experimental results of the CLL res-onant converter at the full-load condition. VQ2 is the drivingsignal of Q2. VdsQ2 represents the drain–source voltage ofQ2. The primary-side current iL2 has the same shape as thesecondary-side current, but it has a different amplitude due tothe turn ratio. iL2 is in a sinusoidal shape. As the dotted lineindicates, VdsQ2 begins to rise just at the zero-cross point ofthe sinusoidal current. Hence, ZCS is achieved. It can also beobserved that the SR body-diode conduction time is almosteliminated.

The experimental efficiency curve of the prototype is shownin Fig. 17. The efficiency at a half load is 96.7%, and at a fullload, it is 96.1%. The holdup time capacitor is 56 μF for a250-W converter, and the input voltage range is 415–220 V. Thevoltage ripple is around ±15 V. Based on this voltage ripple, theswitching frequency range is 725–900 kHz. Based on calcula-tion, the efficiency at 725, 800, and 900 kHz (fixed frequency)is 95.9%, 96.3%, and 95.7%, respectively. As the frequencyvariation is not significant, the efficiency of the converter willchange little. The proposed optimal design procedure is valid.

A detailed loss breakdown under full-load conditions isshown in Table I.

VII. CONCLUSION

This paper has proposed a high-frequency high-efficiencyCLL resonant converter. The characteristics of the CLL res-onant converter are analyzed, and the operation regions of

Fig. 17. Measured efficiency curve for the constructed CLL resonantconverter.

TABLE ILOSS BREAKDOWN OF THE HARDWARE UNDER FULL LOAD

the CLL resonant converter are discussed. Recognizing thatdead time is a critical factor that influences the entire systemdesign and using thorough investigation, an optimal designmethodology is proposed to achieve high efficiency over awide load range. An optimal transformer structure for the CLLresonant converter is proposed to achieve low winding loss andto have the capability of magnetic integration, and an easilyimplemented current-type SR driving scheme is proposed toachieve low SR losses. An 800-kHz 250-W CLL resonantconverter prototype is built to verify the benefits of the proposedCLL resonant converters, and over a 96% efficiency is achievedfor the wide load conditions of interest. The proposed CLLresonant converter is a good candidate for next-generation high-frequency high-efficiency high-power-density power supplies.

3470 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 2011

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Daocheng Huang received the B.S. and M.S. de-grees from the Huazhong University of Science andTechnology, Wuhan, China. He is currently workingtoward the Ph.D. degree at Virginia Polytech-nic Institute and State University (Virginia Tech),Blacksburg.

His research interests include high-frequencypower conversion, soft switching techniques, mag-netic design, passive integration, distributed powersystems, and telecom power conversion techniques.

Dianbo Fu (M’09) received the B.S. degree fromthe Huazhong University of Science and Technology,Wuhan, China, and the M.S. and Ph.D. degrees fromVirginia Polytechnic Institute and State University(Virginia Tech), Blacksburg.

Since 2010, he has been with Huawei Tech-nologies, Plano, TX, where he has been engagedin product design, research, and development. Heis the holder of two U.S. patents and has threeU.S. patents pending. His research interests includehigh-frequency power conversion, soft switching

techniques, magnetic design, electromagnetic interference, distributed powersystems, and telecom power conversion techniques.

Fred C. Lee (S’72–M’74–SM’87–F’90) receivedthe B.S. degree in electrical engineering from theNational Cheng Kung University, Tainan, Taiwan,in 1968, the M.S. and Ph.D. degrees in electricalengineering from Duke University, Durham, NC, in1972 and 1974, respectively.

He is a University Distinguished Professor withVirginia Polytechnic Institute and State University(Virginia Tech), Blacksburg. He directs the Centerfor Power Electronics Systems, a National ScienceFoundation engineering research center. He is the

holder of 35 U.S. patents and has published over 200 journal articles and morethan 500 technical papers in conference proceedings. His research interests in-clude high-frequency power conversion, distributed power systems, electronicspackaging, and modeling and control.

Pengju Kong (M’08) received the B.S.E.E. andPh.D. degrees from Tsinghua University, Beijing,China, in 2003 and 2009, respectively.

He is currently a Postdoctoral Associate withthe Center for Power Electronics Systems, VirginiaPolytechnic Institute and State University (VirginiaTech), Blacksburg. His research interests includeelectromagnetic interference/electromagnetic com-patibility in power electronics systems, magnetics,and micro grid.