High-frequency Current-transformer Based Auxiliary Power ......Current-transformer Based...

High-frequency Current-transformer Based Auxiliary

Power Supply for SiC-based Medium Voltage

Converter Systems

Ning Yan

Thesis submitted to the faculty of the

Virginia Polytechnic Institute and State University

in partial fulfillment of the requirements for the degree of

Master of Science

In

Electrical Engineering

Dong Dong, Chair

Rolando Burgos

Dan M. Sable

September 1, 2020

Blacksburg

Keywords: auxiliary power supply, resonant converter, high frequency, GaN devices,

ZVS, partial discharge, common-mode coupling capacitor

Copyright 2020, Ning Yan

Current-transformer Based High-frequency Auxiliary Power Supply for

SiC-based Medium Voltage Converter Systems

Ning Yan

(ABSTRACT)

Auxiliary power supply (APS) plays a key role in ensuring the safe operation of the

main circuit elements including gate drivers, sensors, controllers, etc. in medium voltage

(MV) silicon carbide (SiC)-based converter systems. Such a converter requires APS to

have high insulation capability, low common-mode coupling capacitance ( ), and high-

power density. Furthermore, considering the lifetime and simplicity of the auxiliary power

supply system design in the MV converter, partial discharge (PD) free and multi-load

driving ability are the additional two factors that need to be addressed in the design.

However, today’s state-of-the-art products have either low power rating or bulky designs,

which does not satisfy the demands. To improve the current designs, this thesis presents a

1 MHz isolated APS design using gallium nitride (GaN) devices with MV insulation

reinforcement.

By adopting LCCL-LC resonant topology, the proposed APS is able to supply multiple

loads simultaneously and realize zero voltage switching (ZVS) at any load conditions.

Since high reliability under faulty load conditions is also an important feature for APS in

MV converter, the secondary side circuit of APS is designed as a regulated stage. To

achieve MV insulation (> 20 kV) as well as low value (< 5 pF), a current-based

transformer with a single turn structure using MV insulation wire is designed. Furthermore,

by introducing different insulated materials and shielding structures, the APS is capable to

achieve different partial discharge inception voltages (PDIV). In this thesis, the transformer

design, resonant converter design, and insulation strategies will be detailly explained and

verified by experiment results.

Overall, this proposed APS is capable to supply multiple loads simultaneously with a

maximum power of 120 W for the sending side and 20 W for each receiving side in a

compact form factor. ZVS can be realized regardless of load conditions. Based on different

insulation materials, two different receiving sides were built. Both of them can achieve a

breakdown voltage of over 20 kV. The air-insulated solution can achieve a PDIV of 6 kV

with of 1.2 pF. The silicone-insulated solution can achieve a PDIV of 17 kV with

of 3.9 pF.

Current-transformer Based High-frequency Auxiliary Power Supply for

SiC-based Medium Voltage Converter Systems

Ning Yan

(GENERAL AUDIENCE ABSTRACT)

Recently, 10 kV silicon carbide (SiC) MOSFET receives strong attention for medium

voltage applications. Asit can switch at very high speed, e.g. > 50 V/ns, the converter system

can operate at higher switching frequency condition with very small switching losses

compared to silicon (Si) IGBT [8]. However, the fast dv/dt noise also creates the common

mode current via coupling capacitors distributed inside the converter system, thereby

introducing lots of electromagnetic interference (EMI) issues. Such issues typically occur

within the gate driver power supplies due to the high dv/dt noises across the input and output

of the supply. Therefore, the ultra-small coupling capacitor (<5 pF) of a gate driver power

supply is strongly desired.[37]

To satisfy the APS demands for high power modular converter system, a solution is

proposed in this thesis. This work investigates the design of 1 MHz isolated APS using

gallium nitride (GaN) devices with medium voltage insulation reinforcement. By

increasing switching frequency, the overall converter size could be reduced dramatically.

To achieve a low 𝐶𝑐𝑚 value and medium voltage insulation of the system, a current-based

transformer with a single turn on the sending side is designed. By adopting LCCL-LC

resonant topology, a current source is formed as the output of sending side circuity, so it

can drive multiple loads importantly with a maximum of 120 W. At the same time, ZVS

v

can use realized with different load conditions. The receiving side is a regulated stage,

so the output voltage can be easily adjusted and it can operate in a load fault condition.

Different insulation solutions will be introduced and their effect on 𝐶𝑐𝑚 will be discussed.

To further reduce 𝐶𝐶𝑚 , shielding will be introduced. Overall, this proposed APS can

achieve a breakdown voltage of over 20 kV and PDIV up to 16.6 kV with 𝐶𝐶𝑚 < 5 𝑝𝐹.

Besides, multi-load driving ability is able to achieve with a maximum of 120 W. ZVS can

be realized. In the end, the experiment results will be provided.

vi

Acknowledgements

First and foremost, I would like to thank my advisor, Dr. Dong Dong, for the opportunity

to be his master student. His expertise, patient, and insight guided me through my research

and helped me to grow. He gave me many suggestions based on his industry experience,

so I have a better understanding of how my research is related to industrial demand, which

is one of the most important things I learned from him. I also would like to thank Dr.

Rolando Burgos for his steady support and guidance in the past two years. Additionally, I

greatly appreciate Dr. Dan M. Sable and Dr. Jason Lai for being my committee members.

My research would not have been done without the support of all CPES staff. Many

thanks to Ms. Trish Rose, Mr. David Gilham, Ms. Audri Cunningham, Mr. Dennis Grove,

Ms. Na Ren, Mr. Matthew Scanland, Ms. Yan Sun, Ms. Marianne Hawthorne, Ms. Teresa

Shaw, Ms. Linda Long, and Ms. Lauren Shutt.

Furthermore, I would like to express the gratitude to my colleagues and friends—He

Song, Xiang Lin, Zheqing Li, Chunyang Zhao, Xin Lou, Dr. Li Cheng, Junjie Feng, Boyan

Wang, Ruizhe Zhang, Xuan Liu, Jiayu Li, Jiangmin Wang, Donghan Hu, Yuan Li, and

Tiancheng Ying. They helped me with research and supported me in life. I would also like

to thank my team members--Keyao Sun, Jianghui Yu, Slavko Mocevic, Yue Xu, Joshua

Stewart, Yu Rong, Dr. Igor Cvetkovic, and Dr. Jun Wang. I am really glad to work in such

a big team and had a great teamwork experience.

Finally, a huge thank to my family. Without their support and encouragement, I would

never get close to my dream.

This research work was primarily supported by Advanced Research Projects Agency-

Energy (ARPA-E). Last but not least, I would like to say thanks to everyone who helped

me along the way.

vii

Table of Contents

Chapter 1: Introduction .................................................................................................... 1

1.1 Background Information and Motivation ........................................................... 1

1.2 State-of-the-Art Architectures ........................................................................... 3

1.2.1 Transformer-based Designs ........................................................................ 3

1.2.2 Non-transformer-based Designs ................................................................. 9

1.3 Thesis Outline ................................................................................................. 11

Chapter 2: Transformer Modeling and Design ............................................................... 12

2.1 Introduction ..................................................................................................... 12

2.2 Maximum Allowable Voltage Modeling.......................................................... 13

2.3 Modeling ................................................................................................ 15

2.4

Transformer Design......................................................................................... 23

2.5 Test Result ...................................................................................................... 35

2.6 Summary ......................................................................................................... 36

Chapter 3: Circuit Design .............................................................................................. 38

3.1 Introduction ..................................................................................................... 38

3.2 Topologies Comparisons ................................................................................. 38

3.3 LCCL-LC Operation Principle ........................................................................ 40

3.4 LCCL-LC Converter Design ........................................................................... 45

3.4.1 Controller Design ..................................................................................... 45

3.4.2 ZVS Analysis ........................................................................................... 46

3.5 PCB Layout Design ......................................................................................... 59

3.6 Hardware Prototype and Test Results .............................................................. 61

3.6.1 Steady-State Responses ............................................................................ 64

3.6.2 Transient Responses ................................................................................. 67

3.6.3 ZVS Verification ...................................................................................... 69

3.6.1 Thermal Test ............................................................................................ 70

3.7 Summary ......................................................................................................... 72

Chapter 4: Insulation Design ......................................................................................... 73

4.1 Introduction ..................................................................................................... 73

4.2 Air-Insulated Solutions .................................................................................... 73

4.2.1 Solution I: Basic Design ........................................................................... 73

viii

4.2.2 Solution II: HV Conductive Shield ........................................................... 74

4.2.3 Solution III: Conductive Shield with Floating Potential ............................ 76

4.2.4 Solution IV: Double Shields ..................................................................... 79

4.3 Silicone-Insulated Solutions ............................................................................ 81

4.3.1 Solution V: Partially Potted Core ............................................................. 82

4.3.2 Solution VI: Potted Core with Stress Cone Terminals............................... 84

4.3.3 Solution VII: Fully Potted Transformer .................................................... 85

4.3.4 Solution VIII: Mixed Dielectric Materials ................................................ 86

4.4 Test Results ..................................................................................................... 88

4.4.1 Manufacturing Process of Silicone-insulated Solution .............................. 88

4.4.2 Insulation Test Verification ...................................................................... 94

4.4.3 Thermal Test Verification ........................................................................ 97

4.4.4 Verification...................................................................................... 97

4.5 Summary ......................................................................................................... 99

Chapter 5: System Test Results ................................................................................... 101

5.1 Test With WPT ............................................................................................. 101

5.2 Tests in MV Converters................................................................................. 104

Chapter 6: Conclusion ................................................................................................. 108

References ................................................................................................................... 110

ix

List of Figures

Figure 1. Main common mode current conducted path in half bridge inverter .................. 2

Figure 2. Block diagram for voltage-transformer-based design on single PCB with labels

insulation path ................................................................................................................. 4

Figure 3.Circuit schematic of active clamp flyback converter .......................................... 4

Figure 4.Circuit schematic of LLC resonant converter ..................................................... 5

Figure 5. Circuit schematic of flyback converter .............................................................. 6

Figure 6. Block diagram for voltage-transformer-based design on two PCBs with labeled

insulation path ................................................................................................................. 7

Figure 7. Circuit schematic of CLLC resonant converter ................................................. 7

Figure 8. Circuit schematic of single active bridge ........................................................... 7

Figure 9. Block diagram for current-transformer-based design on two PCBs ................... 8

Figure 10. Circuit schematic of LCCL-LC resonant converter ......................................... 8

Figure 11. State-of-the-art architectures with blue dots indicated as voltage transformer-

based single PCB solution, orange dots indicated as voltage transformer-based two PCBs

solution, green dots indicated as current transformer-based solution and grey dots

indicated as non-transformer-based solution .................................................................. 10

Figure 12. 3D view of proposed transformer design structure ........................................ 12

Figure 13. Simplified structure of proposed transformer for maximum allowable voltage

modeling ....................................................................................................................... 14

Figure 14. The maximum allowable voltage with increasing transformer inner radius for

concentric cylinder structure .......................................................................................... 14

x

Figure 15. Side view of proposed transformer structure without insulated layer of primary

side winding .................................................................................................................. 16

Figure 16. The coupling capacitors between segments of and ................................ 18

Figure 17. The coupling capacitors between segments of and ............................... 18

Figure 18. The coupling capacitors between segments and ................................... 19

Figure 19. The coupling capacitors between segment and ...................................... 20

Figure 20. model verification................................................................................... 21

Figure 21. Effect of transformer inner radius on with different number of turns ....... 22

Figure 22. Effect of transformer height on with different number of turns ............... 22

Figure 23. Effect of transformer outer radius on with different number of turns ........ 23

Figure 24. Core loss density of P51(labeled in blue), P52 (labeled in orange), P53(labeled

in gray), ML91S (labeled in yellow), ML95S (labeled in green) and P61(labeled in red).

...................................................................................................................................... 25

Figure 25. Current rating for equivalent AWG ............................................................... 26

Figure 26. Transformer volume with different heights ................................................... 27

Figure 27. Calculated with turn numbers from 1 to 10 under different height

conditions ...................................................................................................................... 28

Figure 28. (plotted in blue) and (plotted in orange) values under switching

frequency of 500 kHz .................................................................................................... 29


frequency of 600 kHz .................................................................................................... 30

xi


frequency of 700 kHz .................................................................................................... 30


frequency of 800 kHz .................................................................................................... 31


frequency of 900 kHz. All suitable options are converted by green area. ........................ 31


frequency of 1 MHz ...................................................................................................... 32

Figure 34. Total power loss for 5 pair of solutions ......................................................... 35

Figure 35. Hardware prototype of designed transformer with labeled dimensions .......... 35

Figure 36. Measurement result of for designed transformer ..................................... 36

Figure 37. Flowchart of transformer design steps ........................................................... 37

Figure 38. Constant current output from a voltage source connected in series with (a) an

inductor (b) a capacitor d ............................................................................................... 39

Figure 39. Current source mechanism of type A and type B circuits .............................. 40

Figure 40. CLCL-LC resonant converter ....................................................................... 40

Figure 41. LCCL-LC operation condition in mode 1 with labeled current direction ....... 41






xii

Figure 47. Voltage and current waveforms for LCCL-LC topology during steady state

operation ....................................................................................................................... 44

Figure 48. LCCL-LC resonant converter with hysteresis controller................................ 46

Figure 49. Hysteresis controller schematics ................................................................... 46

Figure 50. Block diagram of proposed APS with series connected receiving side .......... 48

Figure 51. Winding configuration (a) I (b) II. ................................................................ 48

Figure 52. Total impedance with different wire self-inductance ..................................... 49

Figure 53. Simulation result for non-ZVS case caused by large wire self-inductance ..... 49

Figure 54. Diagram for loop inductance calculation ....................................................... 50

Figure 55. Simplified circuit schematic for compensation network design with multiple

loads.............................................................................................................................. 51

Figure 56. Voltage source mechanism from current source. (a) original circuit (b)

equivalent circuit ........................................................................................................... 52

Figure 57. Equivalent circuit for transition compensation method I ............................... 52

Figure 58. Input impedance of traditional compensation method I ................................. 52

Figure 59. Time domain verification with transitional compensation method I with

......................................................................................................................... 53

Figure 60. Equivalent circuit for traditional compensation method II ............................. 53

Figure 61. Input impedance of traditional compensation method II ................................ 54

Figure 62. Time domain verification with transitional compensation method II with

......................................................................................................................... 54

Figure 63. Equivalent circuit for total impedance analysis ............................................. 55

Figure 64. Equivalent circuits of (a). case 1 (b). case 2 and (c). case 3 ........................... 56

xiii

Figure 65. Total input impedance for three analyzed cases............................................. 56

Figure 66. Equivalent circuit for proposed compensation model .................................... 57

Figure 67. Input impedance for proposed compensation method ................................... 58

Figure 68. Time domain verifications with proposed compensation method for .. 59

Figure 69 Time domain verification with proposed compensation method for ..... 59

Figure 70. PCB layout for single device condition ......................................................... 60

Figure 71. PCB layout for half-bridge configuration using parallel devices. (a) top view

(b) bottom view (c) side view with labeled power loop [49] .......................................... 61

Figure 72. PCB’s (a). top side (b) bottom side for diode layer. ....................................... 62

Figure 73. PCB’s (a) top side (b) bottom side for control layer. ..................................... 63

Figure 74. Hardware prototype of assembled receiving side .......................................... 63

Figure 75. Hardware prototype of sending side .............................................................. 63

Figure 76. Half-bridge modular design’s top view (top) and bottome view with assembled

heatsink and fan ............................................................................................................ 64

Figure 77. Current source waveforms under light load condition ................................... 65

Figure 78. Current source waveform under heavy load condition ................................... 65

Figure 79. Steady-state waveform of output voltages measured in DC mode and

controller gate signals .................................................................................................... 66

Figure 80. Steady-state waveform of output voltages measured in AC mode and

controller gate signals .................................................................................................... 66

Figure 81. Output voltages of four loads under steady-state operation............................ 67

Figure 82. System configuration with one sending side and four receiving sides ............ 67

Figure 83. Startup result for four load condition ............................................................ 68

xiv

Figure 84. Short-circuit response ................................................................................... 68

Figure 85. Open-circuit response ................................................................................... 69

Figure 86. Experiment results for non-ZVS condition when .................... 69

Figure 87. ZVS verification for single load condition with the active control switch (a).

turns off (b) turns on ...................................................................................................... 70

Figure 88. ZVS verification for four loads condition with the active control switch (a).

turns off (b) turns on ...................................................................................................... 70

Figure 89. Thermal test result for single receiving side with output power of 20 W. ...... 71

Figure 90. Thermal test result for four receiving sides with total output power of 80 W . 71

Figure 91. Designed transformer with detail labeled ...................................................... 74

Figure 92. FEM simulation result of plane 1 with 5 kV excitation.................................. 74

Figure 93. CAD model of isolated transformer with high voltage shield on insulated wire

...................................................................................................................................... 76

Figure 94. FEM simulation result of plane 2 under 5 kV excitation ................................ 76

Figure 95. FEM simulation result of plane 3 under 5 kV excitation ................................ 76

Figure 96. CAD model of isolated transformer with a floating potential shield .............. 77

Figure 97. FEM simulation result of (a). plane 4 (b) plane 5 with .................. 78

Figure 98. FEM simulation result of (a). plane 4 (b) plane 5 with .................. 79

Figure 99. CAD model of isolated transformer with two fixed potential shields ............. 79

Figure 100. FEM simulation results of (a). plane 6 (b). plane 7 under 5 kV excitation ... 80

Figure 101. CAD model of isolated transformer with partially potted structure. ............. 83

Figure 102. FEM simulation result of (a). plane 8 (b) plane 9 under 15 kV excitation .... 84

xv

Figure 103. CAD model of isolated transformer with stress cone shape as potting

terminals ....................................................................................................................... 84

Figure 104. FEM simulation result of plane 10 under 15 kV excitation .......................... 85

Figure 105. CAD model of fully potted isolated transformer.......................................... 86

Figure 106. FEM simulation result of plane 11 under 15 kV excitation .......................... 86

Figure 107. CAD model of isolated transformer with mixed dielectric materials ............ 87

Figure 108. FEM simulation result of (a). plane 12 (b). plane 13 under 15 kV excitation87

Figure 109. 3D printed fixtures for silicone-insulated design including (a). bottom

supporter (b). top supporter and (c) potting housing ....................................................... 89

Figure 110. Receiving side hardware in 3D printed fixture with RTV applied at terminals

...................................................................................................................................... 90

Figure 111. Mixing material in vacuum chamber ........................................................... 90

Figure 112. Mixing material (a) before vacuum (b) after vacuum .................................. 91

Figure 113. Sample with small amount of potting materiel ............................................ 91

Figure 114. Potted sample in vacuum chamber .............................................................. 92

Figure 115. Potted sample in oven ................................................................................. 92

Figure 116. Hardware prototype of potted receiving side circuity .................................. 93

Figure 117. APS setup for multiple potted receiving side circuitries .............................. 93

Figure 118. PD Test Setup ............................................................................................. 94

Figure 119. Setup configuration for PD test ................................................................... 94

Figure 120. PDIV for air-insulated solution measured by HFCT .................................... 95

Figure 121. PDIV for air-insulated solution measured by PD detector ........................... 95

Figure 122. PDIV for silicone-insulated solution measured by HFCT ............................ 96

xvi

Figure 123.PDIV for silicone-insulated solution measured by PD detector .................... 96

Figure 124. Partial discharge condition for silicone-insulated solution with 20.4 kV

excitation....................................................................................................................... 96

Figure 125.Thermal test result of potted receiving side circuitry .................................... 97

Figure 126. result for air-insulated design with the completed receiving side ........... 98

Figure 127. result for silicone-insulated design with transformer only ..................... 98

Figure 128. result for silicone-insulated design with completed receiving side ......... 99

Figure 129. Block diagram of auxiliary power system ................................................. 101

Figure 130. Auxiliary power system’s startup performance ......................................... 102

Figure 131. Auxiliary power system’s turn-off performance ........................................ 102

Figure 132. Auxiliary power system’s short-circuit response ....................................... 103

Figure 133. Auxiliary power system’s open-circuit response ....................................... 103

Figure 134. Buck test configuration ............................................................................. 104

Figure 135. Hardware setup for buck test ..................................................................... 104

Figure 136. Operating waveform of 6 kV buck configuration ...................................... 105

Figure 137. CPES designed sensor with integrated receiving side circuit (a) top side (b)

bottom side of design sensor ........................................................................................ 106

Figure 138. CPES designed gate driver with integrated receiving side circuit .............. 106

Figure 139. Hardware setup of APS in PEBB .............................................................. 106

Figure 140. Primary side thermal result in PEBB system ............................................. 107

Figure 141. Secondary side thermal result in PEBB system ......................................... 107

xvii

List of Tables

Table 1. Design Specification for the Isolated Auxiliary Power Supply ........................... 2

Table 2. Comparisons of State-of-the-Art Features ........................................................ 10

Table 3. Transformer Design Specifications .................................................................. 24

Table 4. Litz Wire Parameters ....................................................................................... 25

Table 5. Summary of Available Solutions for Frequency of 900 kHz and 1 MHz .......... 32

Table 6. GaN Device Candidates ................................................................................... 34

Table 7 Design Parameters for LCCL-LC Resonant Converter ...................................... 62

Table 8. Summary of Insulation Design with Air ........................................................... 81

Table 9. Potting Materials Parameters ........................................................................... 82

Table 10. Summary of Insulation Design with Silicone.................................................. 88

1

Chapter 1

Introduction

1.1 Background Information and Motivation

Recently, the demand for power electronics in medium voltage (MV) applications is

continuously increasing. It has been widely used in electric transportations [1-3], e.g.

electrical ships, renewable energy systems, e.g. solar-PV system [3][4], data centers [1][5],

etc. However, those applications have high requirements on power converter’s size, power

density, efficiency, and reliability. [6] Thus, the traditional silicon (Si) IGBT-based

converter cannot meet the requirements anymore and a new semiconductor device with

high power processing capability is desired. [7]

As a promising candidate for MV applications, 10 kV SiC MOSFET receives strong

attention as it has higher breakdown voltage, higher operating temperature, faster-switching

speed, e.g. > 50 V/ns, and lower losses compared to Si IGBT [8]. Due to high

blocking voltage, SiC devices enable a few switches in MV converter, which leads to a

simpler control scheme. High allows the converter to operate with the high switching

frequency, which can improve the MV converter’s power density. However, these advanced

device features bring additional design challenges to other circuit components, such as gate

driver (GD) and auxiliary power supply (APS).

The isolated APS is a critical component to ensure device safe operation. Qualified

isolation level and constant output voltages under different conditions are the key features

for APS. Besides medium insulation voltage, medium partial discharge inception voltage

(PDIV) is also required with the consideration of APS’s lifetime [9] and insulation design

of a modular converter. Due to the fast dv/dt caused by the device, a common mode current

via coupling capacitors was created and distributed inside the converter system, which

2

introduces many electromagnetic interference (EMI) issues.[10] As shown in Fig. 1, such

an issue typically occurs through the gate driver power supply (GDPS) because its common-

mode coupling capacitor ( ) value is much larger than the value caused by signal

transmission. Therefore, an ultra-small value (< 5 pF) is strongly desired in APS design.

Finally, considering the future integration purpose, complete auxiliary power system design

inside MV converter, and future high current applications, a multi-channel, high output

power APS design in a compact form factor, which is the most challenging aspect, is

preferred. Overall, a multi-channel APS with high insulation capability, low , high

output power, and small dimensions are required. The complete APS specifications are

listed in Table I.

Figure 1. Main common mode current conducted path in half-bridge inverter

Table 1. Design Specification for the Isolated Auxiliary Power Supply

Parameters Values

Input voltage ( ) 48 V

Output voltage ( ) 24 V

3

Max. receiving side output power ( ) 20 W

Max. sending side output power ( ) 120 W

Insulation Voltage ( ) 20 kV

Partial discharge inception voltage ( ) 5 kV-15 kV

Common-mode coupling capacitance ( ) < 5 pF

Volume < 3

1.2 State-of-the-Art Architectures

1.2.1 Transformer-based Designs

Insulation capability is always the priority to consider for APS design. Based on

insulation methods, today’s state-of-the-art architectures fall into two categories:

transformer-based designs and non-transformer-based designs. Transformer appears as the

most common isolation component in APS design since it provides galvanic isolation and

at the same time, it is able to alternate voltage or current levels with high efficiency. For

transformer-based designs, there are three subcategories: the voltage-based-transformer

design on a single PCB, voltage-based-transformer designs on two PCBs, and current-

based-transformer designs on two PCBs [11].

Figure 2 shows the single PCB solution for voltage-transformer-based design. For this

structure, there are generally two different designs. The first type of design has an extremely

small converter size. To achieve so, the APS is designed as a GaN-based dc/dc converter

with the switching frequency in the Megahertz range. From a topology point of view, simple

circuit structure, such as active clamp flyback and LLC shown in Fig. 3 and Fig.4, is favored

by this design as it requires few numbers components and can achieve high efficiency. [12-

14] Additionally, multiple outputs can be easily achieved with less space required, but due

to the small converter size, the number of outputs is limited. Besides this, a small converter

size brings insulation design challenge. To maintain insulation capability with limited core

4

size, [12-15] use PCB embedded transformer. In this case, FR4 is the insulation material.

Although the voltage strength of FR4 is high, considering the overall size and pollution

condition of the PCB surface, the insulation voltage for this design is limited to a lower MV

level, such as 3 kV. Another drawback for the embedded transformer solution is value

is relatively high. The designs in [12-15] have value varied from 2 pF to 10 pF. Finally,

considering the overall thermal performance and converter size, the output power for the

transformer embedded solution is only 2 W.

Figure 2. Block diagram for voltage-transformer-based design on single PCB with labels insulation path

Figure 3.Circuit schematic of active clamp flyback converter

Primary

side

Circuit

Secondary

side

Circuit

PCB Clearance/

Creepage

winding terminals

Cd

Vin Vo

Co Ro

Lr

CrS2

S1

5

Figure 4.Circuit schematic of LLC resonant converter

The second type of single PCB design has a transformer on the surface of the PCB with

the exact layout shown in Fig. 2. In most designs, the air is the main insulation media, so

the APS insulation level mostly relies on transformer size. Thus, due to the low voltage

strength of air, to ensure the clearance distance between low and high sides, the transformer

size is increased dramatically compared to the previous design. Slots are added to PCB to

increase the creepage distance. [16] To assure the insulation capability between core and

windings, [16, 17] utilize Kapton tape. Although the completed transformer design is bulky

and the manufacturing process is complex, the insulation level is able to reach over 20 kV.

For multi-channel outputs design, [18] uses PCB windings in a flyback converter shown in

Fig. 5. By increasing the number of PCB layers, it is able to supply seven loads

simultaneously with a total output power of 20 W. Although this type of design has large

dimensions, the value can be reduced below 2 pF due to the large distance between

windings. To further decrease value, double transformer s with the opposite winding

method is introduced in [17]. Overall, this type of solution has a high insulation level, small

value but large size.

LrCp

Co Ro

Cd

Vin

Vo

Lm

6

Figure 5. Circuit schematic of a flyback converter

The second subcategory is the voltage-transformer-based design with two separated

PCBs, and the transformer is located on the secondary side boards. As shown in Fig. 6, the

reinforcement insulation distance is slightly different from previous solutions, but in this

case, the MV insulation level can be easily realized by increasing the distance between two

boards. [11] As presented in [19-24], since the high side and low side boards are separated,

the insulation between circuits is less concerned. To ensure the insulation capability inside

the transformer, solid materials are applied. [19-22] potted transformer with either epoxy or

silicone, which is more reliable than using air. [23] offers another solution by using Kapton

tape and PCB is used as insulation media in [24]. All designs can achieve a breakdown

voltage over 18 kVac with a similar converter size to the second case of a single PCB design,

but due to the permittivity of solid material, the is relatively large. From a circuit

perspective, besides flyback, CLLC and single active bridge shown in Fig. 7 and Fig. 8 are

the common topologies due to simple structure and capability to achieve ZVS, but most

designs have an unregulated stage. Thus, the operating condition for this type of design is

limited and when multiple secondary side circuits are connected in parallel, normal

operation will be affected. Thus, besides using PCB windings, using litz wire with the

structure shown in Fig. 6 is difficult to achieve multi-load driving ability.

Cd

Vin Vo

Co Ro

7

Figure 6. Block diagram for voltage-transformer-based design on two PCBs with labeled insulation path

Figure 7. Circuit schematic of CLLC resonant converter

Figure 8. Circuit schematic of single active bridge

To solve the multiple output voltage problem while keeping a high insulation level, a

current-based transformer solution becomes a good candidate. By using the LCCL-LC

Cp

Co RoCd

Vin Vo

Cs

Lp Ls

k

Co RoCd

Vin Vo

Llk

8

topology shown in Fig. 10 [25], the output of the primary side circuit is a constant current,

so multiple loads could be connected in series with one wire hanging in the converter. [25-

27] uses a MV wire as primary side winding in design, so as shown in Fig. 9 by increasing

the length of the MV wire, the insulation requirement can be easily met. Although the

transformer size does not determine the insulation level anymore, it still affects PDIV.

[25][26] can achieve PDIV over 10 kVac and breakdown over 20 kV, but the total output

power is low and the primary side circuit size is extremely large [26] which is not suitable

for system integration.

Figure 9. Block diagram for current-transformer-based design on two PCBs

Figure 10. Circuit schematic of LCCL-LC resonant converter

Priamry

side

Circuit

Secondary

side

Circuit

PCB Clearance/

Creepage

PCB

Cp

Cr Lp Ls

Cd

Vin

kLr Cs

Co Ro

Vo

9

1.2.2 Non-transformer-based Designs

Wireless power transfer (WPT) is the most popular candidate for core-less APS design.

As presented in [28-33], the insulation level depends on the distance between the

transmitting and receiving coils. By adjusting the distance between two transmitter and

receiver coils, insulation levels can be easily scaled up or down. Thus, unlike a transformer-

based solution, WPT can achieve different insulation voltages without changing coil size.

Depends on the effective area and distance between two sets of coils, the value can be

different. By increasing the transmitter coil area or using topology with current source

behavior, multi-channel outputs can be realized. [32] [33] However, WPT is a location-

oriented design which means the transmitter and receiver coils have to overlap with each

other with a certain distance in between. Any location mismatch can cause low efficiency.

Thus, system integration becomes a challenge for WPT when there are multiple loads

needed to be powered.

Power over fiber (PoF) is the last APS solution that is available now. It can achieve high

insulation voltage with negligible value. However, the output power is limited to 0.5

W and the efficiency is below 50 %. Although paralleling more receivers can eventually

increase the output power to the desired value, high cost and ultra-large transmitter are the

biggest concern. Thus, PoF cannot be implemented in a high power density converter

although high isolation level and ultra-small value can be achieved.

Table 2 lists the comparison results for four different state-of-the-art solutions of APS.

Different solutions have different advantages and disadvantages. Considering the overall

performance, the current transformer-based solution becomes the best candidate for high

insulation voltage, high power density with a small value APS design. Thus, this paper

proposes a current-transformer-based APS with a design target as shown in Fig. 11 of 20

kV breakdown voltage, 20 W output power, small dimensions, and ultra-low (< 5 pF).

10

Table 2. Comparisons of State-of-the-Art Features

Solutions Insulation level Size Output Power

If multi-

channel

available

VT-based with

single PCB Relatively low Very small Relatively high Low

Yes

(limited)

VT-based with

two PCBs Relatively high Large High High No

CT-based Relatively high Moderate Relatively Low Relatively High Yes

Non-

transformer-

based

High Moderate

Relatively High

(WPT)

Very low (PoF)

High (WPT)

Very low (PoF) Yes

Figure 11. State-of-the-art architectures with blue dots indicated as voltage transformer-based single

PCB solution, orange dots indicated as voltage transformer-based two PCBs solution, green dots indicated

as a current transformer-based solution, and grey dots indicated as a non-transformer-based solution

11

1.3 Thesis Outline

This thesis focuses on the design and evaluation for a GaN-based isolated DC/DC

auxiliary power supply based on the given specifications. This APS is used for MV SiC-

based convert system.

In Chapter 1, the background and motivation for achieving galvanic isolation APS for

the MV system are discussed. The improved feasibility of this application due to the recent

advancement in wide-bandgap semiconductor technology is explained. A survey on the

state-of-the-art architectures including research project and commercial produces are

presented. Advantages and disadvantages will be briefly discussed. Finally, the target

specifications for the converter prototype to be designed are presented.

Chapter 2 discusses transformer design and optimization based on the requirement of

volume, insulation voltage, and . Due to the core structure, new modeling methods of

maximum allowable voltage and related are proposed and applied in transformer

design. Also, core material and wire selections will also be included in this chapter.

In Chapter 3, a brief discussion about the general structures and corresponding

topologies of APS will be presented first. Then, based on analysis, LCCL-LC topology is

selected and will be introduced specifically. The complete design process of this converter

including magnetic design, device selection, controller, ZVS realization will be presented.

Furthermore, for higher power applications, the design challenge and process for parallel

device structure will be discussed. Finally, the experiment results will be provided.

Chapter 4 focuses on insulation design. Eight different solutions will be introduced.

Different insulation materials and shielding techniques are presented. At the same time, the

effect on caused by different insulation structures will be analyzed. Testing results will

also be provided in the end.

Chapter 5 will provide system experiment results. Low voltage tests with wireless power

transfer (WPT) and assembled auxiliary power system in MV converter test results will be

included.

The overall summary of the thesis along with potential areas of interest that can be

continued as an extension of the research outlined will be presented in Chapter 6.

12

Chapter 2

Transformer Modeling and Design

2.1 Introduction

The transformer is always the key component in converter design as it determines the

insulation level, coupling capacitor values, efficiency, and converter volume. In traditional

transformer design, the overall losses are a major concern and coupling capacitance is less

important since high efficiency is the most desired feature in many applications. However,

the situation is opposite for APS in MV applications. In APS design for MV applications,

insulation capability, coupling capacitance, and overall volume are the three major design

criteria, so losses are less concerned in this design. Thus, a new transformer design method

based on these three criteria will be introduced in the following sessions. According to

[25], a toroid core without an air gap is selected. For installation and insulation purposes,

a single turn using insulated wire of AWG 18 is selected as the primary side winding going

through the center of the core. As shown in Fig. 12, the secondary side winding is wound

tightly on the opposite side of the core in a compact way. Based on this structure, specific

modeling of insulation voltage and coupling capacitance will be introduced first. Then, a

specific transformer design process will be discussed.

Figure 12. 3D view of proposed transformer design structure

13

2.2 Maximum Allowable Voltage Modeling

In the insulation design, the primary side winding is connected to low potentials, such

as GND, and the secondary side winding connects to high potential as shown in Fig. 12.

Although the secondary side winding is tightly wound around the core, there is still a thin

air gap between the core and windings labeled as and in Fig. 13. To ensure no

breakdown would happen in the thin air without adding additional insulation material

such as Kapton tape, the core is also connected to the high voltage side. Thus, the

maximum electric field is mainly determined by the distance between the primary side

winding and the secondary side winding. However, due to the compact winding method

and bending part of secondary side wire, the electric field inside the transformer is not

uniformly distributed, which increases the difficulty to predict the maximum allowable

voltage for this structure.

To simplify the model, it assumes that , and shown in Fig. 15 is larger than

shown in Fig. 13, so only the portion of primary side wire is located at the center of the

core will affect the electric field distribution. In this case, this transformer structure can be

regarded as a concentric cylinder as indicated in Fig. 13 with a uniformly distributed

electric field between the high voltage and low voltage sides. The maximum electric field

inside the structure is [38]:

(1)

where is the radius of the primary side wire including the insulating layer and is

the distance from the center of the primary side wire to the center of the secondary side

wire ( ).

When the secondary side wire radius is much smaller than , can be substituted for

.

14

Figure 13. Simplified structure of the proposed transformer for maximum allowable voltage modeling

Although in the air, the maximum electric field is 3 kV/mm, since manufacturing

tolerance exists in practice, a design margin is required. Thus, the designed maximum

electric field ( ) for the concentric cylinder structure is 2 kV/mm. Then, based on eq.

(1), the maximum allowable voltage is:

(2)

Figure. 14 shows the maximum allowable voltage with a transformer inner radius from

3.5 mm to 20.5 mm. From the figure, to achieve a maximum allowable voltage of 5 kV,

the inner radius of the core is required to be at least 7.3 mm. Due to the manufacturing

requirement, the minimum inner radius will be 7.5 mm.

Figure 14. The maximum allowable voltage with increasing transformer inner radius for concentric

cylinder structure

d7

2rpi

core

primary side wire

15

2.3 Modeling

Due to the fast switching speed of SiC MOSFETs, a common-mode current is often

induced via coupling capacitors ( ) of isolated components inside the converter, which

can introduce electromagnetic interference (EMI) problems. [39, 40] As shown in Fig. 1,

the isolated gate driver power supply and signal controller provide common-mode current

paths. However, the controller signal is usually transmitted by optical fiber and the distance

between transmitter and receiver is much larger than the sending side and receiving side

circuitries of APS, so the caused by signal transmission negligible compared to the

caused by auxiliary power transmission. Thus, APS becomes the main path to conduct

common-mode current. To reduce the circulating common-mode current, a small

value is necessary for APS design. Therefore, an accurate model is needed in order to

complete the transformer design. Paper [25] and [41] provide a modeling method by using

electric field energy. This method divides the two side windings into different groups based

on the coupling path first and then calculates each mutual capacitance. With different

distributed voltage for each group, the corresponding electric field energy can be derived.

By summing up all-electric field energy portions, the final can be calculated with

predetermined input and output voltages. However, the method does not include all

coupling paths between windings. Besides, the calculation process is complex. Therefore,

a new model is developed with all coupling paths considered. In this section, the

mathematical derivation of based on the structure shown in Fig. 12 will be introduced.

To simplify the model derivation process, the insulating layer of the primary side is not

considered. Fig. 15 shows the side view of the transformer with labeled dimensions.

16

Figure 15. Side view of the proposed transformer structure without the insulated layer of primary side

winding

The mutual capacitance between the primary and secondary side winding’s inner

portion labeled as and above is shown in Fig. 16. There are two coupling paths with

three different coupling capacitances between these two wire segments. Firstly, and

are coupled directly through the insulating material which is air in this case and generates

. Then, can be simply modeled as a capacitance between two parallel wires

[42]

(3)

where is the relative permittivity of the insulating material. is the length of .

is the distance from the center of to the center of . is the conductor radius of

primary side wire. is the radius of the secondary side wire.

Since is the coupling capacitor between the primary side winding turn to

secondary winding turn, for the transformer design with multiple turns on the secondary

side, the total coupling capacitance coupled through the air directly is

(4)

where n is the number of turns on the secondary side.

primary side wire

secondary side wire

h ri

d2

2rp

2rs

d3d4 d1

P1P2

P2

S1S2

core

ro

17

The second coupling path between and is from to core first and then from the

core to . Thus, two coupling capacitances labeled as and are created and they

are in series connection. represents the total capacitance that is coupled between

and every single point on the core. To simplify the derivation of , it assumes that the

core is a good conductor. Then, can be regarded as the capacitance of concentric

cylinders structure:

(5)

where is the core inner radius.

Similar to , represents the total capacitance that is coupled between and

every single point on the core, but since is not at the center of the core, eq. (5) cannot

be used in this case. Thus, a new mathematical model needs to be built. By dividing the

core into multiple rectangular prisms with the same dimensions as , the coupling

capacitance between and each rectangular prism approximates to be the capacitance

between parallel wires with a distance of

, where (6)

From eq. (6), is increasing with decreasing . Since secondary side wires are

tightly wounded around the core, the that is from to the closest rectangular prisms

is ultra-small, which can generate an infinitely large capacitance. This leads to that

value is infinitely large. Since and are in series, the total capacitance for this

coupling path is eventually dominated by . To be noticed, although there are multiple

turns on the secondary side, all turns share the same in the model because all are

connected and can be regarded as the same potential point.

18

Figure 16. The coupling capacitors between segments of and

Figure 17 indicates the coupling capacitors caused by and . Unlike the previous

case, this time, there is only one coupling path which is from to core and from the core

to . The capacitor between and core is already discussed can be calculated above.

The derivation process of is similar with ’s. According to eq. (6), is

infinitely large.

Figure 17. The coupling capacitors between segments of and

As shown in Fig. 18, there are two coupling capacitances, and , between

and . is generated by the coupling between and core, so a similar method of

calculating can be applied to obtain . However, the calculation process is

CsiciCpisi,1

core

Cpisi,2

Cpisi,n

Cpici

P1S1,1

S1,2

S1,n

CpiciCsoco

core

P1

S2,1

S2,2

S2,n

19

relatively complicated. To simplify the derivation process, it assumes that the core is a

good conductor, so can be considered as the capacitance between two parallel

cylinders. In this case, is determined as

(7)

where is the outer radius of the core and is the distance from the center of to

the outer cylindrical surface of the core.

Unlike or , is placed a certain distance away from the core’s outer surface due

to insulation requirement. Thus, is not infinitely large and cannot be dropped. As

discussed before, is infinitely large. Thus, this coupling path is dominated by

eventually since and are connected in series.

Figure 18. The coupling capacitors between segments and

The last coupling path is shown in Fig. 19, which is between and . is the

same one as discussed in the previous case and is ignored in this branch. One

important aspect that needs to be noticed that the capacitance caused by direct coupling

20

through the air between and is ignored because, for this designed APS, the number

of turns is limited to 10. In this situation, the area that is covered by secondary side

windings will not exceed half of the core. In another word, if the number of turns for the

secondary side is high enough which leads to the distance between and is equal or

less than , this capacitor should be considered and can be calculated by using eq.

(3).

Figure 19. The coupling capacitors between segment and

The total common-mode coupling capacitors is the summation of all capacitors

mentioned above. Since and are ignored, the final is

(8)

This model is verified with simulation results. Fig. 20 shows the comparison between

simulation and calculation results for one example with transformer inner radius of 7.5

mm, the outer radius of 12.5 mm, and a height of 7 mm. Furthermore, is set to be 10

mm. With turn number from 1 to 10, this model provides high accuracy with an average

of less than 5% error. Thus, the proposed model that is based on physical geometries

is valid.

21

Figure 20. model verification

After obtaining the equation, the relationship between and transformer geometries

need to be further analyzed in order to determine the critical impact factor of , which

can be used as a design boundary in transformer optimization. Fig. 21 shows the

calculation results of with turn numbers varied from 1 to 10 when transformer inner

radius changing from 7.5 mm to 12.5 mm. In this case, transformer height is 14 mm and

the outer radius is 15 mm. As illustrated in the figure, is increasing with increasing

turn numbers and decreasing inner radius. With a fixed turn number, varies less than

20%.

To analyze the impact of transformer height on , the inner radius is selected to be

7.5 mm and the outer radius is 15 mm. Fig. 22 shows the results as transformer height

varied from 1 mm to 14 mm with turn number from 1 to 10. As the result, is highly

increased with larger transformer height. With lower height, i.e. h < 5 mm, turn number

has a smaller impact on , but the impact of turn numbers will increase will increasing

transformer height.

22

Figure 21. Effect of transformer inner radius on with different number of turns

Figure 22. Effect of transformer height on with a different number of turns

Figure 23 shows the results of with transformer inner radius of 7.5 mm, the

height of 14 mm, and the outer radius varied between 8.5 mm and 15 mm under different

turn ratio conditions. The effect of the transformer outer radius is limited. From the

figure, value is approximately constant over the whole outer radius range. Similar to

previous cases, larger turn numbers will increase value, but under the same height

23

conditions, the difference of between turn to turn is nearly the same.

Overall, based on the calculation results, transformer height has the largest impact on

, and outer radius has a smaller impact on . Therefore, to obtain a small

value, a lower transformer height with a small turn ratio is preferred.

Figure 23. Effect of transformer outer radius on with a different number of turns

2.4 Transformer Design

Transformer design is based on three criteria: volume, PDIV and since they are

highly related to transformer geometries as well as they are the key features of APS.

However, it is difficult to achieve a high insulation level, low in a compact form-factor

at the same time because the realization condition of each feature is contradicted with

others. By increasing switching frequency, transformer size can be greatly reduced, but to

achieve a high insulation level, the transformer inner radius needs to be large which will

lead to a larger outer radius. In this case, to maintain a relatively small footprint, either

transformer height or turns ratio needs to be increased to avoid saturation problem.

However, in the meantime, will be increased. Thus, the goal for transformer design is

24

to determine the optimal core geometries, turn ratios, and switching frequency that can

balance these three features. The specific design process will be introduced in this session.

Table 3 shows the design specifications for the transformer. The desired transformer is

able to achieve a PDIV of 5 kV with air insulation, an overall volume of 3.6 , and

of less than 1 pF. To ensure the small transformer volume, the switching frequency is

selected above 500 kHz.

Table 3. Transformer Design Specifications

Parameters Values

Transformer height ( ) 14 mm

Transformer outer radius ( ) 12.5 mm

Transformer volume < 3.6

PDIV 5 kV

1

Switching frequency ( ) > 500 kHz

Secondary side dc current ( ) 1.4 A

Based on the desired frequency range, core material and litz wire can be selected first.

Six core materials are suitable for high-frequency applications. P51, P52, P53 from Acme

Electronics, and ML95s from Hitachi are applicable for frequencies from 500 kHz to 1

MHz. [43] [45] For switching frequencies above 1 MHz, P61 from Acme Electronics and

ML91s from Hitachi are the best candidates. [44] [45]. With a flux density of 50 mT, Fig.

24 shows the core loss density of all selected materials with different frequencies under

different temperatures. In the figure, the solid line represents test results with an ambient

temperature of 23 , and the dash line represents test results with the ambient

temperature of 100 . Although P61 is claimed to be designed for frequency from 1 to 3

MHz, the specific core loss density with a flux density of 50 mT is not provided in the

datasheet for the range of 2 to 3 MHz, so only 1 MHz data is plotted in the figure below.

Overall, under different temperatures, ML91s has the smallest core loss density over the

25

whole frequency range. Thus, it is selected as the final core material. However, since the

core loss density of ML91S increases rapidly after 1 MHz, the desired frequency range is

narrowed down to 500 kHz to 1 MHz.

Figure 24. Core loss density of P51(labeled in blue), P52 (labeled in orange), P53(labeled in gray), ML91S

(labeled in yellow), ML95S (labeled in green), and P61(labeled in red).

For frequency from 500 kHz to 1 MHz, to reduce the ac winding loss caused by skin

effect, strand AWG 44 and AWG 46 listed in Table 4 become the candidates for secondary

side windings.

Table 4. Litz Wire Parameters

Strand AWG Diameter (𝛍𝐦) Frequency (kHz) Skin Depth (𝛍𝐦)

44 50 350-850 110-70.7

46 40 850-1400 70.7-55.1

Since APS is designed to be 24 V with 20 W for each receiving side, the load current is

approximately 1 A. With a certain design margin, the secondary side current is designed to

be 1.4 A as listed in Table 3. According to the current rating, as shown in Fig. 25, the

equivalent AWG 25 is selected as the secondary side wire.

26

Figure 25. Current rating for equivalent AWG

After determining core material and wire, transformer geometry design is the next step.

In the previous session, when calculating the maximum allowable voltage inside the

transformer structure, 2 kV/mm is selected as the designed maximum electric field in air,

which is the critical value to determine partial discharge free design. [45] Since PDIV is

difficult to model, with the same maximum field strength, the maximum allowable voltage

can be regarded as the reference for PDIV. In another word, in this thesis, it assumes that

PDIV follows the same trend of modeled maximum allowable voltage. Thus, according to

Fig. 14, the transformer inner radius has a direct effect on PDIV. In addition, value

will be affected by the transformer inner radius. In order to reach high PDIV and small

value, a large inner radius is desired. To achieve so, the outer radius is designed with the

largest value of 12.5 mm based on Table 3.

As shown in Fig. 22, height is the most critical factor in design, so a low-profile

transformer is preferred. With a fixed outer radius, the minimum height can be achieved

with the smallest inner radius. However, according to eq. (2), the inner radius is limited by

PDIV. To balance between PDIV and , the inner radius is selected based on the

minimum requirement of PDIV, which means the inner radius is 7.5 mm. In this case, the

minimum transformer height can be found based on the desired value and maximum

flux density.

27

With the designed inner and outer radius, transformer volume can be easily calculated

using the following equations. [47] Fig. 26 plots the transformer volume with height varied

from 1 mm to 14 mm. The red dash line represents the maximum volume given in Table

3. As labeled in the figure, the maximum height is limited to 11.8 mm. Due to

manufacturing capability, the height has to be an integer. In addition, if the profile is too

low, the transformer becomes fragile. Therefore, the available height is limited between 3

to 11 mm.

(9)

(10)

(11)

Figure 26. Transformer volume with different heights

To determine the optimal height and turn ratio, the first step is to determine the turn

ratio range. Due to the current rating of the primary side wire and the current requirement

for the secondary side, the maximum turn number for the secondary side is 10. Then, flux

density ( ) is introduced as the fourth design boundary, so the turn ratio range can be

further reduced. For core material ML91S, the recommended maximum flux density is 50

28

mT. Considering the design margin, the interested range of maximum flux density is 25

mT to 40 mT. With a maximum switching frequency of 1 MHz, it can find the minimum

turn number under different height conditions based on eq. (12). Fig. 27 shows the

minimum turn number is 3 with of 40 mT and transformer height of 11 mm.

Furthermore, from the figure, big advantages could be gained when transformer height

increases from 3 mm to 4 mm. Thus, the range of transformer height is from 4 mm to 11

mm.

, where (12)

where D is the duty cycle which usually is 0.5.

Figure 27. Calculated with turn numbers from 1 to 10 under different height conditions

After obtaining the range of transformer height and turn numbers, the next step is to

analyze the effect of switching frequency on transformer height and turn numbers.

and values are used to evaluate each set of height and turn number. Since the maximum

desired value is 1 pF, by simulation results, the insulating layer of primary side wire

will add roughly 10% to the calculated value, the boundary for calculated is reduced

to be 0.9 pF. Fig. 28 – Fig. 33 illustrate the results of calculated and with turn

29

number from 3 to 10 under different transformer height and switching frequency. Blue

curves indicate results and the orange curves indicate results. Each curve is

gained based on different transformer height and plotted with different markers. In each

figure, only when the curves with the same marker but different colors cross each other,

there is a solution that satisfies both requirement of and . For example, Fig. 32

shows the results under 900 kHz. For transformer height of 4, 5, 6, and 7 mm, the

curve and curve are across each other (labeled in red dots). Then, each crossing point

matches a turn number that can achieve from 25 mT to 40 mT while is smaller

than 0.9 pF. However, most of the time, the corresponding turn number is not an integer

which is not practical in reality. In this case, the turn number is rounded to the nearest

integer value and selected from the green area labeled in Fig. 32. Sometimes, the turn

number can be either rounded up or down, such as in the 1 MHz plot, when transformer

height is 5 mm, the turn number could be either 6 or 7. In this case, the turn number that

generates smaller is selected. Overall, there is no solution for frequency from 500 kHz

to 800 kHz, and are few solutions for the frequency of 900 kHz and 1 MHz.

Figure 28. (plotted in blue) and (plotted in orange) values under switching frequency of 500 kHz

30



31


From the green area labeled in Fig. 32, four pairs of turn number and height are

available: 1). h=4 mm and =8.5; 2). h=5 mm and =6.8; 3). h=6 mm and =5.6; and

4). h=7 mm and =4.8; To obtain a practical turn number for each height, rounding up is

needed. However, for the last pair, there is no closest integer for turn number that satisfies

both requirements. Therefore, three solutions left and they are 1). h=4 mm and =9; 2).

h=5 mm and =7; 3). h=6 mm and =6;

Figure 32. (plotted in blue) and (plotted in orange) values under switching frequency of 900

kHz. All suitable options are converted by the green area.

32

For a switching frequency of 1 MHz, there are five sets of solutions left after rounding

up turn numbers. They are 1). h=4 mm, =8; 2). h=5 mm, =6; 3). h=6 mm, =5; 4).

h=7 mm, =5; and 5). h=8 mm, =4.

Figure 33. (plotted in blue) and (plotted in orange) values under switching frequency of 1 MHz

Table 5 lists all possible solutions within the desired range of transformer height, turn

number, and frequency.

Table 5. Summary of Available Solutions for Frequency of 900 kHz and 1 MHz

Frequency Transformer Height (mm) Turn Number

900 kHz

4 9

5 7

6 5

1 MHz

4 8

5 6

6 5

7 5

8 4

33

To obtain the final solution of transformer design, total losses including core loss,

winding loss, and device loss need to be calculated and compared. Although both 900 kHz

and 1 MHz have available solutions, considering the design of passive components in the

resonate converter, 1 MHz is selected as the switching frequency. Thus, only five cases

will be calculated in the following part.

First, to calculate core loss, needs to be calculated for each pair of solutions based

on eq. (12). By using the value provided in the datasheet, core loss with square wave

excitation can be obtained as:

(13)

(14)

Since the switching frequency is 1 MHz, strand AWG 46 is selected. Assume the

average of H for each turn is the same, then simulate the transformer model in Maxwell

and get the average H value. The ac resistance can be calculated by [48]

, where (15)

where is the strand diameter and is the resistivity of copper.

Based on the simulated H value, the ac winding loss is approximately 6.6 .

Compared to dc winding loss, it is negligible.

The dc resistance can be calculated with a predetermined equivalent wire size for the

primary and secondary sides. Since the ac winding loss is ultra-small, the total winding

loss includes dc winding loss for both sides only.

(16)

(17)

Finally, to obtain the device loss, the device needs to be selected first. Due to high

switching frequency, GaN power devices become the best candidate for high switching

34

speed and low losses. Since the normal operating voltage for the primary side is 48 V, low

voltage devices are desired. Table 6 lists a few candidates from EPC with a breakdown

voltage of 60 V and 80 V. Although soft switching can be realized, a 12 V design margin

is not enough to guarantee safe operation. To reduce conduction loss, small turn-on

resistance is required. Thus, EPC 2021 is selected as the main power switch.

Table 6. GaN Device Candidates

𝐕𝐝𝐬 𝐈𝐝 𝐑𝐝𝐬(𝐨𝐧) 𝐐𝐠 Size

(mm x mm)

EPC2031 60 V 48 A 2.6 mΩ 16 nC 4.6 x 2.6

EPC2020 60 V 90 A 2.2 mΩ 16 nC 6.05 x 2.3

EPC2102 60 V 220 A 4.9 mΩ 8 nC 6.05 x 2.3

EPC2029 80 V 48 A 3.2 mΩ 13 nC 4.6 x 2.6

EPC2021 80 V 90 A 2.2 mΩ 15 nC 6.05 x 2.3

EPC2103 80 V 195 A 5.5 mΩ 6.5 nC 6.05 x 2.3

Since ZVS is realized and turn-off loss is normally small compared to conduction loss,

switching loss is not included. Thus, the device losses only include conduction loss and

driving loss.

(18)

(19)

where is the driving voltage that is normally 5 V.

(20)

Figure 34 shows the total power loss calculated from eq. (21) for all solutions under

1MHz. For a height of 7 mm and a turn number of 5, it has the minimum losses.

Furthermore, considering the tunning process during the circuit design and manufacturing

tolerance of the core, needs to have some margins. Therefore, the final transformer

is designed with an inner radius of 7.5 mm, an outer radius of 12.5 mm, a height of 7 mm

35

with 5 turns on the secondary side, and a switching frequency of 1 MHz. The complete

design procedure is shown in Fig. 37.

(21)

Figure 34. Total power loss for 5 pair of solutions

2.5 Test Result

Figure 35 shows the hardware prototype for the designed transformer with an inner

diameter of 15 mm, an outer diameter of 25 mm, and a height of 7 mm. The secondary

side has a turn number of 5. At 10 kHz, the designed transformer is able to achieve

of 1.09 pF as shown in Fig. 36, which is close to the predicted value of 1 pF. Thus, the

model developed above is valid.

Figure 35. Hardware prototype of the designed transformer with labeled dimensions

36

Figure 36. The measurement result of for designed transformer

2.6 Summary

This chapter provides the models of maximum allowable voltage for insulation design

and common-mode coupling capacitors for toroid core with single primary side winding

and multiple secondary side windings. These models as well as volume are used as the

design boundaries of the transformer. Based on the desired value of 1 pF, the

maximum allowable voltage of 5 kV, transformer volume of 3.6 , and maximum flux

density of 25 mT to 40 mT, the optimized transformer has an inner radius of 7.5 mm, an

outer radius of 12.5 mm, and height of 7 mm. The optimal switching frequency is 1 MHz

and the turn number is 5 for the secondary side. The detailed transformer design steps are

provided.

37

Figure 37. Flowchart of transformer design steps

Select ro & ri

Select a fsw, sweep h,

get Bmax vs. N & Ccm vs. N

Get different sets of h & N

Output the final h & N values

Determine h range

Calculate total power loss for

different sets of h & N

If not finish

calculation for

all fsw values

Determine the range of ro , ri , h, N , fsw ,V,

PDIV, Ccm

Select the core materials

If finish calculation for

all fsw values

38

Chapter 3

Circuit Design

3.1 Introduction

As state previously, considering insulation capability, multi-channel outputs, and overall

size, current-transformer-based APS is the best candidate for a 10 kV SiC-based converter

system. Due to constant current output on the sending side and coupling independent

resonance frequency [35], LCCL-LC topology is selected. However, with the traditional

design of LCCL-LC topology, the turn-off current for ZVS realization is dependent on load

conditions. cannot be guaranteed under different load conditions. In addition, the traditional

designed LCCL-LC circuit has a low tolerance for parasitic changing and component

mismatch. Thus, to solve all issues mentioned above, a new LCCL-LC design methodology

is introduced in this chapter. The proposed methodology can realize constant turn-off

current regardless of load conditions and it is not sensitive to parameter change. A controller

is added to the system to ensure the output voltage is regulated and able to operate under

faulty load conditions. This chapter will provide the specific circuit design process of APS

including controller design, ZVS realization, and PCB optimization.

3.2 Topologies Comparisons

Under different load conditions, to ensure all receiving side circuitries to gain power

simultaneously and work independently, a load-independent current source is desired as the

output of sending side circuitry. Fig. 38 (a) and (b) show two simplified structures that have

a current source as output with the input of a voltage source. [36] According to Thevenin’s

Theorem, in the T-model circuit with one passive component ( ) in series with an

input voltage source and another passive component ( ) in parallel with the whole

39

branch, the original circuit can be transformed to the equivalent circuit shown in Fig. 39,

which is a current source in parallel with and . Utilizing the resonance phenomena of

parallel structure, with the resonant frequency of

(22)

(a)

(b)

Figure 38. Constant current output from a voltage source connected in series with (a) an inductor (b) a

capacitor d

The total impedance of and is infinitely large. Thus, a load-independent current

source is formed. With an input voltage of a square wave, by designing resonate

frequency same with switching frequency, only contains the first harmonics component

with corresponding magnitudes for type A and type B are

(23)

Vin

Z3

Ro Vo

+

-

Cr

Lr

ip

40

(24)

Figure 39. Current source mechanism of type A and type B circuits

According to eq. (23) and (24), with a fixed frequency and input voltage, the current

source magnitude only depends on or . However, for type A circuits such as CLCL-

LC topology shown in Fig. 40, in order to realize ZVS, and will experience high

current and high voltage stresses, especially for the design with high current bus

requirement. [37] In this case, component selection becomes a challenge. Thus, the type B

circuit is selected, and the specific structure named LCCL-LC is shown in Fig. 10.

Figure 40. CLCL-LC resonant converter

3.3 LCCL-LC Operation Principle

Z3

Ro Vo

+

-

CrLrip

iin

CpCr

Lp Ls

Cd

Vin

k

Lr

Cs

Co Ro

Vo

41

In one switching cycle, the LCCL-LC converter has six operating modes. Each mode

will be introduced below. Fig. 45 demonstrates the convert waveforms in steady-state

operation.

a) Mode 1 [ - ]

From to , the top device is in turn-on mode. The resonant tank connects to the

input source directly, so the current starts increasing and is charging until is

off. and is out of phase by , therefore ZVS can be achieved in a later period.

In the meanwhile, since and are in resonance, the current source is a sine wave

and outputs a half-cycle from negative peak point to a positive peak point. and are in

phase. Thus, during the negative half cycle of , and will conduct, and after

reaches to zero, and turns off, and and start conducting.

Figure 41. LCCL-LC operation condition in mode 1 with the labeled current direction

b) Mode 2 [ - ]

At , the top device turns off. The deadtime period starts. Due to magnetizing

inductance, the current flow direction in the converter does not change but starts to

decrease, so the output capacitors of and is charging and discharging. and

are still conducting.

42


c) Mode 3 [ - ]

At , the output capacitors of and are fully charged and discharged, so the

voltage across drops to zero. Since as shown in Fig. 43, the current direction in the

converter is unchanged, the body diode of conducts. This is still in the deadtime period.


d) Mode 4 [ - ]

At , turns on with ZVS realized. The current direction remains the same until

reaching zero. and resonate from positive peak value to negative peak value, so

and conduct first during the positive cycle and then and conduct after and

reaches zero. Then, the current direction in the converter is reversed.

43


e) Mode 5 [ - ]

Similar to mode 2, at , turns off. The deadtime period starts. The output capacitor

of and is discharging and charging by decreasing until fully discharged or

charged. and are still conducting.


f) Mode 6 [ - ]

At , the output capacitors finished charging and discharging, so the voltage across

drops to zero and body diode is conducted. ZVS will be realized in the next mode.

44

Figure 46. LCCL-LC operation condition in mode 6 with labeled current direction

Figure 47. Voltage and current waveforms for LCCL-LC topology during steady-state operation

45

3.4 LCCL-LC Converter Design

During transformer design, the switching frequency is determined to 1 MHz and the

turn ratio is 1:5. Thus, with a secondary side current (RMS value) of 1.4 A, the primary

side current source magnitude is designed to be 10 A. According to eq. (23) and eq. (22),

and can be calculated. Then, in the following part, the specific design guideline for

controller and compensation network for ZVS realization will be discussed.

3.4.1 Controller Design

As shown in Fig. 48, a current-fed switching network is designed, so the output voltage

becomes scalable. Due to excellent dynamic performance and simple structures as shown

in Fig. 49, a negative feedback hysteresis controller-based switching regulator is selected.

[37] The working principle of the whole feedback network is simple. In the hysteresis

controller, two voltage boundaries, and are predetermined and the output voltage

will bounce in between. When the output voltage reaches the upper boundary , the active

control switch turns on so the input current will flow through the device, and the load

is charged by the output capacitor . In this case, will drop until it reaches the lower

boundary . Then, the active switch will turn off and rise again. The voltage

boundaries can be calculated according to Eq. (25) and (26) based on the schematics shown

in Fig. 49 and the switching frequency of the active controller can be gained according to

Eq. (27). In design, the output capacitor Co is usually large, so the switching frequency for

the controller is relatively low compared with the 1 MHz switching frequency.

During load failure, when a short-circuit happens to a certain load, the sending side

circuit will not be affected due to current source behavior, so other loads remain normal

operation. When an open-circuit happens, the active switch turns on most of the time, so the

faulty load is bypassed and will not impact other loads. Therefore, with a designed feedback

controller, the APS is immune to a fault and able to work independently.

46

Figure 48. LCCL-LC resonant converter with hysteresis controller

Figure 49. Hysteresis controller schematics

(25)

(26)

, where (27)

3.4.2 ZVS Analysis

Soft-switching realization can not only reduce EMI issues in the high-frequency systems

but also can reduce the device’s switching loss which induces less thermal issue. Thus, it is

an important feature to achieve for APS. In this section, an analytical model of ZVS

47

realization for LCCL-LC resonant converter with multi-load condition is proposed. Then,

the specific design procedure is provided.

To achieve ZVS, the turn-off current ( ) must be able to fully charge and discharge the

output capacitors ( ) of and during the deadtime. In the LCCL-LC converter,

is determined by input voltage ( ) and total impedance under switching frequency (

). In general, the total impedance (Zin) is preferred to be inductive for ZVS

realization. The minimum required can be calculated as:

(28)

where is the deadtime.

Normally, the design of compensation network in a resonant converter, such as and

in Fig. 48, is based on fixed circuit parameters which mean the number of loads, each

load condition, total output power, etc. is known. In addition, most of the time, the parasitic

components are ignored in the compensation network design. However, those conditions

are not applicable to the designed APS. As shown in Fig. 50, the proposed APS only

contains one sending side circuitry but multiple receiving sides. Depending on the MV

system requirement, every time, the total number of driving loads and each driving load

condition could be different, which leads to varied impedance to the circuit. Besides this,

due to insulation requirements, the primary side wire always creates a loop area around the

core. With a different numbers of loads and placement of two side boards, the total loop

area shown in Fig. 51 (a) is different. Since the loop area will generate inductance, another

unknown element is introduced to the total impedance calculation. Therefore, in this case,

the compensation network design becomes extremely difficult, so ZVS realization cannot

be guaranteed for all load conditions.

48

Figure 50. Block diagram of proposed APS with the series-connected receiving side

Before the compensation network design, the impact of loop inductance should be

analyzed first. Fig. 52 shows the converter total input impedance under a single load of 20

W with wire self-inductance ( ) varies from 1 nH to 1 . At the switching frequency

of 1 MHz, the magnitude and phase of input impedance have small changes when is

smaller than 100 nH, but when increased to 1 , the input impedance is much

smaller and becomes capacitive. With the winding configuration I shown in Fig. 51(a),

value can be larger than 0.4 while four loads are connected. It will introduce a

significant impedance at switching frequency. As the result, the devices are in a hard-

switching mode as shown in Fig. 53. Such an issue will be worse when the supplied loads

are installed far away from each other. Since the loop inductance has a large impact on input

impedance as well as ZVS realization, the loop area has to be well controlled.

(a)

(b)

Figure 51. Winding configuration (a) I (b) II.

Receiving side of PS

Receiving side of PS

Gate Driver

Gate Driver

Sending side of PS

49

Figure 52. Total impedance with different wire self-inductance

Figure 53. Simulation result for non-ZVS case caused by large wire self-inductance

To reduce the EMI radiation and loop inductance, twist wire as shown in Fig. 51(b) is

preferred. [37] Then, is determined by the small local loop circled around the

transformer. In a real application, as mentioned before, the minimum distance between

primary side wire and core depends on the insulation requirement, which means the winding

loop always exists. Since the total wire self-inductance is proportional to the number of

loads by using winding configuration II, it cannot be ignored during circuit design. To

simplify the circuit design process, it assumes that each local loop is identical and

50

approximately a circular shape as illustrated in Fig. 54. For each local loop, the self-

inductance is:

(29)

where is the loop diameter in millimeter and is the wire thickness in millimeter

as shown in Fig. 54.

Figure 54. Diagram for loop inductance calculation

During design, the dynamic effect from the control switch on load impedance is

ignored because the controller’s switching frequency is much smaller compared to the

main switching frequency . Only two steady-state conditions are considered in the

compensation network design: 1). turns on and 2). turns off. For case 1 of turned

on, the equivalent load impedance is 0 , so it can be regarded as a special condition of

case 2. In the high frequency range, the total impedance is always dominated by passive

components, i.e. indicator and capacitor. The resistive load will only add a damping effect

at each resonant point but not affect the overall impedance. [37] However, in a resonate

network, the worst case is no damping effect. Thus, in the discussion below, the circuit will

only be analyzed with 0 load resistance. The equivalent circuit with multi-load is shown

in Fig. 55.

51

Figure 55. The simplified circuit schematic for compensation network design with multiple loads

In the following part, the traditional compensation methods will be introduced first.

However, they are not applicable for multi-load configuration. The specific reasons will be

illustrated. To solve the problem, a new compensation method will be proposed and verified

by simulation results under different load conditions.

A. Traditional Compensation Method I

As discussed in [25] and [39], is used to compensate the secondary side self-

inductance , so a constant voltage source output is formed with input of a current source.

[36] The circuit transformation is shown in Fig. 56. is used to compensate for the total

impedance so that ZVS could be realized. With a shorted output, the equivalent circuit for

multiple loads (m) is shown in Fig. 57. Since resonates with , the total impedance

from the secondary side is infinitely large. In this case, value will not affect the total

impedance. Thus, the total input impedance is dominated by and , which is close to

0 as shown in Fig. 58. Although when load numbers increase, the total impedance decreases

and input current will increase, as shown in Fig. 59, the input current for either single load

or multi-load conditions is extremely large. It is not practical in real applications.

52

(a)

(b)

Figure 56. Voltage source mechanism from the current source. (a) original circuit (b) equivalent circuit

Figure 57. The equivalent circuit for transition compensation method I

Figure 58. The input impedance of traditional compensation method I

Cs

Vo

+

-

Vs

Ls

vin

Lpk*mLwire*mLr Cp

Cr

Zin

iin

Zeqn

53

Figure 59. Time-domain verification with transitional compensation method I with

B. Traditional Compensation Method II

Another method is to use to compensate the secondary side leakage inductance ,

so the secondary side impedance is 0. can be used to adjust the total input impedance

for ZVS realization. Fig. 60 illustrates the equivalent circuit for multi-load conditions. With

a fixed value, the total input impedance is proportional to the number of loads. In this

case, with more loads connected in series, the input current becomes smaller. The results

are shown in Fig. 61 and Fig. 62. Since is designed based on the maximum number of

loads, at light load condition, the input current will increase and the circuit becomes more

lossy than heavy load condition.

Figure 60. The equivalent circuit for traditional compensation method II

54

Figure 61. The input impedance of traditional compensation method II

Figure 62. Time-domain verification with transitional compensation method II with

C. Proposed Compensation Method

In the previous methods, the input impedance varied with the number of loads, so the

input current has large changes at different load conditions. This is not desired in many

cases. Therefore, a new compensation method is proposed, which can achieve nearly

constant input impedance.

55

Due to multiple passive components in the circuit, there are many resonates frequencies.

Assuming there is no resonant frequency that is close to , so at , the resonant tank

impedance is either dominated by inductors or capacitors. Thus, to simplify the analysis, at

, the resonant tank can be regarded as either an inductor (Leq) or a capacitor (Ceq). [37]

The equivalent circuit is shown in Fig. 63.

Figure 63. The equivalent circuit for total impedance analysis

First, if the resonant tank behaves like an inductor ( ) around , there are three

different cases (see Fig. 64) with different resonant frequency ( ) caused by and .

(30)

Case 1:

When Leq resonates with Cr at , it will generate an infinite impedance in series with

as shown in Fig. 65. As the result, there will not be any current in the loop, so ZVS is

not realized.

Case 2:

When is smaller but close to , the total impedance at becomes capacitive as

shown in Fig. 64(b). This is not desired for ZVS realization. In addition, another high

resonant frequency ( ) is created and will generate an infinite small impedance:

(31)

vinCr

Leq /Ceq

Lr

Zin

56

When , with a large Leq value, approximately equals to . In this case,

ZVS can be achieved, but the turn-off current is large which can potentially damage the

device.

Case 3:

An inductive impedance is created at . When is larger but close to , the

magnitude of Zin is relatively large. Although the total impedance is inductive, the turn-off

current is too small to achieve ZVS. Thus, in this case, needs to be designed much higher

than , which requires a small Leq value. However, it is difficult to achieve in real

applications due to the uncertainty of load numbers.

(a) (b)

(c)

Figure 64. Equivalent circuits of (a). case 1 (b). case 2 and (c). case 3

Figure 65. Total input impedance for three analyzed cases

57

To avoid complicated design procedure, the impedance of resonant tank around is

designed with capacitive characteristic as shown in Fig. 66. Similar to the previous cases,

an extra resonant frequency is created, but in this design, only one resonant frequency

is generated.

(32)

Figure 66. The equivalent circuit for the proposed compensation model

is always smaller than , so is always inductive at so ZVS could be achieved.

Then, the design has fewer restrictions. The specific design guideline to achieve a capacitive

resonant tank at is provided below.

Step 1: Use Cs to compensate inductances caused by transformer i.e. Lpk, Lsk, and Lm, and

wire loop inductance (Lwire). Therefore, at , Cs should satisfy:

(33)

Unlike traditional design methods which use a single component Cp to compensate the

total impedance, using Cs to compensate each receiving side individually can help Zin to be

independent of the number of loads.

Step 2: Use Cp to control Zin. As shown in Fig. 66, the total impedance at is:

(34)

58

Since and are designed based on current bus value and switching frequency,

becomes the critical element to determine the input impedance at . By adjusting

value, could be well controlled and is independent of load conditions. As shown in Fig.

67, with a fixed Cp value, the total impedance is fixed at a regardless number of loads.

Since the total impedance does not vary with different load conditions, the design of Cp is

much simpler. To verify the load resistor doesn’t affect the operation of the resonant tank,

simulation is performed and results are shown in Fig. 68 and Fig. 69. As a result, the input

impedance magnitude is constant at with or without a load resistor. Thus, Cp can be

designed based on =0 Ω.

Figure 67. Input impedance for the proposed compensation method

59

Figure 68. Time-domain verifications with the proposed compensation method for

Figure 69 Time-domain verification with the proposed compensation method for

3.5 PCB Layout Design

In the high-frequency converter, gate loop and power loop inductances minimization

is the most critical design aspect in PCB layout, since they will induce ringing and

overshoot on gate and switching node voltage, which can potentially damage devices. In

addition, they can slow down the device’s switching speed which can increases losses.

60

According to EPC’s recommendation layout, the input decoupling capacitors are

placed close to the drain terminal of the top device as shown in Fig. 70. [49] Polygon is

used for each power terminals and connected to devices through vias. For thermal

purposes, the polygons connected to each power terminal are designed with a large area

and thermal vias are also designed around devices. However, to avoid high switching

noises polluted other circuits that have different reference potential, the polygon for the

switching node is small. Gate drivers are placed to the gate terminals as close as possible.

To minimize gate loop inductance, the decoupling capacitor for gate drivers are placed on

the same side as gate drivers.

Figure 71 shows another PCB layout for high power applications. This design adopts

parallel devices for each switching position and all devices at each switching position

share one gate driver, so a more symmetrical design for each device is achieved. In this

case, the performance of parallel devices has less difference. As shown in Fig. 71(b),

different than the previous design, this design has input decoupling capacitors under the

devices, so heatsink and fan could be added to the device’s top side. With interleaved

power polygons design, this design is able to achieve power loop inductance of 0.29 nH

and gate loop inductance of 2.5 nH.

Figure 70. PCB layout for single device condition

61

(a)

(b)

(c)

Figure 71. PCB layout for half-bridge configuration using parallel devices. (a) top view (b) bottom view (c)

side view with labeled power loop [49]

3.6 Hardware Prototype and Test Results

Figure 74 shows the receiving side for designed APS. The circuit is designed on two

PCBs including the diode layer and control layer to achieve small size and good thermal

performance. As shown in Fig. 72, only the bottom side of the diode layer has circuits, and

the transformer is located on the top side. Hysteresis controller, current-fed active switch

network, and auxiliary power circuits are located on the top side of the control layer, and

the bottom side of the control layer only contains decoupling capacitor shown in Fig. 73

Overall, the receiving side is able to achieve a power density of 2.22 with a

maximum power of 30 W. The primary side design is shown in Fig. 75. Fig. 76 shows the

modular design of half-bridge for higher power applications. This design is able to reach a

62

bus voltage of 75 V and output power in the kilowatts range. Due to modular, it can be

assembled with other circuit applications. Table 7 provides all passive component values

that are used during the test shown below.

Table 7 Design Parameters for LCCL-LC Resonant Converter

Parameter Design Value

0.5

51 nF

0.5

229 nH

1.33

420 nH

4.3 nF

(a)

(b)

Figure 72. PCB’s (a). top side (b) bottom side for diode layer.

63

(a)

(b)

Figure 73. PCB’s (a) top side (b) bottom side for control layer.

Figure 74. Hardware prototype of the assembled receiving side

Figure 75. Hardware prototype of the sending side

64

Figure 76. Half-bridge modular design’s top view (top) and bottom view with assembled heatsink and fan

3.6.1 Steady-State Responses

Figure 77 shows the steady-state results of the current source and transformer secondary

side input current under light load conditions. It is a sine wave. However, under heavy load

conditions, the controller will introduce a small perturbation for every time the control

device turns on as shown in Fig. 78, but the output will not be disturbed.

65

Figure 77. Current source waveforms under light load condition

Figure 78. Current source waveform under heavy load condition

Figure 79 and 80 show the steady-state waveforms for two load conditions. The output

ripples match well with the deigned value of 0.5 V. Due to relatively large output ripples,

the control device is switching with a low frequency. By adjusting the resistor values of the

controller, output ripples can be set to any other values. However, if the ripple value

decreases, the switching frequency of the control device will increase. Overall, the APS is

able to provide constant output voltages with a different numbers of loads as shown in Fig.

81.

66

Figure 79. Steady-state waveform of output voltages measured in DC mode and controller gate signals

Figure 80. Steady-state waveform of output voltages measured in AC mode and controller gate signals

67

Figure 81. Output voltages of four loads under steady-state operation

3.6.2 Transient Responses

The transient responses are verified by the system with four receiving sides of the total

output power of 80 W. As shown in Fig. 83, during startup, there no overshoot, so soft-

startup is achieved. All loads are able to gain power simultaneously.

Figure 82. System configuration with one sending side and four receiving sides

68

Figure 83. Startup result for four load condition

When fault conditions happen to load as shown in Fig. 82, the protection of the controller

is triggered immediately. As illustrated in Fig. 84 and Fig. 85, during short and open-circuit

conditions, the controller is able to protect the faulty load without interfering with other

loads. Thus, fault immunity is achieved.

Figure 84. Short-circuit response

69

Figure 85. Open-circuit response

3.6.3 ZVS Verification

Figure 86 shows the experiment result of a non-ZVS case caused by unintentional wire

loop inductance. As analyzed before, due to large capacitive input impedance, ZVS is not

achieved. This result matches with the previous analysis shown in Fig. 53.

Figure 86. Experiment results for the non-ZVS condition when

70

With the wining method II showed in Fig. 51 (b), the loop inductance caused by the

primary side wire is controlled to be 46 nH with a loop diameter of 25 mm. Then, applying

the proposed compensation method, ZVS is achieved under different load conditions and

the turn-off current is approximately the same. Thus, the proposed design method is valid.

(a)

(b)

Figure 87. ZVS verification for single load condition with the active control switch (a). turns off (b) turns on

(a)

(b)

Figure 88. ZVS verification for four loads of condition with the active control switch (a). turns off (b) turns

on

3.6.4 Thermal Test

A 3-hour continuous test is performed to verify thermal performance. There is no forced

air-cooling during the test. As shown in Fig. 89 and Fig. 90, the hottest spot on the

secondary side circuit is below 50 and is on the board as well as the primary side wire.

The transformer is around 40 . The devices on the primary side reach 100 under 80

71

W condition. It is still below the device’s rated maximum ambient temperature. Overall,

there is no thermal problem for designed APS.

Figure 89. Thermal test result for a single receiving side with an output power of 20 W.

Figure 90. Thermal test result for four receiving sides with a total output power of 80 W

72

3.7 Summary

In this chapter, the design of the current-fed switch network is discussed first, so the

output voltage of APS becomes regulated. Then, different compensation methodologies

of LCCL-LC converter are analyzed and compared. However, since they are not suitable

for multi-load driving conditions, a new design method for ZVS realization is proposed.

Wire self-inductance caused by the placement of the sending side and receiving side

circuits is also addressed, so the proposed circuit can achieve constant turn-off current

and guarantee ZVS realization. PCB layout design is also shown for minimizing loop

inductance purposes.

Overall, the designed APS has a constant current source as the output of the primary

side, so it is able to drive multiple loads simultaneously. Due to the additional feedback

loop design, the APS can achieve fault immunity and soft startup. During load transient,

the output voltage remains constant. ZVS could be realized regardless of load conditions

and parasitic inductance. Thermal wise, the designed APS is able to perform continuously

without any forced air cooling.

73

Chapter 4

Insulation Design

4.1 Introduction

As mentioned in the previous chapter, the designed transformer uses insulated wire

and litz wire on the primary and secondary sides. To achieve breakdown voltage over 20

kV, the primary side wire only needs to provide a sufficiently long distance between the

exposed conductor and core, since both the core and secondary side wire connect to the

high voltage side. However, it cannot prevent system degradation because partial

discharge (PD) will happen at a lower insulated voltage level. [9] Thus, to maintain a

long lifetime of APS, a PD free insulation system design is desired. To achieve so, the

maximum electric field (E-field) inside the transformer which is related to conductor

geometry and insulation material needs to be well controlled. In this chapter, a total of

eight solutions using different E-field stress control techniques and insulation materials

will be introduced, but not all solutions are able to reach the desired PDIV. The first four

designs use air as insulation media with a PDIV design target of 5 kV AC. 2 kV/mm is

selected as the critical value for E-field strength to evaluate each design solution. The last

four designs adopt silicone as an insulation material to further increase the design target

to 15 kV. In this case, 8 kV/mm is the E-field boundary to determine if the solution meets

the design target.

4.2 Air-Insulated Solutions

4.2.1 Solution I: Basic Design

Figure 91 shows the first design structure. It is the most basic design by using air only.

To analyze the E-field distribution, a 3D FEM simulation is operated with the result shown

74

in Fig. 92. With 5 kV excitation, the highest E-field stress happens around the bending

points of outer windings on the secondary side. This is caused by the small radius of selected

litz wire and sudden change of routing direction. However, the highest E-field within the

transformer does not exceed 2 kV/mm. Thus, this design reaches the design target of 5 kV

PDIV.

Figure 91. Designed transformer with detail labeled

Figure 92. FEM simulation result of plane 1 with 5 kV excitation

4.2.2 Solution II: HV Conductive Shield

The insulating layer of primary side wire is manufactured by silicone rubber which has

a breakdown field strength of 18 kV/mm. Since the breakdown field strength of silicone

rubber is much higher than air, the insulating layer can be utilized in the insulation design.

As shown in Fig. 93, a conductive shield is added to the outer surface of insulated wire. In

this case, the shield can be connected to any other fixed potential between 0 and 5 kV in the

75

MV converter system. For example, the shield can be connected to the midpoint of the bus

voltage. In this case, 5 kV is shared by both insulated layer and air, so the maximum E-field

stress in the air can be reduced. However, this method is not applicable for designed APS

because there is no such potential in the applied MV converter system. Therefore, another

method can be introduced. By connecting the shield to the same reference point with core

and secondary side wire, 5 kV differential voltage is added to the insulating layer only. As

shown in Fig. 94, there is no E-field in the air between shield and core and the maximum E-

field inside the insulting layer is 7.7 kV/mm which is below the breakdown value of 18

kV/mm. However, from the side view, as shown in Fig. 95, the field stress at the triple point,

i.e. junction of air, shield, and insulated layer exceeds the breakdown field of air. This is

caused by the boundary condition for the normal component of the electrical field between

two media [46]:

(35)

Because the relative permittivity of silicone rubber is 3-4 which is higher than air’s, at

the interface of two materials, air will experience a higher E-field. To solve such a problem,

[9] introduces a stress control system. This system uses a nonlinear stress grading layer that

can reshape the E-filed intense area and allow the E-field decreases gradually. However,

such strategy is difficult to be applied in the MV system when multiple loads are connected

to APS’s sending side because multiple shield sections will be required if each driving

component are connected to a different reference potential. Also, to achieve 5 kV PD-free,

the stress grading layer has minimum thickness and length requirement which can reduce

the difficulty during APS assembly. As the result, this insulation solution is not suitable for

designed APS even with a stress grading layer at shield terminals.

76

Figure 93. CAD model of isolated transformer with high voltage shield on insulated wire

Figure 94. FEM simulation result of plane 2 under 5 kV excitation


4.2.3 Solution III: Conductive Shield with Floating Potential

77

As shown in Fig. 96, another shielding technique used in much large power transformer

and bushing system is adopted. [46] By adding a ring shape shield with floating potential

between high voltage and low voltage portions, the E-field distribution inside the

transformer can be reshaped. Depending on the distance from the insulating layer to the

shield, the sensed voltage on the conductive shield will change. Fig. 97 shows the simulation

result of . Since the induced voltage on the shield is 2.2 kV which is slightly

higher than without shield case, the E-field distribution is similar to the result shown in the

solution I. However, from the side view, the maximum E-field exceeds the design boundary

of 2 kV/mm due to the sharp edge of the core. However, when increases to 5 mm, 3.8

kV are induced on the shield. As shown in Fig. 98(a), the maximum E-field increases due

to the limited space between shield and secondary side windings. From the side view shown

in Fig. 98(b), the highest E-field point is transferred from core edges to shield terminals.

Unlike the previous method, this method sets the shield with a floating potential, so

there’s no server E-field problem around the shield terminals, which means termination does

not require for this design to achieve the 5 kV design target. However, based on the

simulation results, adding a shield with floating potential cannot increase PDIV dramatically

compared to a non-shield design. Furthermore, to make sure this method works

appropriately, an accurate shield position is definingly needed. Any position mismatch can

reduce PDIV. Thus, this design structure has extremely high requirements for the

manufacturing and insulation process, which is hard to realize in practice.

Figure 96. CAD model of the isolated transformer with a floating potential shield

78

(a)

(b)

Figure 97. FEM simulation result of (a). plane 4 (b) plane 5 with

(a)

79

(b)

Figure 98. FEM simulation result of (a). plane 4 (b) plane 5 with

4.2.4 Solution IV: Double Shields

Due to the compact winding method, the E-field distribution inside the transformer is

nonuniform as shown in Fig. 92. However, nonuniform filed distribution will introduce

weak points that have higher E-field intensity, so in most cases, a partial discharge will

happen around the weak points first, which means PDIV in a nonuniformly distributed

structure could be lower than in a uniformly distributed structure. Therefore, in order to

improve the insulation performance of this transformer, the conductor structures need to be

more uniform. As the result, double shields with fixed potentials design are introduced as

shown in Fig. 99.

Figure 99. CAD model of the isolated transformer with two fixed potential shields

For the proposed structure, the outer shield connects to the high voltage side, so it shields

a high E-field around the litz wire and forms a uniform conductor. The inner shield connects

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to the low voltage side which can increase the low voltage conductor radius. According to

eq (1), increasing the conductor radius can efficiently reduce the maximum E-field. In this

case, a concentric cylinder structure is formed. As shown in Fig. 100(a), the E-field

distributes more uniformly inside the transformer. However, because of the limited space

between two shields, the maximum field increases over 2 kV/mm. Furthermore, as shown

in Fig. 100(b), the triple point issue caused by shield terminals happens again, so termination

needs to be designed. In addition, considering creepage distance, it is better to not use any

holder to fix shields' position or connect shields. Therefore, manufacturing and installation

processes become complex for the multi-load auxiliary systems.

(a)

(b)

Figure 100. FEM simulation results of (a). plane 6 (b). plane 7 under 5 kV excitation

Table 8 provides a summary of air-insulated designs discussed above. The method I is a

basic design without any shielding technique. It forms non-uniform conductor structures

and reaches the maximum E-field of 2 kV/mm under 5 kV excitation. To solve the

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nonuniformly distributed E-filed, method IV introduces two shields connected to high and

low voltage sides to form a concentric cylinder structure. This method reshapes the E-field

distribution inside the transformer but cannot meet the desired voltage target due to the triple

point issue at shield terminals. By setting a shield to a floating potential can solve the triple

point issue, which is realized by method III. However, this method requires accurate shield

position, which increases the difficulty of installation. Method II also has an insulation

problem. It utilizes the silicone layer of insulated wire as insulation media by adding a high

voltage conductive shield. However, due to abrupt material change at shield terminals, the

E-field at shied terminals excesses air breakdown field, so this method cannot be applied.

Table 8. Summary of Insulation Design with Air

Insulation

Design

Insulation

Capability Termination Manufacturability

I Relatively high Not required Easy 1 pF

II Low (without

termination) Required

Easy (without

termination) N/A

III Moderate Not Required Relatively hard N/A

IV Relatively high

(with termination) Required Hard N/A

Overall, air-insulated solutions are able to achieve relatively low PDIV but small

coupling capacitance with the designed transformer. Sharp core edges and inaccurate

conductor positions can harm PDIV. The additional conductive shield cannot bring obvious

benefits on insulation capability but will increase difficulty during assembly.

4.3 Silicone-Insulated Solutions

In order to further increase PDIV without changing transformer design, insulation media

needs to be changed. Solid materials such as epoxy and silicone become good candidates.

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Table 9 lists a few material options. From the table, all materials have similar voltage

strength but different relative permittivity, thermal conductivity, and viscosity. Considering

value and manufacturability in the lab, small relative permittivity and low viscosity

features are desired. Thus, SilGel612 from Wacker is selected. Then, in the following

sections, different design solutions will be discussed based on the same material. The design

target is 15 kV and the critical E-field is 8 kV/mm.

Table 9. Potting Materials Parameters

Manufacturer Part

Number

Voltage

Strength

Relative

Permittivity

Thermal

Conductivity Viscosity

Quantum

Silicones

Qsil 553

LV 18 kV/mm 3.12@10kHz 0.65 W/m*K 4000 cps

Epoxies 20-1634 17.72

kV/mm 3.1@1kHz 1.9 W/m*K 30000 cps

Epoxies

20-

1710/20-

1715

18 kV/mm

2.7@60Hz 1.9 W/m*K 6500 cps

Wacker SilGel612 23 kV/mm 2.7@50Hz 0.2 W/m*K 1000 cps

DOWSIL TC-4605

HLV 24 kV/mm 4.12@100K 1 W/m*K 2900 cps

Creative

Material 116-04A 20 kV/mm 4.3@60Hz 2.63 W/m*K 2000 cps

4.3.1 Solution V: Partially Potted Core

Figure 96 offers the first silicone-based design. This method completely pots core and

litz wire. The primary side wire is located at the center of the potting structure. An only a

small portion is potted in silicone and the majority is exposed to the air. As the simulation

result shown in Fig. 102(a), under 15 kV excitation, the highest E-field occurs around the

conductor inside the insulated wire because the dielectric constant of silicone rubber is

similar to the selected silicone’s and primary side winding is connected to GND. Although

the maximum E-field does not exceed 8 kV/mm in silicone, due to abrupt dielectric material

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change, as shown in Fig. 102(b), the E-field in the air is closed to the junction of air, silicone,

and primary side wire is higher than the breakdown field of air. Thus, this method cannot

be applied to achieve a 15 kV PD-free target unless termination is designed. However, since

the majority of primary side wire is in the air, this design can achieve Ccm of 1.43 pF at 10

kHz, which is smaller than the Ccm value generated by other silicone-insulated solutions.

Figure 101. CAD model of an isolated transformer with partially potted structure.

(a)

(b)

84

Figure 102. FEM simulation result of (a). plane 8 (b) plane 9 under 15 kV excitation

4.3.2 Solution VI: Potted Core with Stress Cone Terminals

As mentioned in previous methods, the abrupt dielectric material change will induce high

E-field stress at the interface in the air as shown in Fig. 102(b). Thus, termination needs to

be designed at the ends of the primary side wire, where they are going out from silicone

potting material. Therefore, solution VI introduces stress-cone structure as terminations

shown in Fig. 103. To simplify the manufacturing process, the stress-cone structures are

made of the same potting material. Inside the silicone potted structure, E-field distribution

for this design is the same as shown in Fig. 102(a), but unlike the previous method, from

the side view, the maximum E-field in the air at the junction point of three materials is much

reduced and reaches 2.79 kV/mm with cone’s upper radius of 1.8 mm, lower radius of 9

mm and height of 10 mm as shown in Fig. 104. If further increases cone height, the

maximum E-field in the air at the junction point can be further reduced. However, in this

case, the isolated transformer will occupy more space when integrated with other circuits.

Figure 103. CAD model of the isolated transformer with stress cone shape as potting terminals

85


4.3.3 Solution VII: Fully Potted Transformer

Although the previous method solves the E-field problem at the junction of different

dielectric materials and can meet the design target of 15 kV, due to additional terminations,

the geometry of the potted transformer becomes irregular, so it increases the integration

difficulty with other circuitries. Therefore, improving the overall geometry of the potted

transformer while maintaining insulation capability is important. To achieve so, this design

solution uses silicone as the main insulation media, so the majority portion of the primary

side wire is potted in silicone gel as shown in Fig. 105. The primary side wire forms a local

loop inside the potting structure to ensure the insulation capability between low and high

voltage sides. When the primary side wire comes out from the silicone gel, two terminals

are tightly placed together to reduce the EMI problems as well as loop inductance.

The E-field simulation result with 15 kV excitation is shown in Fig. 106. Due to the

winding pattern of the primary side wire, a low voltage shield is formed at the outer side

of the potted structure. Thus, the differential voltage is sustained by silicone gel only.

Within silicone gel, the maximum E-field does not exceed the critical field value of 8

kV/mm. Outside of the potted structure in the air, the maximum E-field keeps below 1

kV/mm, so there is no triple point issue in this design. Thus, this design can maintain high

insulation capability without any termination required. However, one thing that needs to

be noticed for this design is that the potential for silicone housing is floating. In a real

application, to ensure insulation ability between the isolated power supply and driving

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circuitries, an extra-high voltage shielding layer needs to be added to the potted housing,

especially the surface closed to the high voltage side of the auxiliary power supply.

Figure 105. CAD model of fully potted isolated transformer


4.3.4 Solution VIII: Mixed Dielectric Materials

In silicone potted solutions, shielding techniques can also be applied. Fig. 107 presents

the last design using mixed dielectric materials. In this design, the potted structure is a

concentric cylinder and a conductive shield is added to the inner side. To utilize the voltage

strength of silicone, the shield is connected to the low voltage side, which is on the same

potential as the primary side wire, so there is no voltage difference between the shield and

the primary side wire. In this case, the assembly for the primary side wire is much easier

compared to other potted solutions because the primary side does not need to be potted. As

the result shown in Fig. 108(a), the highest field inside silicone occurs around the litz wire

bending points, but it is still below the critical field value. However, from Fig. 108(b), in

this design, at the joint of three materials, air experiences high field stress, which is the same

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problem as other designs that connects shield to a fixed voltage. Thus, this design cannot

meet the design target of 15 kV without an extra termination design.

Figure 107. CAD model of the isolated transformer with mixed dielectric materials

(a)

(b)

Figure 108. FEM simulation result of (a). plane 12 (b). plane 13 under 15 kV excitation

Table 10 provides a summary of silicone-insulated solutions. From an insulation point

of view, method V and VIII cannot meet the 15 kV PD-free target due to the triple point

issue unless extra terminations are designed, but this could increase difficulty during

manufacturing. Method VI uses a stress-cone shape made of silicone as terminations to offer

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a smooth field transition, so it is able to achieve a PDIV of 15 kV, but due to irregular shape,

this design is hard to standoff by itself and to integrate with other circuitries. Method VII

fully pots the transformer to keep high insulation voltage and regular shape, so it can easily

achieve the design target. However, due to the increase dielectric constant value, silicone

potted designs have a larger Ccm value than air-insulated designs, but it is still below 5 pF,

which meets the design requirement. Additionally, the Ccm value is proportional to the

percentage of primary side wire that is potted in silicone, so the Ccm value of method V is

much smaller than method VIII’s.

Table 10. Summary of Insulation Design with Silicone

Insulation

Design

Insulation

Capability Termination Manufacturability

V Low Required Easy 1.48 pF

VI High Not required Relatively easy 1.84 pF

VII High Not required Easy 2.22 pF

VIII Relatively low Required Relatively easy N/A

4.4 Test Results

This section will mainly show the insulated test results for design method I and VII as

well as measured values for the two designs. The manufacturing process and hardware

prototypes for silicone-insulated design will be shown first.

4.4.1 Manufacturing Process of Silicone-insulated Solution

For silicone-insulated solutions, reducing the number of voids inside silicone is

important because air gaps can harm insulation capability. Thus, the potting process

becomes critical as it determines if the sample can achieve the designed voltage.

89

Before starting potting, a set of fixtures to hold receiving side boards needs to be

designed. To ensure the hardware to stay in the middle of the potted structure, two fixtures

placed on the bottom and top of the hardware are designed as shown in Fig. 109(a) and (b).

Both of them have a hole at the center to allow the primary side to go through and an

actuated structure on the left to keep the primary side wire a center distance away from the

core and PCBs. Furthermore, to ensure the primary side wire to stay at the center of PCBs

and cores, a convex structure is designed on both top and bottom fixture. Fig. 109(c) shows

the housing with holes used for wires to come out.

(a)

(b)

(c)

Figure 109. 3D printed fixtures for silicone-insulated design including (a). bottom supporter (b). top

supporter and (c) potting housing

After finishing the design of the fixture, the next step is to put everything inside. Then as

shown in Fig. 110, RTV is applied around the slots on silicone housing to avoid the potting

material leaking out. Before start potting, RTV should be fully cured.

90

Figure 110. Receiving side hardware in a 3D printed fixture with RTV applied at terminals

During the manufacturing process, material preparation is the first step. Silgel 612 is

made of two materials, so when using it, the two materials need to be mixed with a ratio of

1:1. While stirring materials, air bubbles appear as shown in Fig. 112(a). To reduce the

number of air bubbles in the final sample, vacuuming the mixed material first is necessary

as shown in Fig. 111. After a few minutes, the air bubbles are eliminated as shown in Fig.

112(b), so this material is ready to be used.

Figure 111. Mixing material in the vacuum chamber

91

(a)

(b)

Figure 112. Mixing material (a) before vacuum (b) after vacuum

Since the viscosity of Silgel 612 is not too low, it is hard to eliminate the voids at the

bottom of PCBs if all materials are poured into housing at once. Therefore, every time a

small amount of material is poured into the housing as shown in Fig. 113. Then, the

sample needs to be put in a vacuum chamber for tense of minutes. As shown in Fig. 114,

during a vacuum, a heavy object can be placed on the top of the sample to give additional

force to let air bubbles come out, but this step is optional. During the vacuum period, air

pressure needs to be adjusted depending on air bubble status. Repeat these few steps until

the sample is full of potting material.

Figure 113. Sample with small amount of potting materiel

92

Figure 114. Potted sample in the vacuum chamber

The last step is to put the potted sample in the oven as shown in Fig. 115 with the

temperature around 60 ℃ to fasten the curing process.

Figure 115. Potted sample in the oven

The final product is shown in Fig. 116. Although each receiving side is potted

separately, a multi-load driving system with a single wire on the primary side is still

achievable. As shown in Fig. 117, each potted receiving side circuitry is connected to a

PCB adaptor and all PCB adaptors are connected by a shielded cable. The shielded cable

has an inner conductor connected to the positive terminal of the current bus and the outer

conductor is connected to the negative terminal of the current bus, which is the return

93

path for the current bus. Thus, the return path is evenly wrapped around the current path

that flows to receiving side circuitries. In this case, the EMI issue is eliminated.

Figure 116. Hardware prototype of potted receiving side circuity

Figure 117. APS setup for multiple potted receiving side circuitries

94

4.4.2 Insulation Test Verification

The partial discharge (PD) test is operated with the complete receiving side circuitry

including transformer and PCBs. As shown in Fig. 118, the sample is connected to a 60 Hz

ac source with primary side wire shorted and connected to low voltage side and output wires

shorted and connected to the high voltage side. As shown in Fig. 119, an HFCT and a PD

detector are used to measure PDIV.

Figure 118. PD Test Setup

Figure 119. Setup configuration for PD test

The PDIV results of the air-insulated solution are shown in Fig. 120 and Fig. 121

measured by HFCT and PD detector respectively. According to Fig. 121, no discharge

happens at 5.8 kV with the threshold discharge level of 10 pC, which matches with the result

95

measured by the HFCT. However, since the setups are not identical for every experiment,

the measured PDIV could vary a little bit. Overall, both results indicate the design reaches

the PDIV target of 5 kV. Fig. 122 and Fig. 123 show the measured PDIV for silicone-

insulated design and both of them have similar results and reach the design target of 15 kV.

For silicone-insulated solution, the average accumulated charge can keep around 10 pF

once reaches the threshold discharge level but the air-insulated design cannot due to the

dielectric material features. Thus, the silicone-insulated solution has a more stable and

reliable performance than the air-insulated design. Although PDIV for the silicone-

insulated solution is 16.4 kV peak, when the excitation voltage increases over 20 kV, the

discharge value is only 30 pC.

Figure 120. PDIV for the air-insulated solution measured by HFCT

Figure 121. PDIV for the air-insulated solution measured by PD detector

96

Figure 122. PDIV for the silicone-insulated solution measured by HFCT

Figure 123.PDIV for the silicone-insulated solution measured by PD detector

Figure 124. Partial discharge condition for the silicone-insulated solution with 20.4 kV excitation

97

4.4.3 Thermal Test Verification

Figure 125 shows the thermal result for potted design under steady-state operation with

a total power of 20 W. This test is operated under natural convection cooling for 30 minutes.

The surface temperature of potted housing is 28 ℃ and the primary side wire at the top

surface of potted housing is 42 ℃. From the calculation, the maximum temperature inside

silicone is around 67 ℃, which is much below the maximum temperature requirements for

all circuit components.

Figure 125. The thermal test result of potted receiving side circuitry

4.4.4 Verification

Impedance analyzer Agilent 16047E is used to measure the coupling capacitance for the

designed APS. As shown in Fig. 126, the Ccm value for the transformer and boards together

is 1.86 pF. Compared to the measured Ccm value in the previous chapter, the coupling

between the primary side wire and PCBs introduces a large capacitance. This could also be

verified by the measurement results for the silicone-insulated design shown in Fig. 127 and

Fig. 128. Due to larger relative permittivity, the silicone-insulated design has a larger Ccm

value. With the transformer only, the Ccm is 2.27 pF, which matches the simulation result

and predicted value calculated by the developed model. With the competed receiving side,

the Ccm value increases to 3.61 pF.

98

Figure 126. result for air-insulated design with the completed receiving side

Figure 127. result for silicone-insulated design with transformer only

99

Figure 128. result for silicone-insulated design with the completed receiving side

4.5 Summary

This chapter using the designed APS as an example offers a list of insulation design

ideas by implementing air and silicone as dielectric materials and shielding techniques.

To analyze the insulation performance for each solution, an E-field simulation using

Maxwell is operated. Based on simulation results, all air-insulated solution has lower

insulation capability than the silicone-insulated solution, but due to smaller dielectric

constant value, the air-insulated solution has a smaller value. For the designed APS,

most shielding techniques cannot improve the insulation performance because a shield

with a fixed potential will introduce a triple point problem unless additional termination

is designed. Shield with a floating potential can eliminate such a problem, but it cannot

greatly increase PDIV. In addition, it has high requirements for the manufacturing and

installation process. Thus, considering manufacturability, insulation performance, and

Ccm value, two designs are implemented in hardware. Air-insulated design using the

method I is built and tested. It can achieve a PDIV of 5.4 kV with Ccm of 1.1 pF with

transformer only and 1.86 pF with transformer and PCBs together. Another design

adopting method VII achieves PDIV of 16.4 kV and Ccm of 2.27 pF with transformer and

3.6 pF with the completed receiving side circuitry. For both cases, experiment results

100

match well with simulation and calculation results. Thus, the model built in the previous

chapter is verified. All design methods discussed in this chapter can be applied to other

applications.

101

Chapter 5

System Test Results

After verifying the standalone performance of APS, the next step is to evaluate APS

performance in the system. Since one of the applications for designed APS is power

electronics building block (PEBB), a MV converter system built in CPES, the system test

for APS is conducted mainly in PEBB converter. In PEBB, the designed APS is used to

power gate drivers and sensors. In addition, it works with a wireless power transfer (WPT)

converter together to form the complete auxiliary system. Thus, in this chapter, all

experiment results related to the auxiliary power system and MV converter will be shown.

5.1 Test With WPT

Before testing in MV converter, the functionality and reliability tests with WPT need to

be conducted first. Fig. 129 shows the test setup of the two-stage auxiliary power network.

The test is operated with an input voltage of 48 V and an output voltage of 24 V with an

output power of 40 W total. During the test, resistors are used as driving loads.

Figure 129. Block diagram of auxiliary power system

During transient, the output voltage is expected to be smooth without any voltage spikes,

so the driving load will not be damaged. As shown in Fig. 130 and Fig. 131, during turn-

on and turn-off periods, there is no voltage overshoot or undershoot for both WPT and

102

APS. During startup, WPT will be power first. After output voltage of WPT reaching 35

V, APS starts to work and rises output voltage gradually. During the turn-off period, WPT

will lose power first and the output voltage will be clamped by under-voltage protection.

Then the output voltages of both WPT and APS will drop together. Overall, during the

transient mode, both driving loads are able to gain or lose power simultaneously. [50]

Figure 130. Auxiliary power system’s startup performance

Figure 131. Auxiliary power system’s turn-off performance

103

During a faulty load condition, the auxiliary power network still has stable performance.

As shown in Fig. 132, when a short-circuit happens to the second load, the corresponding

output voltage drops without interfering with other load operations. In the open-circuit

condition shown in Fig. 133, the APS is still able to respond fast. Each receiving side is

working independently, so in a real application, when one load has a failure, other loads

will not be shut down immediately. In short-circuit or open-circuit tests, since WPT is an

unregulated converter, the output voltage will change slightly but this will not affect the

overall auxiliary power network performance because APS has a wide input range with a

maximum input voltage of 60 V.

Figure 132. Auxiliary power system’s short-circuit response

Figure 133. Auxiliary power system’s open-circuit response

104

5.2 Tests in MV Converters

Next, before connecting the designed APS to a real system, reliability performance in

the MV system needs to be verified. Thus, as shown in Fig. 134 and Fig. 135, a 6-kV buck

test is conducted first. For safety purposes, the bottom switch is powered by a commercial

power supply, and the top switch is powered up designed APS. As the result shown in Fig.

136, the designed APS is able to supply constant voltage to the gate driver with reference

voltage connected to the jumping node.

Figure 134. Buck test configuration

Figure 135. Hardware setup for buck test

Gate Driver

GDPS

Concept

Power Supply

Gate

Driver

Vo

Vout

iL

Vjumping

+

-

Vin

+

-

105

Figure 136. Operating waveform of 6 kV buck configuration

According to previous results, the designed APS has stable performance in both low

voltage and medium voltage systems. Finally, the APS can be assembled in a PEBB

converter. As shown in Fig. 137 and Fig. 138, the receiving side circuit of the designed

APS is integrated with sensors and gate drivers. For insulation and system mechanical

stability purposes, a transformer housing is designed to ensure the transformer position. As

shown in Fig. 139, the designed APS is installed in PEBB. Overall gate drivers and sensors

are able to gain a constant power during the test, which verifies the APS performance in

the MV converter.

(a)

106

(b)

Figure 137. CPES designed sensor with integrated receiving side circuit (a) top side (b) bottom side of

design sensor

Figure 138. CPES designed gate driver with integrated receiving side circuit

Figure 139. Hardware setup of APS in PEBB

107

Figure 140 and 141 show the thermal test results of APS in PEBB. After hours of 6 kV

continuous test, the primary side of APS has a maximum temperature of around 60

without any forced air-cooling. The embedded secondary side has a similar temperature.

Thus, there is no thermal issue for designed APS. To be noticed, since the system setup is

different from than the bench top setup, the value on the secondary side is changed to

be 40 nF.

Figure 140. Primary side thermal result in PEBB system

Figure 141. Secondary side thermal result in PEBB system

108

Chapter 6

Conclusion

This thesis proposes an auxiliary power supply solution that has multi-channel, high

insulation capability, small voltage, and ultra-low coupling capacitance.

The proposed APS uses the LCCL-LC converter to realize the current source

transformation. With series-connected receiving sides, multi-load driving ability is easily

achieved. By adding a current-fed switching network with a hysteresis controller, a

constant output voltage under different load conditions is achieved. Also, the circuit is

immune to faulty load conditions and each receiving side is able to operate independently.

However, the additional feedback network changes the equivalent load resistance, which

brings the challenge to ZVS design. Furthermore, in a real application, the load numbers

and distance between the sending side and receiving side circuitries, which will induce

parasitic inductance, are uncertain. Thus, two additional unknown parameters are

introduced in the APS circuit design. With traditional LCCL-LC design procedure, the

ZVS realization condition has low tolerance on the change of load numbers and parasitic

inductance. Thus, a new design methodology is proposed which can guarantee ZVS

regardless of load number and parasitic inductance. The new method simplifies the ZVS

design procedure by creating constant input impedance which is only determined by three

components. Test results are provided to verify ZVS realization.

The transformer is the most crucial component in the APS as it determines PDIV, the

overall volume, and coupling capacitance. To achieve PDIV of 5 kV, transformer volume

under 3.6 , and of 1 pF, a new transformer optimization based on these three

criteria is specifically provided. New modeling with the compact winding method is

proposed and verified by simulation results. In the end, a transformer with an inner radius

of 7.5 mm, an outer radius of 12.5 mm, and a height of 7 mm with a turn ratio of 1:5 is

designed. To achieve minimum losses, the switching frequency is determined to be 1 MHz.

109

Based on the designed transformer, different insulation methods including different

shielding techniques and insulation materials are proposed and analyzed based on 3D FEM

simulation results. For air-insulated solutions, adding a floating potential shield can

improve E-field distribution inside the transformer but manufacturing is difficult. With

fixed potential shields, a server E-field problem will be induced at terminals which will

require additional termination to release the intense E-field distribution. However, this will

decrease the flexibility of the insulated wire during the installation process. To further

increase PDIV, solid material, silicone is applied as insulation media in the transformer.

By designing stress cone shape terminals or fully potted transformer, PDIV can be

increased to 15 kV but will increase as well.

The designed APS has stable performance in both standalone tests and system tests. It

is able to respond fast during load transients and has high tolerance on the input voltage

range. The performance in the auxiliary power network and PEBB system have been

verified. There are no electrical or thermal problems during the continuous tests.

Overall, the designed APS is able to achieve multi-load driving ability with a maximum

power of 120 W. The air-insulated receiving side can achieve 6 kV PDIV with of 1.25

pF and power density of 2.2 W/ . It is already embedded with sensors and gate drivers

and used in the PEBB system. The silicone-insulated receiving side can reach a PDIV of

17 kV with of 3.9 pF. It will be incorporated into other MV systems in the future.

110

References

[1]. ABB Communications, “Power electronics: the hidden technology that makes the

modern world run,” press release, May 2013.

[2]. H. Zhang, L. M. Tolbert, B. Ozpineci, “Impact of SiC devices on hybrid electric

and plug-in hybrid electric vehicles,” IEEE Trans. Ind. Appl., vol. 47, no. 2, pp.

912-921, Mar.-Apr. 2011.

[3]. J. Rabkowski, D. Peftitsis, H. P. Nee, “Silicon carbide power transistors- A new

era in power electronics is initiated,” IEEE Ind. Electron. Mag., vol. 6, no. 2, pp.

17- 26, June 2012.

[4]. S. M. Shinde, K. D. Patil, S. S. Khairnar, W. Z. Gandhare, “The role of power

electronics in renewable energy systems research and development,” in Conf.

Emerging Trends in Eng. and Technology, pp. 726-730, Dec. 2009.

[5]. J. Stark, “380V dc power: Shaping the future of data center energy efficiency,”

Data Center Knowledge, June 2015.

[6]. J. Wang et al., "Power Electronics Building Block (PEBB) design based on 1.7

kV SiC MOSFET modules," 2017 IEEE Electric Ship Technologies Symposium

(ESTS), Arlington, VA, 2017, pp. 612-619, doi: 10.1109/ESTS.2017.8069345.

[7]. J. Wang, “Switching-Cycle Control and Sensing Techniques for High-Density

SiC-Based Modular Converter”, PhD. Dissertation, Dep’t. Elect. Eng., Virginia

Tech, Blacksburg, VA, USA, 2017

[8]. J. Millán, P. Godignon, X. Perpiñà, A. Pérez-Tomás and J. Rebollo, "A Survey of

Wide Bandgap Power Semiconductor Devices," in IEEE Transactions on Power

Electronics, vol. 29, no. 5, pp. 2155-2163, May 2014, doi:

10.1109/TPEL.2013.2268900.

[9]. Q. Chen, R. Raju, D. Dong and M. Agamy, "High Frequency Transformer

Insulation in Medium Voltage SiC enabled Air-cooled Solid-State

Transformers," 2018 IEEE Energy Conversion Congress and Exposition (ECCE),

111

Portland, OR, 2018, pp. 2436-24

[10]. V. Nguyen, P. Lefranc and J. Crebier, "Gate Driver Supply Architectures for

Common Mode Conducted EMI Reduction in Series Connection of Multiple

Power Devices," in IEEE Transactions on Power Electronics, vol. 33, no. 12, pp.

10265-10276, Dec. 2018, doi: 10.1109/TPEL.2018.2802204.

[11]. T. Batra, G. Gohil, A. K. Sesham, N. Rodriguez and S. Bhattacharya, "Isolation

design considerations for power supply of medium voltage silicon carbide gate

drivers," 2017 IEEE Energy Conversion Congress and Exposition (ECCE),

Cincinnati, OH, 2017, pp. 2552-2559, doi: 10.1109/ECCE.2017.8096485.

[12]. B. Sun et al., "Two comparison-alternative high temperature PCB-embedded

transformer designs for a 2 W gate driver power supply," 2016 IEEE Energy

Conversion Congress and Exposition (ECCE), Milwaukee, WI, 2016, pp. 1-7, doi:

10.1109/ECCE.2016.7855537.

[13]. R. Perrin et al., "2 MHz high-density integrated power supply for gate driver in

high-temperature applications," 2016 IEEE Applied Power Electronics

Conference and Exposition (APEC), Long Beach, CA, 2016, pp. 524-528, doi:

10.1109/APEC.2016.7467922.

[14]. D. Nicolas, L. Guillaume and M. Stefan, "A 2W, 5MHz, PCB-integration

compatible 2.64cm3 regulated and isolated power supply for gate driver," 2016

18th European Conference on Power Electronics and Applications (EPE'16

ECCE Europe), Karlsruhe, 2016, pp. 1-10, doi: 10.1109/EPE.2016.7695517.

[15]. Isolated 2 W Single Output SM DC-DC Converter, Murata Power Solutions, Oct.

2018. [Online]. Available:

https://www.murata.com/products/productdata/8807031898142/kdc-

nxe2.pdf?1583754813000

[16]. J. Kim, H. Kim, Y. Cho and J. Kim, "Highly isolated power supply design for

gate drivers of the solid state transformer," 2017 Asian Conference on Energy,

Power and Transportation Electrification (ACEPT), Singapore, 2017, pp. 1-5, doi:

10.1109/ACEPT.2017.8168625.

[17]. K. Mainali, S. Madhusoodhanan, A. Tripathi, K. Vechalapu, A. De and S.

Bhattacharya, "Design and evaluation of isolated gate driver power supply for

112

medium voltage converter applications," 2016 IEEE Applied Power Electronics

Conference and Exposition (APEC), Long Beach, CA, 2016, pp. 1632-1639, doi:

10.1109/APEC.2016.7468085.

[18]. A. Christe, M. Petkovic, I. Polanco, M. Utvic and D. Dujic, "Auxiliary submodule

power supply for a medium voltage modular multilevel converter," in CPSS

Transactions on Power Electronics and Applications, vol. 4, no. 3, pp. 204-218,

Sept. 2019, doi: 10.24295/CPSSTPEA.2019.00020.

[19]. L. Zhang et al., "Design Considerations for High-Voltage-Insulated Gate Drive

Power Supply for 10-kV SiC MOSFET Applied in Medium-Voltage Converter,"

in IEEE Transactions on Industrial Electronics, doi: 10.1109/TIE.2020.3000131.

[20]. ISO5125I Data Sheet, Power Integrations, Aug. 2020. [Online]. Available:

https://gate-

driver.power.com/sites/default/files/product_document/data_sheet/ISO5125I.pdf

[21]. D. Rothmund, D. Bortis and J. W. Kolar, "Highly compact isolated gate driver

with ultrafast overcurrent protection for 10 kV SiC MOSFETs," in CPSS

Transactions on Power Electronics and Applications, vol. 3, no. 4, pp. 278-291,

Dec. 2018, doi: 10.24295/CPSSTPEA.2018.00028.

[22]. GvA Power Electronics, “ Highly Insulating DC/DC Converter with 24 kV

Insulation Voltage,” GvA Power Electronics. [Online]. Available:

https://www.gvaleistungselektronik.de/fileadmin/user_upload/IPSS_Flyer_e.pdf.

[Accessed: Jun. 14, 2020].

[23]. A. Tripathi, K. Mainali, S. Madhusoodhanan, A. Yadav, K. Vechalapu and S.

Bhattacharya, "A MV intelligent gate driver for 15kV SiC IGBT and 10kV SiC

MOSFET," 2016 IEEE Applied Power Electronics Conference and Exposition

(APEC), Long Beach, CA, 2016, pp. 2076-2082, doi:

10.1109/APEC.2016.7468153.

[24]. A. Anurag, S. Acharya, Y. Prabowo, G. Gohil and S. Bhattacharya, "Design

Considerations and Development of an Innovative Gate Driver for Medium-

Voltage Power Devices With High $dv/dt$," in IEEE Transactions on Power

Electronics, vol. 34, no. 6, pp. 5256-5267, June 2019, doi:

10.1109/TPEL.2018.2870084.

https://www.gvaleistungselektronik.de/fileadmin/user_upload/IPSS_Flyer_e.pdf

113

[25]. J. Hu, J. Wang, R. Burgos, B. Wen and D. Boroyevich, "High-Density Current-

Transformer Based Gate-Drive Power Supply with Reinforced Isolation for 10 kV

SiC MOSFET Modules," in IEEE Journal of Emerging and Selected Topics in

Power Electronics.

[26]. Preliminary Datasheet GPSS 118-24, GvA Power Electroncis, Mar. 2020.

[Online]. Available: https://www.gva-

leistungselektronik.de/fileadmin/user_upload/DS_P19055_01_Preliminary.pdf

[27]. J. Gottschlich, M. Schäfer, M. Neubert and R. W. De Doncker, "A galvanically

isolated gate driver with low coupling capacitance for medium voltage SiC

MOSFETs," 2016 18th European Conference on Power Electronics and

Applications (EPE'16 ECCE Europe), Karlsruhe, 2016, pp. 1-8, doi:

10.1109/EPE.2016.7695608.

[28]. R. Steiner, P. K. Steimer, F. Krismer and J. W. Kolar, "Contactless energy

transmission for an isolated 100W gate driver supply of a medium voltage

converter," 2009 35th Annual Conference of IEEE Industrial Electronics, Porto,

2009, pp. 302-307, doi: 10.1109/IECON.2009.5414939

[29]. C. Marxgut, J. Biela, J. W. Kolar, R. Steiner and P. K. Steimer, "DC-DC

converter for gate power supplies with an optimal air transformer," 2010 Twenty-

Fifth Annual IEEE Applied Power Electronics Conference and Exposition

(APEC), Palm Springs, CA, 2010, pp. 1865-1870, doi:

10.1109/APEC.2010.5433487.

[30]. V. T. Nguyen and G. Gohil, "Dual-Output Isolated Gate Driver Power Supply for

Medium Voltage Converters using High Frequency Wireless Power Transfer,"

2020 IEEE Applied Power Electronics Conference and Exposition (APEC), New

Orleans, LA, USA, 2020, pp. 1821-1828, doi:

10.1109/APEC39645.2020.9124146.

[31]. J. Pan, F. Qi, H. Cai and L. Xu, "Efficiency and electromagnetic interference

analysis of wireless power transfer for high voltage gate driver application," 2016

IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI,

2016, pp. 1-5, doi: 10.1109/ECCE.2016.7855069.

114

[32]. K. Kusaka, K. Orikawa, J. Itoh, K. Morita and K. Hirao, "Isolation system with

wireless power transfer for multiple gate driver supplies of a medium voltage

inverter," 2014 International Power Electronics Conference (IPEC-Hiroshima

2014 - ECCE ASIA), Hiroshima, 2014, pp. 191-198, doi:

10.1109/IPEC.2014.6869579.

[33]. O. C. Spro et al., "Optimized Design of Multi-MHz Frequency Isolated Auxiliary

Power Supply for Gate Drivers in Medium-Voltage Converters," in IEEE

Transactions on Power Electronics, vol. 35, no. 9, pp. 9494-9509, Sept. 2020, doi:

10.1109/TPEL.2020.2972977.

[34]. X. Zhang et al., "A Gate Drive With Power Over Fiber-Based Isolated Power

Supply and Comprehensive Protection Functions for 15-kV SiC MOSFET," in

IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 4, no.

3, pp. 946-955, Sept. 2016, doi: 10.1109/JESTPE.2016.2586107.

[35]. J. Feng, M. Fu, Q. Li and F. C. Lee, "Resonant converter with coupling and load

independent resonance for omnidirectional wireless power transfer

application," 2017 IEEE Energy Conversion Congress and Exposition (ECCE),

Cincinnati, OH, 2017, pp. 2596-2601.

[36]. W. Zhang and C. C. Mi, "Compensation Topologies of High-Power Wireless

Power Transfer Systems," in IEEE Transactions on Vehicular Technology, vol.

65, no. 6, pp. 4768-4778, June 2016, doi: 10.1109/TVT.2015.2454292.

[37]. N. Yan, J. Hu, J. Wang, D. Dong and R. Burgos, "Design Analysis for Current-

transformer Based High-frequency Auxiliary Power Supply for SiC-based

Medium Voltage Converter Systems," 2020 IEEE Applied Power Electronics

Conference and Exposition (APEC), New Orleans, LA, USA, 2020, pp. 1390-

1397, doi: 10.1109/APEC39645.2020.9124436.

[38]. X. Liang, C. Chen and Y. Zhang, “High Voltage Engineering”, Beijing, China,

2020

[39]. J. Feng, Q. Li and F. C. Lee, "Soft Switching Realization of LCCL-LC Resonant

Converter for Wireless Power Transfer Application," 2019 IEEE Applied Power

Electronics Conference and Exposition (APEC), Anaheim, CA, USA, 2019, pp.

664-670

115

[40]. V. Nguyen, P. Lefranc and J. Crebier, "Gate Driver Supply Architectures for

Common Mode Conducted EMI Reduction in Series Connection of Multiple

Power Devices," in IEEE Transactions on Power Electronics, vol. 33, no. 12, pp.

10265-10276, Dec. 2018, doi: 10.1109/TPEL.2018.2802204.

[41]. K. Nguyen-Duy, Z. Ouyang, A. Knott and M. A. E. Andersen, "Minimization of

the transformer inter-winding parasitic capacitance for modular stacking power

supply applications," 2014 16th European Conference on Power Electronics and

Applications, Lappeenranta, 2014, pp. 1-10, doi: 10.1109/EPE.2014.6910843.

[42]. University of Alabama Online. (2018). [Online]. Available:

http://pleclair.ua.edu/ph106/Homework/HW4_SOLN.pdf

[43]. Material Characteristics (4), Acme Electronics Corporation, Sep. 2020. [Online].

Available: https://www.acme-ferrite.com.tw/investor/m4.pdf

[44]. Material Characteristics (5), Acme Electronics Corporation, Sep. 2020. [Online].

Available: https://www.acme-ferrite.com.tw/investor/m5.pdf

[45]. Mn-Zn soft ferrite cores for high frequency power supplies MaDC-F™, Hitachi

Metal, Mar. 2020. [Online]. Available: http://www.hitachi-

metals.co.jp/products/elec/tel/pdf/madc-f.pdf

[46]. N. Yan, Q. Chen, D. Dong and R. Burgos, “Design of Insulation System in High-

Frequency Auxiliary Power Supply for Medium Voltage Applications”, in 2020

IEEE Energy Conversion Congress & Expo (ECCE), Detroit, MI, USA, Oct. 2020

[in progress].

[47]. J. Hu, “Current-Transformer Based Gate-Drive Power Supply with Reinforced

Isolation”, M.S. thesis, Dept. Elect. Eng., Virginia Tech, Blacksburg, VA, USA,

2018

[48]. C. R. Sullivan, "Computationally efficient winding loss calculation with multiple

windings, arbitrary waveforms, and two-dimensional or three-dimensional field

geometry," in IEEE Transactions on Power Electronics, vol. 16, no. 1, pp. 142-

150, Jan. 2001, doi: 10.1109/63.903999.

[49]. D. Reusch, “Optimizing PCB Layout with eGaN FETs” white paper, 2014.

[Online] Available:

https://www.acme-ferrite.com.tw/investor/m5.pdf

116

http://epcco.com/epc/Portals/0/epc/documents/papers/optimizing%20pcb%20layo

ut%20with%20egan %20fets.pdf

[50]. K. Sun, N. Yan, J. Wang, D. Dong, R. Burgos and D. Boroyevich, "Auxiliary

Power Network Architecture for 10 kV SiC-Based Power Electronics Building

Blocks," 2020 IEEE Applied Power Electronics Conference and Exposition

(APEC), New Orleans, LA, USA, 2020, pp. 1347-1352, doi:

10.1109/APEC39645.2020.9124332.

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