High Efficiency High Voltage Flyback - easii-ic.com
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APPLICATION NOTE
AN-00987-19
HIGH EFFICIENCY HIGH VOLTAGE FLYBACK
By EASII-IC, X-REL Semiconductor
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TABLE OF CONTENTS
1 Introduction ...................................................................................................................................... 4
2 Main Features................................................................................................................................... 4
3 Flyback diagram............................................................................................................................... 5
4 Design consideration ........................................................................................................................ 6
4.1 Start-up .................................................................................................................................. 6
4.2 After start-up of the xtr30014 ................................................................................................ 6
5 Component and characteristics choice ............................................................................................. 7
5.1 Start-Up Phase ....................................................................................................................... 7
5.2 XTR30014 settings ................................................................................................................ 8
5.2.1 XTR30014 characteristics: ........................................................................................ 8
5.2.2 FB voltage ................................................................................................................. 8
5.2.3 SWT resistor .............................................................................................................. 8
5.2.4 SSTR resistor ............................................................................................................. 8
5.2.5 R sense calculation for over current .......................................................................... 9
5.3 Switching MOSFET: xtr20411 ............................................................................................ 10
5.4 Transformer characteristics ................................................................................................. 11
5.5 JFET..................................................................................................................................... 12
5.6 Snubber Network ................................................................................................................. 13
5.7 D_out and D_aux (D1,D2) size ........................................................................................... 13
5.8 COUT calculation ................................................................................................................ 13
6 Power supply Performances and waveforms ................................................................................. 14
6.1 Introduction ......................................................................................................................... 14
6.2 Start-up waveform ............................................................................................................... 14
6.3 Voltage Regulation Accuracy .............................................................................................. 15
6.4 Power-good flag from the XTR30014 ................................................................................. 15
6.5 Load Transient Response ..................................................................................................... 16
6.6 Input Transient Response .................................................................................................... 17
6.7 Output Protection ................................................................................................................. 18
6.7.1 MAX output load protection: Fold back point ........................................................ 18
6.7.2 Secondary protection: short circuit.......................................................................... 20
6.7.3 Secondary protection: Over Voltage on Vout ......................................................... 20
7 Efficiency measurement................................................................................................................. 21
7.1 Efficiency vs ILOAD .............................................................................................................. 21
7.2 Efficiency vs POUT ............................................................................................................... 23
7.3 Efficiency vs VIN ................................................................................................................. 25
8 Vout measurement ......................................................................................................................... 27
8.1 VOUT vs ILOAD....................................................................................................................... 27
8.2 VOUT vs POUT ........................................................................................................................ 29
8.3 VOUT vs VIN .......................................................................................................................... 31
9 Ripple measurement....................................................................................................................... 33
9.1 RIPPLE vs ILOAD .................................................................................................................. 33
9.2 RIPPLE vs VIN ..................................................................................................................... 33
10 Duty cycle measurement ................................................................................................................ 34
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10.1 DUTY CYCLE vs ILOAD ...................................................................................................... 34
10.2 DUTY CYCLE vs VIN ......................................................................................................... 34
11 System design guidelines/Layout recommendation....................................................................... 35
11.1 Design consideration ........................................................................................................... 35
11.2 Typical Flyback Schematic ................................................................................................. 35
11.3 Bill of Material .................................................................................................................... 35
12 Board Photos .................................................................................................................................. 36
12.1 Board drawing ..................................................................................................................... 36
12.2 Thermal photos .................................................................................................................... 36
13 Conclusion ..................................................................................................................................... 37
14 Important Notice & Disclaimer ..................................................................................................... 38
15 Contact Us ...................................................................................................................................... 38
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ABSTRACT
This application note describes how to design and use a high voltage Flyback with the XTR30014,
XTR20411, 2K1208, 1K1210, XTR431 and XTR1N0850. This covers. This application note de-
scribes how the schematic has been built and the measurement result.
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1 INTRODUCTION
This document is application to show a flyback architecture that could be used for high voltage (up to
600V), high out power (<30W) and high temperature (max 175°C).
This application note describes the design of a Flyback power supply able to work in extreme tem-
perature environment. It is designed to accommodate the requirements for markets needed wide range
of input voltage and high temperature environment. These devices are designed to achieve fast transient response, high efficiency, very good thermal per-
formance, and high output voltage accuracy. Its main purpose is to convert a DC Input voltage to DC
regulated output voltage. The power supply provides input and output protections. The rest of the
network is isolates from the output. This power supply limits the transient input voltage and protects
against inrush current at plug in. The secondary side is regulated at 24V in this version. The control-
ler, the PWM XRT30014 from easii-ic, is able to switch up to 1000 kHz and stay the heart of the
power supply.
An evaluation board could be available.
2 MAIN FEATURES
Input: VIN (DC) = 30V to 600V
Output: IOUT = 1.25A; 30W; 24V
Large range of ambient Temperature Range: TEMP = -60 to 175°C
Standard flyback architecture
Output regulated voltage easy to adapt
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3 FLYBACK DIAGRAM
XTR2K1208
XTR2K1208
XTR431
XTR30014
Cout1
X7R
Resr
Cout2
NP0
C30
Cvdd
Cvau
xR
vin
Cpvin
ENABLE
GND
VIN
OCS
HDrv
COMP
VDD
VOUT
VIN
30-600v
Rocs
Cp
vd
d
Rsense
XTR20411V
DD
DR
AIN
SO
UR
CE
IN
GN
D
PV
DD
Normally-ON
SiC jFET
J2
Cvin
VAUX
Normally-ON
SiC jFET
J1Rpvdd
FB
C28 R23 R24
C31
R25
R26+R27
XTR1N0850
ANCA
Rvaux
SWT
Rswt
XTR1N0850
AN CA
VOUT
C17
R9+R6
R11
RLIMOver voltage
protection
D2
D1
Snubber network
R12
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4 DESIGN CONSIDERATION
4.1 Start-up
Maximum voltage for X-REL drivers is less than 80V. In a flyback architecture, during the switching,
an usual driver will see the supply voltage, plus the transformer reflected output voltage, plus voltage
spikes related to leakage inductors. If the input is more than 80V a cascode must be used. Due to this,
an external (non X-REL) switching device is required for the 70V input constraint. We propose the
use a Silicon Carbide normally-ON
In this schematic 2 JFET have been used. One is for the start-up functionality; the second is to “view”
the high voltage for the switching. Indeed the first JFET will be on during the start-up phase and it
will off during normal phase. Without this transistor the circuitry cannot work. Also due to the fact the
transistor is used for the start-up a resistor can be added directly between the drain and power supply
to limit the inrush current.
For the calculation of the resistor see the Start-Up Phase
The PWM controller is also not able to sustain directly the high input voltage (>35V). In order to turn-
around this limitation, the normally ON JFET threshold voltage can be advantageously used.
The capacitor CVIN should be as high as possible compare to the capacitors on VDD & PVDD (CVDD
& CPVDD). Indeed, once the enable upper threshold is reached, the XTR30014 internal LDO turns ON
and will promptly charge capacitors on VDD & PVDD. This fast charge transfer between CVIN and
CVDD makes a fast voltage drop on the PWM VIN voltage. If this input voltage drop is larger than 2V
within few µs, the internal reference of the XTR30014 can be briefly turned-off, so that the full sys-
tem could never start as expected. In order to avoid this, it is recommended to use at least 3.3uF on the
VIN input and about 220nF on VDD & PVDD.
At start-up, when VIN is set, we assume that all capacitors are discharged. The PWM controller is
therefore not supplied, so that VDD remains at zero and both drivers are off. The system will however
be initialized thanks to the internal reverse diode (source to drain) of the upper driver. Indeed, at turns
on, the JFET source is at zero, so that the JFET is strongly ON. A DC current path is created from
VIN, across the transformer primary winding, the JFET, the upper driver body diode, Rlim1 (responsible
for limiting the start-up DC current in the transformer) and CVIN. The Capacitor CVIN will therefore
start charging with an initial rate (V/s) of about VIN /(CVIN*RLim1). When the ENABLE voltage will
pass the XTR30014 ENABLE upper threshold (about 1.5V), the internal LDO will turns on and pro-
vides 5V on VDD. At that moment, the JFET should be about OFF as its source voltage should be
high. Now, the PWM will initiate a soft-start period, with progressively increasing duty cycle. When
the PWM pulse is high, the JFET source is tight to ground across the lower driver (controlled by
BDRV). The transformer primary winding is stocking energy in the magnetic core. When the PWM
pulse goes OFF, the JFET must now be turned as fast as possible. This is the purpose of the upper
driver (controlled by ADRV) thanks to the voltage on CVIN and the diode which is in parallel with
RLIM1.
4.2 After start-up of the xtr30014 During normal working when there is no load on the output, the VOUT is go over the regulation , to limit the ef-
fect an Zener diode (like xtr431) has been added. There is a double effect; the first is to limit the voltage by the
XTR431 and also due to the current that decrease the voltage.
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5 COMPONENT AND CHARACTERISTICS CHOICE
5.1 Start-Up Phase
At plug in, the input voltage charges the input capacitor C2 to C5 and this voltage is applied on the
Transformer primary which is ready to start when the PWM will provide BDrv command.
Few milliseconds later the PWM starts, fed by Q1.
As soon as the PWM runs and Vaux is available, Q1 is going off and XTR3014 is only supply by the
Vaux (24V).
As soon as the voltage on the pin 5 of XTR30014 reaches the upper voltage threshold of the UVLO
logic, the device turns into active mode and start switching smoothly due to the internal soft start.
In order to limit the Inrush current at start up, R3 must be adjusted to provide minimum input voltage
to the XTR30014. This value is specified at 6V.
So, the maximum value for the resistance on VIN is defined by the following equation:
The consumption of the XTR3001X being (in typical) of the order of 3mA. With the margin of 2mA
(for the worst case process and temperature). We obtain a maximum resistance for VIN = 32V with &
5mA current:
So, R3=5.1KΩ
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5.2 XTR30014 settings
The PWM is equipped with lot of functions, here we use it in flyback mode with LDrv permanently
off.
See the datasheet of the XTR30010
http://www.x-relsemi.com/EN/Products/Product/?Ref=XTR30010
5.2.1 XTR30014 characteristics:
VIN: 6V min at start-up then 24V (VAUX) in steady state.
Fsw=50KHz theorical, but 45KHz real due to parasitic capacitor
FB ref=1.2V
Desired Functionality OCPMode PSkipEnbl AsyncEnbl IntlvMode
Boost, buck-boost, flyback modes with LDrv permanently off.
Pulse skipping mode disabled. 0 0 0 0
5.2.2 FB voltage
PWM output controller is regulated on VAUX Feedback voltage.
FB reference is 1.2V so, we set R24 = 100K then R26+R27 (VREF/( VAUX - VREF)) = 5.26K
We set R26 = 3.6K so R27 = 1.69K
5.2.3 SWT resistor
The SWT resistor is the resistor use on the SWT pin to control the slope of the XTR30014 saw tooth.
Following our startup measurement the choice made is 330kohms. If the frequency changes the resis-
tor must be adapted with the startup sequence and also the duty cycle to avoid any stability issue.
5.2.4 SSTR resistor
A resistor could be added on the pin SSTR and GND to decrease the startup time (see the datasheet of
the XTR30010)
XTR30014Cvau
x
GND
VIN
FB
VAUX
R24
R26+R27
1.2V
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5.2.5 R sense calculation for over current
For OCP_MODE=0
With ROCS = 1K; IOCS = 48µA, VTHOCS = 370mV, ŋ=80% I_IN_avg_max=Vout*Iout/VIN_MIN/ŋ = (24*0.5)/0.8/30=0.5A IOCP peak = 2*I_IN_avg_max /Duty_cycle = 2*0.5/0.5 = 2A Assuming margin IOCP peak = 3.2A then, Rsense = (VTHOCS – (IOCS*ROCS))/IOCP=0.107 Ohms So, Rsense=R21=100mΩ
OCSOCP
Timing VTHOCS
OCP Fault
OCPMode
IOCS
Comp
Rsense
Rocs
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5.3 Switching MOSFET: xtr20411
The schematic contains a 40V N-Channel MOSFET instance Q5 in a cascode structure with a 1200V
JFET instance Q3. This cascode aims to accumulate energy in transformer primary.
When Q3 is blocked, to prevent this JFET Drain-Source leakage current from charging the N-Channel
MOSFET Q5 Drain capacitor to a damaging voltage value above 55V damaging definitely the device,
a resistor R12 from Q3 Source to the Ground is present.
R12 value is calculated to insure a Q3 maximum voltage Vgs of -10V when Q3 is blocked and only
the Q3 Drain-Source leakage current is flowing through R12. At ambiant temperature this leakage
current is in the range of 1.0mA which means R12 value must be at least:
R12=10V/1.0mA=10kOhms
When the circuit is at High Temperature 175°C, the leakage current increases towards 1.5mA.
When at 175°C and Q3 blocked, Q5 Vds will be:
Vds=R12*Ileak=10k*1.5mA=15V
To be accurate you have also to tweak R12 value to what this resistance value is at 175°C and verify
Q5 Vds will not exceed XTR2N20411 Maximum Absolute Ratings.JFET Drain-source voltage cycle.
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5.4 Transformer characteristics
The transformer has been choiced to fit the VIN 600V characteristics.
Electrical Specification@25C:
Inductance (1-3): 3mH ±12% @ 100kHz with 0.1V
Leakage inductance (1-3): 50µH Max @ 100kHz with 0.1V with all pins shorted
RDC: (1-3): 3.35Ω Max
(4-5): 0.40Ω Max
(6-10): 50.0mΩ Max
Turn Ratio: @100kHz with 0.1V
(1-3): (4-5)=1:0.12±5%
(1-3): (6-10)=1:0.12±5%
Hipot: Pins (1-3) to (6-10): 2500VDC for 2 seconds @0.5mA
1
2
3
4
5
6
10
SEC
PRI
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5.5 JFET
The choice of the JFET is depending of transformer.
The Jfet is depend on the voltage peak, the peak voltage must be lower than the voltage breakdown of
the JFET.
The purpose is this Jfet is to use as a cascode for the xtr20411( for the J2), the maximum voltage on
the XTR201411 is 35V on the drain-source.
Vds_max = Vin_max + Vout/Nr + Vspike = 600+24/0.12=800Vmax
Assuming Vspike = 100V with margin,
Vds_max = 600+24/0.12+100 =900Vmax
The JFET (XTR1208) used is a 1200V Breakdown voltage.
The following plot shows the drain-source voltage and the image of drain current of Q3 (JFET) for
one complete cycle. The different phases of the cycle are:
1. Conducting phase
2. Off phase with two parts
a. Energy transfer phase
b. Dead time
No relevant overshoot detected on JFET for this condition
a b
1
2
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5.6 Snubber Network
This schematic uses and RDC Snubber network in order to limit destructive overvoltage for the cas-
code.
Indeed, in switched mode power supplies, there is a high dV/dt across the FET when it switches off.
This is caused by abruptly cutting off the current through the primary inductance of the transformer.
This high dV/dt is undesirable for a number of reasons:
High switching losses in the FET
Cause EMI Emission
High output ripple
This high dV/dt can be reduced by a clamp network/Snubber.
There is a snubber network on the primary side with a D3, R7, C2 and also a pcb footprint snubber
across the secondary diode D1 and D2.
As the JFET use in this DC/DC as a large Vds capability we do not need to be tied, as energy losses
impact the efficiency. This snubber must be perfectly appaired with the FET to damp or lower the
Vspike.
5.7 D_out and D_aux (D1,D2) size
The choice of the Diode is related to the maximum voltage on the anode-cathode.
VBREAKDOWN_MAX = Vout +VIN_max*Nr=24+600*0.12=96V
IOUT_MAX = 1.3A
So D1 =D2 =XTR1N850
5.8 COUT calculation
We want Vripple = 600mV max
COUT = IOUT_PEAK*dt/dv
IOUT_PEAK = IIN_PEAK/Nr = 2/0.12 = 17A
Duty_cy = 40% then dt = 0.4/50E3 = 8µs
COUT = 17*8E-6/600E-3 = 226µF
1K1210
R2 C7
D3
VDRAIN J2
VIN
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6 POWER SUPPLY PERFORMANCES AND WAVEFORMS
6.1 Introduction
Functional tests to ensure full reliability have been done with DC input voltage from 30V to 600V
with an output current of 1200mA and 24V on the output (30W) over an ambient temperature range
from -60°C to +175°C.
6.2 Start-up waveform
The following plot shows the voltage on (Vin, Vout, Pgood, JFET_Drain) during start-up phase. It can
be seen from the plots that it takes around 240ms for the power supply to regulate.
Red arrow shows transition when Q1 is going off and Vaux is going on.
Conditions: VIN=150V noLoad
Yellow: Vin =Vaux; green: Vout ; Blue : Pgood
Time=100ms/ div Time=20ms/div
Conditions: VIN=600V ILOAD=1A
Yellow: Vin =Vaux; green: Vout ; Blue : Pgood
Time=100ms/ div Time=20ms/div
Time delay after plug in:
Before starting the DC/DC converters and to avoid disturbing the line during plug in, the power sup-
ply should wait a minimum time, at least 240ms. This is to ensure that all of the input storage capaci-
tors have charged up to the full available source power supply voltage before starting up. This is done
by adding R3 and C22 on the VIN pin. The following plots show the timing between the plug in and
the 24V output at full load with 30V and 600V input voltage.
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6.3 Voltage Regulation Accuracy
Due to continuous improvement CAO, systems require good voltage accuracy to operate properly.
Every system documentation specifies the voltage tolerance over the entire operating temperature
range. To keep a good level of accuracy, components are selected in accordance, and the routing of
the printed circuit board must be carefully realized. The variations of the application, like the input
voltage variations, temperature swings, and fast changes in the load must take account too.
The following graphs show the output voltage regulation accuracy.
6.4 Power-good flag from the XTR30014
PGood is an active-HIGH output flag indicating that the DC-DC output is within a given range of val-
ues and that no over current event is present. Output voltage sensing is performed on node FB. When-
ever FB goes outside the range 90-120% of VREF (1.2V), PGood is immediately pulled down. In case
of an overvoltage on FB (>120%Vref), the high-side output driver (HDrv) is turned off until FB
reaches 90% of VREF, in which case the controller enters again into normal operation. Once that FB
goes back above 90% of VREF, the PGood flag remains low for a period of about 256 clock cycles.
The following graphs show the power good flag operating:
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6.5 Load Transient Response
As systems are more and more speed and solicited nowadays, consumption is very impacted and so
the load variation. That is why it is important to consider AC transient performance. A DC/DC con-
verter with a fast-transient response is important to ensure the system is functional in all specified
conditions.
The following graphs show the output load transient response.
Conditions: VIN=400V IOUT transition from 0.4A to 1A
Yellow: VAUX green: VOUT
Conditions: VIN=600V IOUT transition from 0.4A to 1A
Yellow: VAUX green: VOUT
Conditions: VIN=600V IOUT transition 0.4A to 0.8A
Yellow: VAUX green: VOUT
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6.6 Input Transient Response
As for the load transient the power supply should be able to operate even if the acceptable input volt-
age in going up or down for any reason.
The following graphs show the output response vs input line variation.
Conditions:
ILOAD =0.5A VIN 100V to 500V ILOAD=1A VIN 400V to 600V
Yellow: VAUX green: VOUT Pink : VIN Yellow: VAUX green: VOUT Pink : VIN
Conditions:
ILOAD=1.2A VIN 200V to 600V ILOAD=1.2A VIN 600V to 200V
Yellow: VAUX green: VOUT Pink : VIN Yellow: VAUX green: VOUT Pink : VIN
Conditions: ILOAD=1A VIN 120V to 50V
Yellow: VAUX green: VOUT Pink : VIN
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6.7 Output Protection
6.7.1 MAX output load protection: Fold back point
XTR30014 is equipped with the programmable over-current protection level function (OCP). If cor-
rectly setting, that means the power supply cannot be damaged. As soon as the over current disappears
on output, the power supply will go back to the 24V regulated voltage.
Concerning power supply the fold back point is well known and is where the load on the output of the
power supply is increased until the Power supply can no longer regulate and the voltage starts to fall.
The reason is that the drain current of the JFET(Q2) is so large (maximum duty cycle reached) that the
current limit threshold is reached. This limits the energy that can be stored in the transformer TRF1
and hence the energy that can be transferred to the secondary side. The fold back point is a measure of
the max output power of the power supply and represents the worst-case load on the power supply.
The following graphs show the maximum output response depending on condition of input voltage,
load and temperature.
Example of short-circuit detection
Full range Zoom on the left side
Yellow: VAUX; green: VOUT ; blue : SSTR ; pink : HDRV
Zoom on the right side with restart
Yellow: VAUX; green: VOUT ; blue : SSTR ; pink : HDRV
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Yellow: VAUX; green: VOUT ; blue : SSTR ; Yellow: VAUX; green: VOUT ; blue : SSTR
pink : VDD pink :CK
Zoom on previous to measure the frequency
Yellow: VAUX; green: VOUT ; blue : SSTR ; pink :CK
The frequency clock is 45.5kHz.
The number of CK period is 16100; that means the restart will be happened 353.8ms as at is on the
first snapshot. The starting point is when the HDRV is off and the final point is the start of SSTR
slope. That could be seen on the first graph.
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6.7.2 Secondary protection: short circuit
At short circuit and general safety reasons requirements, it has been ensured that no component can
overheat or burn in case of short circuit. At short circuit the power supply reaches the fold back point
and provides a defined maximum current. So, the power supply cannot be damaged. As soon as the
short circuit is removed from the output, the power supply will go back to the 24V regulated voltage.
6.7.3 Secondary protection: Over Voltage on VOUT
In case of an overvoltage on output, active XTR431 shunt regulator is able to pull down and hold the
output voltage to a reasonable and acceptable value. This is the case when no load is applied.
The setting method is given in its datasheet:
In the standard shunt regulator, the output voltage can be obtained from:
We set VOUT=VKA=26.5V
VREF=2.55V
We set R2=10KΩ => R1=94KΩ
We set VIN max=30V and set IKA=10mA => Rlim = (VIN-VOUT) / IKA =350Ω (P=35mW)
Results are represented below:
Yellow : Vaux ; Green : VIN ; Blu : VOUT ; Pink : VREF
VIN=600V; No load
Without XTR431 With XTR431
XTR431
Rlim
R1
R2
P24V_SEC
Cout
P26V5_SECIKA
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7 EFFICIENCY MEASUREMENT
7.1 Efficiency vs ILOAD (with different VIN)
0
10
20
30
40
50
60
70
80
90
100
0 0,5 1
Eff
icie
nc
y (
%)
Iload (A)
EFFICIENCY Vs ILOAD T=-60°C
30
50
150
400
600
0
10
20
30
40
50
60
70
80
90
100
0 0,5 1
Eff
icie
nc
y (
%)
Iload (A)
EFFICIENCY Vs ILOAD T=25°C
30
50
150
400
600
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0
10
20
30
40
50
60
70
80
90
100
0 0,5 1
Eff
icie
nc
y (
%)
Iload (A)
EFFICIENCY Vs ILOAD T=175°C
30
50
150
400
600
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7.2 Efficiency vs POUT (with different VIN)
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30
Eff
icie
nc
y (
%)
POUT (W)
EFFICIENCY Vs POUT T=-60°C
30
50
150
400
600
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30
Eff
icie
nc
y (
%)
POUT (W)
EFFICIENCY Vs POUT T=25°C
30
50
150
400
600
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0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30
Eff
icie
nc
y (
%)
POUT (W)
EFFICIENCY Vs POUT T=175°C
30
50
150
400
600
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7.3 Efficiency vs VIN (with different ILOAD)
50
55
60
65
70
75
80
85
90
95
100
0 100 200 300 400 500 600
Eff
icie
nc
y (
%)
VIN (V)
EFFICIENCY Vs VIN T=-60°C
0.1
0.2
0.5
1
1.3
50
55
60
65
70
75
80
85
90
95
100
0 100 200 300 400 500 600
Eff
icie
nc
y (
%)
VIN (V)
EFFICIENCY Vs VIN T=25°C
0.1
0.2
0.5
1
1.3
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40
50
60
70
80
90
100
0 100 200 300 400 500 600
Eff
icie
nc
y (
%)
VIN (V)
EFFICIENCY Vs VIN T=175°C
0.1
0.2
0.5
1
1.3
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8 VOUT MEASUREMENT
8.1 VOUT vs ILOAD (with different VIN)
18
20
22
24
26
28
30
32
0 0,5 1
VO
UT
(V
)
Iload (A)
VOUT Vs ILOAD T=-60°C
30
50
150
400
600
18
20
22
24
26
28
30
32
0 0,5 1
VO
UT
(V
)
Iload (A)
VOUT Vs ILOAD T=25°C
30
50
150
400
600
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18
20
22
24
26
28
30
32
0 0,5 1
VO
UT
(V
)
Iload (A)
VOUT Vs ILOAD T=175°C
30
50
150
400
600
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8.2 VOUT vs POUT (with different VIN)
18
20
22
24
26
28
30
32
0 5 10 15 20 25 30
VO
UT
(V
)
POUT (W)
VOUT Vs POUT T=-60°C
30
50
150
400
600
18
20
22
24
26
28
30
32
0 5 10 15 20 25 30
VO
UT
(V
)
POUT (W)
VOUT Vs POUT T=25°C
30
50
150
400
600
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18
20
22
24
26
28
30
32
0 5 10 15 20 25 30
VO
UT
(V
)
POUT (W)
VOUT Vs POUT T=175°C
30
50
150
400
600
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8.3 VOUT vs VIN (with different ILOAD)
20
21
22
23
24
25
26
0 100 200 300 400 500 600
VO
UT
(V
)
VIN (V)
VOUT Vs VIN T=-60°C
0.1
0.2
0.5
1
1.3
18
19
20
21
22
23
24
25
26
0 100 200 300 400 500 600
VO
UT
(V
)
VIN (V)
VOUT Vs VIN T=25°C
0.1
0.2
0.5
1
1.3
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18
19
20
21
22
23
24
25
26
0 100 200 300 400 500 600
VO
UT
(V
)
VIN (V)
VOUT Vs VIN T=175°C
0.1
0.2
0.5
1
1.3
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9 RIPPLE MEASUREMENT
9.1 RIPPLE vs ILOAD (with different VIN)
9.2 RIPPLE vs VIN (with different ILOAD)
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
0 0,5 1 1,5
RIP
PL
E (
V)
ILOAD (A)
RIPPLE Vs ILOAD (@25°C)
30
50
150
400
600
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
0 100 200 300 400 500 600
RIP
PL
E (
V)
VIN (V)
RIPPLE Vs VIN (@25°C)
0.1
0.2
0.5
1
1.3
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10 DUTY CYCLE MEASUREMENT
10.1 DUTY CYCLE vs ILOAD (with different VIN)
10.2 DUTY CYCLE vs VIN(with different ILOAD)
0
10
20
30
40
50
60
70
80
90
100
0 0,5 1 1,5
DU
TY
CY
CL
E (
%)
ILOAD (A)
DUTY CYCLE Vs ILOAD (@25°C)
30
50
150
400
600
0
10
20
30
40
50
60
70
80
90
100
0 100 200 300 400 500 600
DU
TY
CY
CL
E (
%)
VIN (V)
DUTY CYCLE Vs VIN (@25°C)
0.1
0.2
0.5
1
1.3
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11 SYSTEM DESIGN GUIDELINES/LAYOUT RECOMMENDATION
11.1 Design consideration
Most sensitive external components and tracks connected to OCS, COMP, and FB should be very
carefully place close to the XTR30014 and in a non-noisy area.
Components connected to RT/SYNC (R, C) should be properly placed in order to avoid parasitic
capacitor which will change the choosy operate frequency.
FB, COMP and OCS terminals are sensitive to system noise. Layout these terminals with mini-
mum parasitic capacitance and avoid any possible coupling with SW, HDrv, LDrv, CKOUT and
PGOOD signals.
Noise on RT/SYNC could cause erratic behaviour of the internal clock generator. Avoid any pos-
sible coupling with SW, HDrv, LDrv, CKOUT and PGOOD signals. In case a capacitor is con-
nected to RT/SYNC to slow down the clock, connect the capacitor to a noiseless GND. Do not
connect this capacitor to PGND under any condition.
Notice that terminal OCS is relative to PGND (not GND).
When using “input voltage feed forward”, connect SWT to VIN through a resistor of at least
100Ω.
Printed board with internal layer reference GND and VDD will be preferred.
D1 and Q4 placed close to the transformer will optimize the efficiency (less power losses).
Appropriate track dimensions will help the electrical and thermal performance. Enlarge the Source
area for better thermal performance.
11.2 Typical Flyback Schematic
Schematic below is a typical flyback application circuit built around the XRT30014 with the compo-
nent names used in the layout Bill of Material.
The schematic could be provided in pdf format.
XTDB30007_Flyback_Application_E.1.2.pdf
11.3 Bill of Material
The BOM could be provided in an excel spreadsheet:
XTDB30007_Flyback_Application_E.1.2.xls
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12 BOARD PHOTOS
12.1 Board drawing
12.2 Photo
12.3 Thermal photo
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13 CONCLUSION
This power supply comply the specification in very harsh environment. All performances measured
are good as well as electrical (Iout, Vout) than Thermal (temperature resistance).
This power supply is an example of feasibility and can be adjusted for different output voltages. The
feedback of the XTR30014 and over-voltage protection should be adjusted to reach the voltage.
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14 IMPORTANT NOTICE & DISCLAIMER
EASii IC PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS),
DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DE-
SIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED,
INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABIL-
ITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY
INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with EASii IC products. You are solely
responsible for (1) selecting the appropriate EASii IC products for your application, (2) designing,
validating and testing your application, and (3) ensuring your application meets applicable standards,
and any other safety, security, or other requirements. These resources are subject to change without
notice. EASii IC grants you permission to use these resources only for development of an application
that uses the EASii IC products described in the resource. Other reproduction and display of these re-
sources is prohibited. No license is granted to any other EASii IC intellectual property right or to any
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nify EASii IC and its representatives against, any claims, damages, costs, losses, and liabilities arising
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15 CONTACT US
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