High Density Interconnect necessitates board test...

High Density Interconnect necessitates board test innovation

NK Chari

iNEMI Workshop on Board Assembly & Test Technology

August 25, 2014 to August 26, 2014

Unlocking measurement insights for 75 years

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Substrate & Package Technology Workshop, Toyama, Japan, April 22, 2014


• Proliferation of connected devices

• Each device will be connected to a wireless infrastructure

• Each device will be accessing content (massive back-end storage)

• Millions of servers will be used to support connection and content

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• Each connected device will have the computing power of a 1980s mainframe

squeezed into one IC

• ICs will most likely be massively integrated 3D IC

• Smallest footprint

• Shortest trace for highest speeds (GHz)

• Best thermal management

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• Connected devices will have the highest technology per square inch

• PCB real estate will be premium; more buried nets

• IC pin count constrained by footprint will drive smaller package pitch

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• IC package trends is not confined to consumer devices

• Infrastructure equipment share the same challenges

• Growth in IC package pin count

• Constrained IC footprint

• IC package pitch decreasing

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

1 2 3 4

# Pins (thousands)

Area/Pin (cm sq/pin)

2007 2010 2013 2014

IC Pin Count & Area/Pin

Pin Count

Pin Real Estate

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• Decreasing IC package pitch by 0.1mm yields >25% I/O count

http://www.smta.org/chapters/files/WI_Solberg_PoP_presentation.pdf2013 SMTA WI Chapter Meeting

+28.0% +29.2%

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http://www.smta.org/chapters/files/WI_Solberg_PoP_presentation.pdf

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• Memory IC package leads the pitch trend

• All connected device and infrastructure equipment has memory ICs

Next Generation PoP Technology for High IO Memory JuHoon Yoon, Amkor Technology Korea

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Trends in IC package pitch sizes are driven by handheld devices and the

number of units consumed will quickly drive the cost of packaging to its

lowest; making the package size attractive

2014 Device Packaging Conference

MOBILE PACKAGING AND INTERCONNECT

TRENDSBrandon Prior, Senior Consultant

PRISMARK PARTNERS LLC

No growth in

0.5mm and greater

pitch packages

<0.5mm pitch

packages growingPitch

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HDI Design Rules &

Microvia TechnologyJeroen Leinders

CADSTAR/Zuken

• More pcb traces will sink into the inner layers reducing electrical test

access on pcb surfaces

• 0.5mm pitch BGA

• Space for at most 1 trace between balls

• 0.4mm pitch BGA

• No space for trace between balls

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Post-Reflow AOI AXI ICT FCT


Current test strategy may not meet the challenges of testing HDI boards.

Building and testing boards with

the computing power of a 1980s

mainframe.

Inability to inspect

3D ICs and

increasing

percentage of hidden

joints.

Call accuracy to

separate joints

inside 3D ICs and the

attachment joint to

pcb.

Reducing test

access as more

traces migrate to

inner pcb layers.

Trade-off test time

and tester capacity

to recover test

coverage lost by

AOI, AXI and ICT.

Board Test Challenges for HDI boards

REQUIRED :

A complementary test solution. Optimum

test access but maximum test coverage.

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Rockchip 3288 Quad Core 1.8GHz

Mali-T764 3D GPU

HDMI, AV output, optical, RJ45,

Micro SD slot, USB host x 3, USB

slave x 1 Camera,


TV set-up box

CPU/SoC is at the ‘heart’ of the design; managing

all functions of all TV set-up boxes.

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Snapdragon 805

Quad-core Krait 450 2.7 GHz

telephone Adreno™ 420 GPU

4G LTE Advanced

H.264 (AVC) and H.265 (HEVC

USB 3.0, BT4.1


Smartphone


all functions of all smartphones.

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nVidia Tegra K1 2.3 GHz

NVIDIA 4-Plus-1™ Quad-Core

ARM Cortex-A15 "r3“192 NVIDIA CUDA® Cores


Tablet


all functions of all tablet pc.

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Freescale i.MX6Q: i.MX 6

4xARM® Cortex™-A9 up to 1.2 GHz per core

1 MB L2 cache

32 KB instruction and data caches

NEON SIMD media accelerator


Automotive

MCU/SoC is at the ‘heart’ of the design; managing

all functions of most automotive electronics.

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Intel Core i5-3427U 2.8GHz 3MB L3

Intel HD 4000 Graphics 1150MHz

4GB DDR3L-1333


Notebook

CPU is at the ‘heart’ of the design; managing all

functions of all notebook pc.

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Intel® Xeon® Processor E5-2690

8 cores, 20M Cache

8.00 GT/s Intel® QPI


Server

CPU is at the ‘heart’ of the design; managing all

functions of all server boards..

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Embedded Board Test (EBT) concept


RAMRAM

CPU/SoC

Power/Battery

Flash

MemoryRAM

Display Port/HDMI

I2C/G PIO/UART

USB

PCIe

SATA Keyboard/Keypad

LAN

WiFi

BT

eDP

MIPIAudio

Codec

Pwr

Mgmt

Monitor voltages

1. Check power is sequenced correctly2. Power up CPU/SoC3. Load boot ROM

a. Initialize Cache & DDR memories(train)b. Initialize CPU/SoC services and communication bus(discover devices)c. Establish communications with peripheral ICs(load drivers)d. Check the I/Os; if necessary with external devices

SD

x1149

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Intel Harris Beach

Customer Reference BoardTop side

CPU : Haswell ULT

No. Devices : 2,377

Bscan ICs : 2 (ULT-CPU+PCH, SensorHub)

No. Nets : 2,144

Electrical

Test Access : 42%

Test access?1. Power management circuit =15

2. CPU test mode, control and conditioning pins.

3. Boundary Scan pins = 18 (3 TAP)

Function Access

Power / Sleep 36

Compliance 10

BScan 18 (3 TAP)

Test mode 29

TOTAL 93

Embedded Board Test (EBT) test vehicle

Test Coverage?42%

4.4% of Nets

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Intel® Harris Beach CRB DOE

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BFT

Repair

(BFT)

EBT&

Program

Flying Pr

DOE process :Test Test Name Chain Name Remarks Coverage

x1149

Monitor ALL_SYS_PWRGD monitor power rail Voltage within +/- 10%

Monitor +VCCIN monitor power rail Voltage within +/- 10%

Monitor +V_VDDQ_VR monitor power rail Voltage within +/- 10%

Monitor +V_VDDQ_VTT monitor power rail Voltage within +/- 10%

idcode U9999_U9999 Haswell CPU Bscan CPU idcode

interconnect U9999_U9999 Haswell CPU Bscan ULT shorts only(cell monitoring)

idcode U9999P_U9999P Haswell PCH Bscan PCH idcode

interconnect_dot6 U9999_U9999 Haswell CPU Bscan ULT Dot6 pins

pullup_pulldown U9999_U9999 Haswell CPU Bscan ULT termination resistors

integrity U9999P_U9999P Haswell PCH Bscan ULT Bscan circuit

interconnect U9999P_U9999P Haswell PCH Bscan ULT shorts only(cell monitoring)

interconnect_dot6 U9999P_U9999P Haswell PCH Bscan ULT Dot6 pins

pullup_pulldown U9999P_U9999P Haswell PCH Bscan ULT termination resistors

sn_U8D3_SN U9999P_U9999P Silicon Nail test U8D3 SPI Flash

ce_J7 U9999P_U9999P CoverExtend test CET on connector J7

ce_J8 U9999P_U9999P CoverExtend test CET on connector J8

Recycle power Power_Up U9999_U9999 Recycle power Transit from BScan to SVT

SVT

Masterframe Intel® DFx* Abstraction Layer initialization

pmcstatus Check power on the CPU

pcieslotstatus Check PCH PCIe bus / devices

tcowatchdogtimer Check CPU watchdog timer

systimerroll Check CPU system timer

smbusstatus Check PCH SMBus / devices

hpetcounterroll Check CPU high precision event timer

CpuInfo Check CPU specification

pecistatus Check Platform Environment Control Interface

HDAudioStatus Check audio codec

gpiostatus Check PCH GPIO pins

hdmifunctional Check HDMI

memdata_inline Check DDR3 memory

usb3portstatus Check USB 3 devices

99 boards

Test Times :

Test Time(s)

x1149 7.65

Recycle Power 12.02

*SVT 136.31

TOTAL 155.98

*SVT test time totaled ~75s. Additional 60s

were due to :

1. Masterframe initialization ~40s.

2. Inherent overhead to get into reset

state(Checkpoint0) ~20s.

(x1149 + SVT)

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Intel® Harris Beach CRB DOE

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BOARD SVT FAILURE BFT BFT FAILURE / DIAGNOSTICS OBSERVATION

FZHB32500008 HDAudioStatus FAIL No sound HDAudio failed

FZHB32400230 hdmifunctional FAIL No HD output No VISUAL video output from HDMI port

FZHB32400243 usb3portstatus FAIL L7 component missing L7 part of HB USB circuit

FZHB32500133 usb3portstatus FAIL ICT Fail - L1 malfunction (sticker on board). L1 is at USB port0

Results

• 99 boards tested at Board Functional Test were re-tested at

the EBT station.

• EBT had 4 failures, when investigated further, were co-related

to Board Functional Test failures.

OBSERVATIONS:

• The value of EBT increases as ICT test access diminishes.

• Critical to monitor power signals; especially voltage rail sequencing during power-up.

• DFT is critical for the success of EBT implementation.

• Location of test access to manage test measurement paths (capacitance).

• Fixture may require dual stage to prevent impedance loading by probes.

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Embedded Board Test (EBT) integrated solution

Probe Alignment Plate

Probe Plate

Spring

FR4 PCB routed for probes

signals

CPU/SoC

x1149 Intel® ITP

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Fixture for

Intel® Haswell & Broadwell

CPU pcba

Keysight x1149 & Intel® SVT software

Intel® ITP podKeysight x1149


Embedded Board Test (EBT) integrated solution with

Keysight x1149 Boundary Scan and Intel® SVT

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Post-Reflow AOI AXI ICT FCT


Current test strategy may not meet the challenges of testing HDI boards.

Building and testing boards with

the computing power of a 1980s

mainframe.

Inability to inspect

3D ICs and

increasing

percentage of hidden

joints.

Call accuracy to

separate joints

inside 3D ICs and the

attachment joint to

pcb.

Reducing test

access as more

traces migrate to

inner pcb layers.

Trade-off test time

and tester capacity

to recover test

coverage lost by

AOI, AXI and ICT.

Board Test Challenges for HDI boards

REQUIRED :

A complementary test solution. Lowest

test access but maximum test coverage.

Test strategy for testing HDI boards.

DFT using a

complementary ICT

and EBT to recover

test coverage.

ICT+EBT pre-screen

structural and basic

functional defects.

FCT to focus on

performance test.

Embedded Board Test (EBT) recovers

structural test loss with minimal test

access requirements AND

complements ICT.

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TBE+ICTICT + EBT

ICT + EBT


Unlocking measurement insights

Thank You

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