High aspect-ratio InGaAs FinFETswith sub-20 nm fin width

Alon Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao and Jesús A. del Alamo

Microsystems Technology Laboratories, MITJune 15, 2016

Sponsors: DTRA (HDTRA 1-14-1-0057), NSF E3S STC (grant #0939514) Lam Research

Outline• Motivation• Process technology• Electrical characteristics• Late news• Conclusions

2

InGaAs planar Quantum-Well MOSFETs

• Superior electron transport properties in InGaAs• InGaAs planar MOSFET performance exceeds that

of High Electron Mobility Transistors (HEMT) 3

MIT MOSFETs

del Alamo, J-EDS 2016

InGaAs planar Quantum-Well MOSFETs -short-channel effects

• Short-channel effects limit scaling to Lg~40 nm• 3D transistors required for further scaling

4

Lin, IEDM 2014

0.01 0.1 1 10

100150200250300350400

S min (m

V/de

c)

Lg(µm)

Vds=0.5 V

tc ↓

tc=12 nm

3 nm

5

Intel Si Trigate MOSFETs

FinFETs

• FinFETs are use in modern state-of-the-art technologies • Good balance of SCE and high ON current per footprint

6

InGaAs FinFETs

Radosavljevic ,IEDM 2011 Kim, IEDM 2013

• Demonstrations to date: Wf ≥ 25 nm, ARc ≤ 1

Kim, TED 2014

Thathachary, VLSI 2015 Waldron, VLSI 2014

Wf~30 nm

Wf~50 nm

Wf~50 nm

Goal: Sub-20 nm Wf Self-aligned III-V FinFETs

• Deeply scaled fin width, gate length and gate oxide• High channel to fin width aspect ratio (ARc)• Self-aligned contacts • CMOS-compatible processes and materials in front-

end7

InAlAs

channel

capW/Mo

LgSiO2

HSQHigh -K

Hc

Wf

ARc = Hc/WfARf = Hf/Wf

Hf

Fin definition:Dry etch + Digital etch

8

30 nm

100 nm

8 nm

170 nm

• BCl3/SiCl4/Ar RIE of InGaAsnanostructures with smooth, vertical sidewalls and high aspect ratio (>10)

• Digital etch (DE): self-limiting O2 plasma oxidation + H2SO4oxide removal

25 nm

Device fabrication

9

30 nm In0.53Ga0.47As,Si doped 3e19 cm-3

4 nm InP stopper40 nm In0.53Ga0.47As,

undoped5 nm In0.52Al0.48As

Si δ-Doping: 4e12 cm-2

In0.52Al0.48As buffer

InP semi insulating substrate

• Highly doped cap• 40 nm thick channel layer• Delta doping underneath

Device fabrication

10

Wf directionLg direction

InAlAs

channelcap

W/MoSiO2

o Sputtered W/Mo contact o CVD SiO2 hard mask

Device fabrication

11

35 nm

SiO2

W/Mo

Wf directionLg direction

InAlAs

channelcap

W/MoSiO2 Lg

o Sputtered W/Mo contact o CVD SiO2 hard masko Gate lithographyo Gate recess (Dry):

SiO2/W/Moo Active area definition

Device fabrication

12

35 nm

SiO2

W/Mo

InPW/MoSiO2

20 nmInGaAs

60 nm

Wf directionLg direction

InAlAs

channelcap

W/MoSiO2 Lg

Lg

o Sputtered W/Mo contact o CVD SiO2 hard mask o Gate lithographyo Gate recess (Dry):

SiO2/W/Moo Active area definitiono Gate recess (Wet): Cap

etch

13

HSQ

HcHf

100 nm

Device fabricationo Sputtered Mo contact o CVD SiO2 hard masko Gate lithographyo Gate recess (Dry):

SiO2/W/Moo Active area definitiono Gate recess (Wet): Cap

etcho Fin Lithographyo Fin etch

14

HSQ

HcHf

High-k/Mo

100 nm

20 nm

Device fabricationo Sputtered W/Mo contact o CVD SiO2 hard masko Gate lithographyo Gate recess (Dry):

SiO2/W/Moo Active area definitiono Gate recess (Wet): Cap

etcho Fin lithographyo Fin etcho Digital etchingo ALD gate dielectric

depositiono Mo gate sputtering

Mo

HSQ

• Double gate FinFET• Al2O3/HfO2 , EOT = 1 nm

15

Via

SiO2

Gate hat

Device fabricationo Sputtered W/Mo contact o CVD SiO2 hard masko Gate lithographyo Gate recess (Dry):

SiO2/W/Moo Active area definitiono Gate recess (Wet): Cap

etcho Fin Lithographyo Fin etcho Digital etchingo ALD gate dielectric

depositiono Mo gate sputteringo Gate head photo and

patterno ILD1 depositiono Via openingo Pad formation

• Fin pitch 200 nm

• 10-50 fins/device

Long channel characteristics,Wf=22 nm, Lg=2 μm

16

• Slin=68 mV/dec

• Negligible DIBL

• Good electrostatic control over dry etched sidewalls

0.0 0.1 0.2 0.3 0.4 0.50

5

10

15

20

25

0 V 0.25 V

0.5 V

I d [µA

/µm

]

VDS [V]

VGS= 0.75 V

-0.2 0.0 0.2 0.4 0.6 0.81E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

DIBL~0

50 mV

I d [A/µm

]VGS [V]

Slin=68 mV/dec

VDS=500 mVAl2O3/HfO2EOT = 1 nm

17

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.80

200

400

600

800

1000

Wf=22 nmLg=30 nm

VDS=500mV

VGS [V]

I d [µA

/µm

]

0

400

800

1200

1600

gm [µ

S/µm

]

0.0 0.2 0.4 0.6 0.8 1.00

200

400

600

800

1000

1200 VGS= 0.75V

0.5

0.25

0

-0.25

I d [µA

/µm

]

VDS [V]

-0.5

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.61E-8

1E-7

1E-6

1E-5

1E-4

1E-3

DIBL=220 mV/V

VGS [V]

I d [A/µm

]Wf=22 nmLg=30 nm

VDS=500 mV

50 mV

S=140 mV/dec

170

• ARc~2• gm,max = 1.4 mS/µm at

VDS=0.5 V• Ron=170 Ω∙µm

Short channel characteristics,Wf=22 nm, Lg=30 nm

Hc

Current normalized by 2xHc

18

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.61E-10

1E-9

1E-8

1E-7

1E-6

1E-5Wf=7 nmLg=20 nm

VDS=500 mV

VGS [V]

I d [A/µm

]

50 mVS=120 mV/decDIBL~150

0.0 0.2 0.4 0.6 0.8 1.00

10

20

30

40 VGS= 0.75 V

0.5

0.25

0-0.25

I d [µA

/µm

]

VDS [V]

• ARc~6• Poor drive current Increased line edge

roughness for Wf<10 nm

Most aggressively scaled device,Wf=7 nm, Lg=20 nm

Lg and Wf scaling

19

10 100 10000

400800

120016000

400800

120016000

400800

120016000

400800

12001600

Lg [nm]

Wf=7 nm

Wf=12 nm

gm [µ

S/µm

]

Wf=17 nm

Wf=22 nm

• Lg ↓ gm ↑• Wf ↓ gm ↓

gm,max at VDS=0.5 V

Lg and Wf scaling

20

10 100 10000

501001502000

501001502000

501001502000

50100150200

Lg [nm]

Ssa

t [m

V/de

c]

Wf=7 nm

Wf=12 nm

Wf=17 nm

Wf=22 nm

gm,max at VDS=0.5 V

10 100 10000

400800

120016000

400800

120016000

400800

120016000

400800

12001600

Lg [nm]

Wf=7 nm

Wf=12 nm

gm [µ

S/µm

]

Wf=17 nm

Wf=22 nm

Ssat at VDS=0.5 V

• Lg ↓ gm ↑• Wf ↓ gm ↓

• Wf ↓ Lg @ onset of SCE↓

Lg and Wf scaling

21

10 100 10000

501001502000

501001502000

501001502000

50100150200

Lg [nm]

Sm

in [m

V/de

c]

Wf=7 nm

Wf=12 nm

Wf=17 nm

Wf=22 nm

gm,max at vDS=0.5 V

10 100 10000

400800

120016000

400800

120016000

400800

120016000

400800

12001600

Lg [nm]

Wf=7 nm

Wf=12 nm

gm [µ

S/µm

]

Wf=17 nm

Wf=22 nm

Ssat at VDS=0.5 V

• Lg ↓ gm ↑• Wf ↓ gm ↓• Wf ↓ Lg @ onset of SCE ↓

10 100 10000

1020304050050

1001502000

501001502000

50100150200

Lg [nm]

I on [µ

A/µm

]

Ioff=100 nA/µm

Wf=7 nm

Wf=12 nm

Wf=17 nm

Wf=22 nmcc

cc

cc

• Wf ↓ Lg @ max Ion ↓

Ion at Ioff=100 nA/μm

22

0 100 200 300 400 5000

5001000150020002500300035004000

12

22

17

Ron

[ Ω- µ

m]

Lg [nm]

Wf=7 nm

ON resistance scaling

• Wf ↓ Ron↑• For all Wf , Rsd=100 Ω∙µm• Extremely low series resistance due to contact first and

self-aligned approach

VT rolloff

23

0 400 800

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

Wf=12 nm

V T [V]

Wf=7 nm

0 400 800

Wf=22 nmWf=17 nm

Lg [nm]0 400 800

0 400 800

• Wf ↓ VT ↑ delta doping, quantization• Wf ↓ VT rolloff ↑ line edge roughness ?

A. Vardi, IEDM 2015

Benchmark

24

Physical gm:normalized by gate periphery

HC

Wf

• gm of Si ~ gm of III-V• III-V FinFET ARc≤1

Hc

WF

0 20 40 600.0

0.5

1.0

1.5

2.0

0.8

0.57

InGaAs FinFETs

5.34.3

Si FinFETsg m

[mS/µm

]

Wf [nm]

0.630.6

0.230.66

1

0.18

Benchmark

25

Physical gm:normalized by gate periphery

HC

Wf

Hc

WF

0 20 40 600.0

0.5

1.0

1.5

2.0

0.8

0.57

5.7

3.3

2.31.8

InGaAs FinFETs

5.34.3

Si FinFETsg m

[mS/µm

]

Wf [nm]

0.630.6

0.230.66

1

0.18

MITInGaAsFinFETs

• ARc>1 for the first time in III-V• Sub-20 nm Wf• Wf ↓ gm ↓

Our results:

Benchmark

26

0 20 40 600

5

10

15

20

0.570.8

5.7

3.32.31.8

InGaAs FinFETs

5.3

4.3Si FinFETs

g m/W

f [m

S/µm

]Wf [nm]

0.630.6

0.230.66 1

0.18

• Si >> III-V• MIT FinFETs > all other III-V good use of sidewall conductance

Our results improve the state-of-art

Physical gm: Footprint gm:normalized by fin width

0 20 40 600.0

0.5

1.0

1.5

2.0

0.8

0.57

5.7

3.3

2.31.8

InGaAs FinFETs

5.34.3

Si FinFETs

g m[m

S/µm

]

Wf [nm]

0.630.6

0.230.66

1

0.18

MITInGaAsFinFETs

Wf

For gm/Wf:

27

-0.4 -0.3 -0.2 -0.1 0 0.1 0.20

200

400

600

800

1000

VGS [V]

g m [ µ

S/ µ

m]

-0.4 -0.3 -0.2 -0.1 0 0.1 0.210-12

10-10

10-8

10-6

10-4

VGS [V]

I [A

/ µm

]

0 0.1 0.2 0.3 0.4 0.50

100

200

300

400

500

VDS [V]

I d [ µA

/ µm

]

Wf=7 nmLg=30 nmEOT=0.6 nm (HfO2)

VGS=-0.5 to 0.75 ΔVGS=0.25 V

gm max=0.9 mS/μm

S=100 mV/decId

Ig

DIBL=90 mV/V

Post-submission results

VDS=500 mV

50 mV

VDS=500 mV

50 mV

Benchmark with latest results

28

0 20 40 600

5

10

15

20

EOT=1 nm (HfO2/Al2O3) EOT=0.6 nm (HfO2)

0.570.8

5.7

3.32.31.8

InGaAs FinFETs

5.3

4.3Si FinFETs

g m/W

f [m

S/µm

]

Wf [nm]

0.630.6

0.230.66 1

0.18

0 20 40 600.0

0.5

1.0

1.5

2.0

0.8

0.57

5.7

3.3

2.31.8

InGaAs FinFETs

5.34.3

Si FinFETs

g m[m

S/µm

]

Wf [nm]

0.630.6

0.230.66

1

0.18

Physical gm: Footprint gm:

• New record results for sub-10 nm Wf InGaAs FinFETs

Conclusions

29

• Novel self-aligned gate-last FinFET:– Self-aligned gate to contact metals – CMOS process compatibility – Sub-10 nm fin width– ARc>1 for the first time in III-V– Double-gate FinFET

• Outstanding performance and short-channel effects in devices with Lg=30 nm and Wf=22 nm

• Demonstrated subthreshold swing of 68 mV/dec in long channel devices

Thank you !

30