Hidden Implications of the Momentum Built by National...

1Copyright © W. Maly

Hidden Implicationsof the Momentum Built by

National Technology Roadmap forSemiconductors:

The End of the Moore’s Law Era ?

Wojciech Maly Wojciech MalyDepartment of Electrical and ComputerDepartment of Electrical and Computer

EngineeringEngineeringCarnegie Mellon UniversityCarnegie Mellon University

Pittsburgh , PA 15213.Pittsburgh , PA 15213.


Objectives of the TalkObjectives of the Talk

To expose potential To expose potential weaknessweakness in current in currentmomentum of IC industry evolution.momentum of IC industry evolution.

To list and rank major To list and rank major challengeschallenges generated generatedby such a weakness.by such a weakness.


OutlineOutline

FF How IC industry has been evolving ?How IC industry has been evolving ?FF 1997 NTRS (SIA Roadmap) 1997 NTRS (SIA Roadmap)

FFKey assumptionsKey assumptionsFF Immediate implicationsImmediate implicationsFFCost analysisCost analysisFF ÒCost contradictionÓÒCost contradictionÓ

FFLonger range implications of 1997 NTRSLonger range implications of 1997 NTRSFF Change of Priorities Change of Priorities

FF Design for Manufacturability (DFM) Design for Manufacturability (DFM)FF Monolithic integration ? Monolithic integration ?FF Feature size and Memory size ? Feature size and Memory size ?


How IC industry has been evolving ?How IC industry has been evolving ?

BB

BB

BBBB

BB

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Min

imum

Fea

ture

Siz

e [m

icro

ns]

Year

FF Moore’s law:Moore’s law:

FF Minimum feature sizeMinimum feature size__

FF Transistor density Transistor density aa

FF Die sizeDie size aaFF Results: Results:

FF Performance Performance aa

FF Transistor cost Transistor cost __

FF Reliability Reliability aa

Revenue (Performance,t) - Cost(t) > 0Revenue (Performance,t) - Cost(t) > 0


How IC industry has been evolving ?How IC industry has been evolving ?

FF The NTRS has been a detailed implementation The NTRS has been a detailed implementationagenda of Moore’s Law.agenda of Moore’s Law.

FF The NTRS has been a “linear extrapolation” of the The NTRS has been a “linear extrapolation” of thetrends known from the past.trends known from the past.

FF The NTRS is a The NTRS is a “self-fulfilling prophecy”“self-fulfilling prophecy”..FF The NTRS captures evolution trends of IC industry. The NTRS captures evolution trends of IC industry.

SIA National Technology Roadmap SIA National Technology Roadmap for Semiconductors (NTRS)for Semiconductors (NTRS)


1997 NTRS Assumptions: Feature Size1997 NTRS Assumptions: Feature Size

OOOO

OOOO

OOOOOOOO

OOOO

OOOO

OOOO

��

��

��

��

��

��35

100

25019

96

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

Fea

ture

Siz

e [n

m]

Year

OOOO Technology Generation

�� Isolated Lines

300 mm 450 mm200 mm


1997 NTRS Assumptions: Memory Size1997 NTRS Assumptions: Memory Size

B

B

B

B

B

B

J

J

J J

J

J

J

64100

1000

10000

100000256000

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

Mem

ory

Size

[10

]

Year

B Introduction J Production Ramp

6


1997 NTRS Assumptions: 1997 NTRS Assumptions: Transistor DensityTransistor Density

Year

BBBBBBBB BBBB

BBBBBBBB

BBBBBBBB

��

��

��

��

HHHHHHHH HHHH HHHH

HHHHHHHH

HHHH

1

10

100

1000

10000

10000019

96

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

Tra

nsis

tor

Den

sity

[1

M/c

m

]

BBBB Memory �� MPU HHHH ASIC

2

1


1997 NTRS Assumptions: 1997 NTRS Assumptions: Die Size - DRAMDie Size - DRAM

Year

80100

1000

200019

9619

9719

9819

9920

0020

0120

0220

0320

0420

0520

0620

0720

0820

0920

1020

1120

1220

1320

1420

1520

1620

1720

18

Chi

p Si

ze [

mm

]

B Year 1 J Year 3 H Year 6

200

400

600

2

B

B BB

B

B

J

J JJ

J

J

H

HH

H

H

H

H

300 mm 450 mm200 mmB J

2


1997 NTRS Assumptions: 1997 NTRS Assumptions: Die Size - MPUDie Size - MPU

��

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

Year

80100

1000

2000

Chi

p Si

ze [

mm

]

Year 1 Year 3 Year 6

200

400

600

2

��

��

��

��

��

��

��

��

��

��

��

��

450 mm300 mm200 mm

2


1997 NTRS Assumptions: 1997 NTRS Assumptions: Cost per TransistorCost per Transistor

BB

BB

BB

B

JJ

JJ

JJ

J

HH

HH

HH

H

��

��

��

��

��

��

��

��

��

0.01

0.1

1

10

100

1000

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013C

ost

per

Bit

/Tra

nsis

tor

[mic

roce

nts]

Year

B DRAM - Year 1 J DRAM - Year 3 H DRAM - Year 6� MPU - Year 1 �� MPU - Year 3 �� MPU - Year 6

3


1997 NTRS Immediate Implications1997 NTRS Immediate Implications

FF Exponential increase in theExponential increase in thenumber of available transistors;number of available transistors;

FF Substantial increase in Substantial increase inperformance;performance;

FF Cost decrease (increase) ?Cost decrease (increase) ?



Investment

Functionality

Volume Sold

1998

ComplexityEvolution Spiral



Investment

Functionality

Volume Sold

1998

ComplexityEvolution Spiral Complexityand Cost

out of control???


Cost Analysis: Calculations PerformedCost Analysis: Calculations Performed

( Chip size) * ( Tr. density ) = Tr. per chip

( Cost per tr. ) * ( Tr. per chip) = "Affordable" cost per chip3

Historical costdata

extrapolatedinto the future

Cost whichmarket was

able to ÒaffordÓin the past


Cost Analysis: Calculations PerformedCost Analysis: Calculations Performed


( Cost per tr. ) * ( Tr. per chip) = "Affordable" cost per chip3

Historical costdata

extrapolatedinto the future

Cost whichmarket was

able to ÒaffordÓin the past

Maximum chipcost which

market should beable to ÒaffordÓ

in the future.


Cost Analysis: CostCost Analysis: Cost per Die - DRAM per Die - DRAM

B

BB

B

B

B

B

JJ J J

JJ

J

H H H H H H H0200

400600800

10001200140016001800

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

Chi

p C

ost

-DR

AM

- [$

]

Year



Cost Analysis: DiscussionCost Analysis: Discussion

FF The cost of memory chip has to grow The cost of memory chip has to growrapidly.rapidly.

FF By today’s system cost standards, memory By today’s system cost standards, memorychip price in the range chip price in the range above $200 above $200 seem toseem tobe unacceptable for most of the systems inbe unacceptable for most of the systems inthe mass market.the mass market.

The 1997 NTRS cost per bitassumptions may be too high for

DRAM die to be really affordable.

The 1997 NTRS cost per bitThe 1997 NTRS cost per bitassumptions may be too high forassumptions may be too high for

DRAM die to be really affordable.DRAM die to be really affordable.


Cost Analysis: Cost per Die - MPUCost Analysis: Cost per Die - MPU

��

��

��

��

0

100

200

300

400

500

600

700

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

Chi

p C

ost

-MP

U-

[$]

Year

�� Die - Year 1 �� Die - Year 3



FF Maximum MPU chip cost is expected to be very high.Maximum MPU chip cost is expected to be very high.FF The rate of die cost decrease needs to be high too. SuchThe rate of die cost decrease needs to be high too. Such

a die cost decrease is expected to be achieved bya die cost decrease is expected to be achieved byaggressive:aggressive:FF Yield increase (from 60% to 80%),Yield increase (from 60% to 80%),FF Die size decrease, Die size decrease,FF Wafer cost decrease Wafer cost decrease

Cost per transistor assumptions ofthe 1997 NTRS for the MPU die areon the borderline of affordability.

Cost per transistor assumptions ofCost per transistor assumptions ofthe 1997 NTRS for the MPU die arethe 1997 NTRS for the MPU die areon the borderline of affordability.on the borderline of affordability.


Cost Analysis: Performed CalculationsCost Analysis: Performed Calculations


( Cost per tr. ) * ( Tr. per chip) = "Affordable" cost per chip

Wafer area

Chip size=

( )*( "Affordable" cost per chip) =

(Yield) * ( ) =

"Affordable" cost per wafer

Number of good chips per wafer

Number of good chips per wafer

Number of chipsper wafer

per waferNumber of chips

"Affordable" cost per wafer

( Number of masks ) * ( Wafer area)

Cost per mask per cm "acceptable”by the market

=2


Cost per cm per layer - DRAMCost per cm per layer - DRAM22

B

B

BB

BJ

0000....4444

1111

5555

3333

2222

Year

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

B J H DRAM Year 6

Man

ufac

turi

ng C

ost

[$/c

m

]2

DRAM Year 3DRAM Year 1

J

J

J J J JJ

H

H

H H HH

H

BB

200 mm 300 mm

450 mm


Cost per cm per layer - MPUCost per cm per layer - MPU22

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

Man

ufac

turi

ng C

ost

[$/c

m

]

Year

MPU Year 1 MPU Year 3

��

��

2

��

��

��

��

200 mm 300 mm 450 mm

0000....4444

1111

5555

3333

2222��



FF Cost of manufacturing is expected to stay on Cost of manufacturing is expected to stay onthe unchanged level.the unchanged level.

FF Costs of key processing steps is likely to be Costs of key processing steps is likely to bemore expensive:more expensive:FFNew lithography paradigms;New lithography paradigms;FFDefect learning;Defect learning;FFTest;Test;

The 1997 NTRS cost per transistorassumptions do not permit any

increase of cost of manufacturing.

The 1997 NTRS cost per transistorThe 1997 NTRS cost per transistorassumptions do not permit anyassumptions do not permit any

increase of cost of manufacturing.increase of cost of manufacturing.


1997 NTRS Cost Contradiction1997 NTRS Cost Contradiction

FFFrom the maximum acceptable dieFrom the maximum acceptable diecost standpoint, the NTRScost standpoint, the NTRSassumptions about “affordable” assumptions about “affordable” costcostper transistor are not aggressiveper transistor are not aggressiveenoughenough (too low a rate of cost(too low a rate of costdecrease especially for memory if thedecrease especially for memory if thecost per chip is supposed to stay in acost per chip is supposed to stay in areasonable range by today'sreasonable range by today'sstandards).standards).


1997 NTRS Cost Contradiction1997 NTRS Cost Contradiction

FFFrom the cost of manufacturing pointFrom the cost of manufacturing pointof view the NTRS assumptions aboutof view the NTRS assumptions about“affordable” “affordable” transistor cost reductiontransistor cost reductionare too aggressiveare too aggressive (by failing to provide(by failing to providethe cost “safety margin” needed tothe cost “safety margin” needed toaddress all new deep submicron eraaddress all new deep submicron erachallenges).challenges).


Longer Range Implications of 1997 NTRS:Longer Range Implications of 1997 NTRS:The end of Moore’s Law ?The end of Moore’s Law ?

Complexity

Investment

Functionality

Volume Sold

?

1998

Evolution Spiral Cost out ofcontrol !

The 1997 NTRS COSTCONTRADICTION may become a

show-stopper for Moore’s Law.

The 1997 NTRS COSTThe 1997 NTRS COSTCONTRADICTION may become aCONTRADICTION may become a

show-stopper for Moore’s Law.show-stopper for Moore’s Law.


OutlineOutline

FF How IC industry has been evolving ? How IC industry has been evolving ?FF 1997 NTRS (SIA Roadmap) 1997 NTRS (SIA Roadmap)

FFKey assumptionsKey assumptionsFF Immediate implicationsImmediate implicationsFFCost analysisCost analysisFF ÒCost contradictionÓÒCost contradictionÓ

FFLonger range implications of 1997 NTRSLonger range implications of 1997 NTRSFF Change of Priorities Change of Priorities

FF Design for Manufacturability (DFM) Design for Manufacturability (DFM)FF Monolithic integration ? Monolithic integration ?FF Feature size and Memory size ? Feature size and Memory size ?


Longer Range Implications of 1997 NTRS:Longer Range Implications of 1997 NTRS: Change of Priorities Change of Priorities

FF Decrease of transistor size Decrease of transistor sizeFF LithographyLithography

FF Interconnect InterconnectFF CopperCopperFF Low k dielectricLow k dielectric

FF Design&TestDesign&TestFF IP reuseIP reuseFF VerificationVerification

Current key challenges of IC industryCurrent key challenges of IC industryCurrent key challenges of IC industry

Top performance !

Time-to-market !


Implications of 1997 NTRS:Implications of 1997 NTRS: Change of Priorities Change of Priorities

FF Decrease of wafer cost Decrease of wafer costFF Simplified processesSimplified processes

FF Higher volumesHigher volumes

FF End of monolithic integrationEnd of monolithic integrationFF Better manufacturability Better manufacturability

FF Design for ManufacturabilityDesign for ManufacturabilityFF Rapid yield rampingRapid yield rampingFF Less aggressive introduction ofLess aggressive introduction of

new technologiesnew technologies

Cost Effectiveness !

Near future top challenges of IC industryNear future top challenges of IC industryNear future top challenges of IC industry


IC Design-Manufacturing Interface : IC Design-Manufacturing Interface : PastPast

SiliconFoundry

CompleteDesign&Test

Capability

IP Assembly


IC Design-Manufacturing Interface : IC Design-Manufacturing Interface : TodayToday

SiliconFoundry

SiliconFoundry

“i+2”

SiliconFoundry

“i+2”

CompleteDesign&Test

Capability

FablessDesign

House “k”

IP Assembly


IC Design-Manufacturing Interface : IC Design-Manufacturing Interface : Next 3 YearsNext 3 Years

Silicon Foundry “i” SiliconFoundry “i+1”

SiliconFoundry “i+1”

SiliconFoundry

“i+2”

SiliconFoundry

“i+2”

CompleteDesign&Test

Capability

IP Bank “i”

FablessDesign

House “k”

IP AssemblyHouse “k”

IP Assembly


IC Design-Manufacturing Interface : IC Design-Manufacturing Interface : Next 3 -10 YearsNext 3 -10 Years



SiliconFoundry

“i+2”

SiliconFoundry

“i+2”

CompleteDesign&Test

Capability

IP Bank “i”

IP Bank “j”IP Bank “j” IP Bank“j+1”IP Bank“j+1”

FablessDesign

House “k”

Fabless DesignHouse “x”

Fabless DesignHouse “x+1”

IP AssemblyHouse “z+1”

FablessDesign

House “x”

IP Market


IP Assembly


Higher VolumeHigher Volume

200 2,000 20,000 200,000 [$]

Log(cost)

# of systems built

1980s1990s



10 100 1,000 10,000

#of systems built

1980s

1990s

#of ICs per systems built



1001,000

10,000

Price of the system sold in high volume

100,0001,000,000

1960s 1970s 1980s 1990s

101

0.1

[$]



1001,000

10,000

Cost of a single IC

100,0001,000,000

1960s 1970s 1980s 1990s

101

0.1

[$]



1001,000

10,000

Price of the system sold inhigh volume

and cost of a single ICThe END of Moore’s Law !

100,0001,000,000

1960s 1970s 1980s 1990s

101

0.1?

[$]


Longer Range Implications of 1997 NTRS:Longer Range Implications of 1997 NTRS:The end of Moore’s Law ?The end of Moore’s Law ?

Complexity

Investment

Functionality

Volume Sold

?

1998

Evolution Spiral Cost out ofcontrol !

The 1997 NTRS COSTCONTRADICTION will become a

show-stopper for Moore’s Law.

The 1997 NTRS COSTThe 1997 NTRS COSTCONTRADICTION will become aCONTRADICTION will become a

show-stopper for Moore’s Law.show-stopper for Moore’s Law.


End of Monolithic IntegrationEnd of Monolithic Integration

DRAMDRAM

ROMROM

Current vision:

SYSTEM onSINGLECHIP ! ?but …..

Current vision:

SYSTEM onSINGLECHIP ! ?but …..



DRAMDRAM

ROMROM

Need forintegration ofMixedTechnologies:EmbeddedMemories

Need forintegration ofMixedTechnologies:EmbeddedMemories



Very selective usageof newesttechnologies:“Smallest featuresize”

Very selective usageof newesttechnologies:“Smallest featuresize”



Man

ufac

turi

ng C

ost

[$/c

m

] MPU Year 1 MPU Year 3�� 2

1997

1999

2001

2003

2005

2007

2009

2011

2013

2015

0000....4444

1111

5555

2222

��

��

��

Year



System on the chipmay be:System on the chipmay be:

FF MoreMoreexpensive toexpensive tofabricate;fabricate;

FF More difficultMore difficultto design;to design;

FF IncompatibleIncompatiblewith of ÒIPwith of ÒIPAssemblyAssemblyMarketÓMarketÓ


IC Design-Manufacturing Interface : IC Design-Manufacturing Interface : Next 3 -10 YearsNext 3 -10 Years



SiliconFoundry

“i+2”

SiliconFoundry

“i+2”

CompleteDesign&Test

Capability

IP Bank “i”

IP Bank “j”IP Bank “j” IP Bank“j+1”IP Bank“j+1”

FablessDesign

House “k”

Fabless DesignHouse “x”

Fabless DesignHouse “x+1”

IP AssemblyHouse “z+1”

FablessDesign

House “x”

IP Market


IP Assembly


2.5 D System Integration2.5 D System Integration

High Performance and High Cost

Modest Performance and Low Cost



Communication Channel

“Exotic” Technology (Sensors/MEMS)



Embedded, Stackable DRAM


Design for ManufacturabilityDesign for Manufacturability

Prediction of Defect

Characteristics

Prediction of Market

Conditions

Price-Performance Trade-offs

Cost Modeling

Cost Accounting

Yield/ Performance

Modeling

Cost-Performance Trade-offs

DFM = Profit Maximization

Prediction of Process

Instabilities

Optimization of

Optimization of


Lithography LimitationsLithography Limitations

0.4

1995

1997

1999

2001

2003

2006

K1

Fact

or (

R*N

A/λ

)

Year

6666

0.35 0.25 0.18 0.15 0.13 0.10

0.55 0.60 0.70 0.70 0.70 0.70

F. Size

NA

0.5

0.6

0.7

0.8

6666 6666

6666

SSSS SSSS

6666

6666

6666

i-line

KrF(248 nm) ArF

(193 nm)

Difficult

Ex. Difficult

H. Watanabe1998 VLSI Technology Symposium


Alternative Assumptions: Feature SizeAlternative Assumptions: Feature Size

35

100

25019

96

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

Fea

ture

Siz

e [n

m]

Year

300 mm 450 mm200 mm

66666

6666

6666

6666

6 77777777

1997 NTRS

Possible Scenario

6

7777

77776

7777

180 nm180 nm150 nm


B

Alternative Assumptions: Memory SizeAlternative Assumptions: Memory Size

B

B B B B B

J

J

J J J J

64100

1000

10000

100000256000

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

Mem

ory

Size

[10

]

Year

B Introduction J Production Ramp

6

J


Alternative Assumptions: Alternative Assumptions: Transistor DensityTransistor Density

BBBBBBBB BBBB BBBB BBBB BBBB BBBB

��

1

10

100

1000

10000

100000

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013T

rans

isto

r D

ensi

ty S

ize

[1/c

m

]

Year

BBBB Memory �� MPU

2


Alternative Assumptions: Memory SizeAlternative Assumptions: Memory Size

Year

80100

1000

2000

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

Chi

p Si

ze [

mm

]


200

400

600

2

B200

BB

1Gb

J

H

HJ

J

256 Mb

H HH


Alternative Assumptions: Alternative Assumptions: Cost per TransistorCost per Transistor

BB B

��

��

��

0.01

0.1

1

10

100

1000

1000019

96

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013C

ost p

er B

it/T

rans

isto

r [m

icro

cent

s]

Year

B DRAM - Year 1 J DRAM - Year 3 H DRAM - Year 6� MPU - Year 1 �� MPU - Year 3 �� MPU - Year 6

��

��

J J BJHBJH BJH BJH BJH BJH


Alternative Assumptions: Alternative Assumptions: Cost per Die - DRAMCost per Die - DRAM

BBB B B B

B

B B B B B B B B BJ

J

J J

J

J J J J J J J J J J JH

H H H H H H H H H H H H H H H

0

50

100

150

200

250

300

350

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

Die

Cos

t -D

RA

M-

[$]

Year



ConclusionsConclusions

FF Current momentum of IC Industry may Current momentum of IC Industry maylead to a “lead to a “severe cost contradictionsevere cost contradiction”.”.

FFSuch a cost contradiction will requireSuch a cost contradiction will requiredramatic dramatic reshuffling of priorities reshuffling of priorities thatthatguide IC industry.guide IC industry.

FFAchieving high levels of Achieving high levels of manufacturing costmanufacturing costeffectiveness effectiveness will become priority #1.will become priority #1.


DetailsDetails

http://www.ece.cmu.edu/~maly/circuits.htmlhttp://www.ece.cmu.edu/~maly/circuits.html


Implications of 1997 NTRS Cost ContradictionImplications of 1997 NTRS Cost Contradiction

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

Man

ufac

turi

ng C

ost [

$/cm

]

Year

MPU Year 1 MPU Year 3

��

��

2

��

��

��

��

200 mm 300 mm 450 mm

0000....4444

1111

5555

3333

2222��

B

B

BB

BJ

0000....4444

1111

5555

3333

2222

Year

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018B J H DRAM Year 6

Man

ufac

turi

ng C

ost [

$/cm

]2

DRAM Year 3DRAM Year 1

J

J

J J J JJ

H

H

H H HH

H

BB

200 mm 300 mm

450 mm

B

BB

B

B

B

B

JJ J J

JJ

J

H H H H H H H0200

400600

80010001200140016001800

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

Chi

p C

ost

-DR

AM

- [$

]

Year


��

��

��

��

0

100

200

300

400

500

600

700

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

Chi

p C

ost

-MP

U-

[$]

Year

�� Die - Year 1 �� Die - Year 3

Hidden Implications of the Momentum Built by National...

Documents

Transcript of Hidden Implications of the Momentum Built by National...